From: Jim Grosbach Date: Wed, 18 Jan 2012 21:54:09 +0000 (+0000) Subject: Rename pattern for clarity. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=a2ee0fa3ee4ae46c3dc655a5a57e9db539912e14;p=oota-llvm.git Rename pattern for clarity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148422 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index d55b08dc53e..30aa424343c 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -672,10 +672,9 @@ def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, } // FIXME: Remove this entry when the above ldr.n workaround is fixed. -// For disassembly use only. -def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, - "ldr", "\t$Rt, $addr", - [/* disassembly only */]>, +// For assembly/disassembly use only. +def tLDRpciASM : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, + "ldr", "\t$Rt, $addr", []>, T1Encoding<{0,1,0,0,1,?}> { // A6.2 & A8.6.59 bits<3> Rt;