From: Johnny Chen <johnny.chen@apple.com>
Date: Fri, 25 Mar 2011 22:19:07 +0000 (+0000)
Subject: Fix DisassembleThumb2DPReg()'s handling of RegClass.  Cannot hardcode GPRRegClassID.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=a2755b9829affb1c2ac07d7710228e80d222f588;p=oota-llvm.git

Fix DisassembleThumb2DPReg()'s handling of RegClass.  Cannot hardcode GPRRegClassID.
Also add some test cases.

rdar://problem/9189829


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128304 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
index a238306dd15..d08e98f511e 100644
--- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
+++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
@@ -1947,25 +1947,25 @@ static bool DisassembleThumb2DPReg(MCInst &MI, unsigned Opcode, uint32_t insn,
   OpIdx = 0;
 
   assert(NumOps >= 2 &&
-         OpInfo[0].RegClass == ARM::rGPRRegClassID &&
-         OpInfo[1].RegClass == ARM::rGPRRegClassID &&
+         OpInfo[0].RegClass > 0 &&
+         OpInfo[1].RegClass > 0 &&
          "Expect >= 2 operands and first two as reg operands");
 
   // Build the register operands, followed by the optional rotation amount.
 
-  bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::rGPRRegClassID;
+  bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass > 0;
 
-  MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
+  MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
                                                      decodeRs(insn))));
   ++OpIdx;
 
   if (ThreeReg) {
-    MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
+    MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B,OpInfo[OpIdx].RegClass,
                                                        decodeRn(insn))));
     ++OpIdx;
   }
 
-  MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
+  MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
                                                      decodeRm(insn))));
   ++OpIdx;
 
diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt
index eeb8dd0f367..f5775b50449 100644
--- a/test/MC/Disassembler/ARM/thumb-tests.txt
+++ b/test/MC/Disassembler/ARM/thumb-tests.txt
@@ -172,3 +172,12 @@
 
 # CHECK:	ldr.w	r5, [r6, #30]
 0x56 0xf8 0x1e 0x56
+
+# CHECK:	sel	r7, r3, r5
+0xa3 0xfa 0x85 0xf7
+
+# CHECK:	lsl.w	r7, r3, r5
+0x03 0xfa 0x05 0xf7
+
+# CHECK:	adds.w	r7, r3, r5
+0x13 0xeb 0x05 0x07