From: Colin LeMahieu <colinl@codeaurora.org>
Date: Wed, 10 Dec 2014 18:24:16 +0000 (+0000)
Subject: [Hexagon] Adding JR class predicated call reg instructions.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=9f3b3bca89fbc45d23575cfc4d48bf292c0ca1cf;p=oota-llvm.git

[Hexagon] Adding JR class predicated call reg instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223933 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td
index 40d30dea043..fc3da5a3425 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -1383,6 +1383,34 @@ multiclass JMPR_base<string BaseOp> {
   }
 }
 
+let isCall = 1, hasSideEffects = 1 in
+class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
+               dag InputDag = (ins IntRegs:$Rs)>
+  : JRInst<(outs), InputDag,
+      !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
+                                 "if ($Pu) callr $Rs"),
+                                 "callr $Rs"),
+      [], "", J_tc_2early_SLOT2> {
+    bits<5> Rs;
+    bits<2> Pu;
+    let isPredicated = isPred;
+    let isPredicatedFalse = isPredNot;
+
+    let IClass = 0b0101;
+    let Inst{27-25} = 0b000;
+    let Inst{24-23} = !if (isPred, 0b10, 0b01);
+    let Inst{22} = 0;
+    let Inst{21} = isPredNot;
+    let Inst{9-8} = !if (isPred, Pu, 0b00);
+    let Inst{20-16} = Rs;
+
+  }
+
+let Defs = VolatileV3.Regs, isCodeGenOnly = 0 in {
+  def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
+  def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
+}
+
 let isTerminator = 1, hasSideEffects = 0 in {
 let isBranch = 1 in
 defm JMP : JMP_base<"JMP">, PredNewRel;
diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.td b/lib/Target/Hexagon/HexagonRegisterInfo.td
index 82b417ebbf7..a7646dc7cc3 100644
--- a/lib/Target/Hexagon/HexagonRegisterInfo.td
+++ b/lib/Target/Hexagon/HexagonRegisterInfo.td
@@ -145,6 +145,14 @@ def CRRegs : RegisterClass<"Hexagon", [i32], 32,
   let Size = 32;
 }
 
+def VolatileV3 {
+  list<Register> Regs = [D0, D1, D2, D3, D4, D5, D6, D7,
+                         R28, R31,
+                         P0, P1, P2, P3,
+                         M0, M1,
+                         LC0, LC1, SA0, SA1, USR_OVF];
+}
+
 def PositiveHalfWord : PatLeaf<(i32 IntRegs:$a),
 [{
   return isPositiveHalfWord(N);
diff --git a/test/MC/Disassembler/Hexagon/jr.txt b/test/MC/Disassembler/Hexagon/jr.txt
new file mode 100644
index 00000000000..97515151ab5
--- /dev/null
+++ b/test/MC/Disassembler/Hexagon/jr.txt
@@ -0,0 +1,6 @@
+# RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s
+
+0x00 0xc1 0x15 0x51
+# CHECK: if (p1) callr r21
+0x00 0xc3 0x35 0x51
+# CHECK: if (!p3) callr r21