From: Jim Grosbach Date: Wed, 7 Oct 2009 22:49:41 +0000 (+0000) Subject: reverting thumb1 scavenging default due to test failure while I figure out what's up. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=9f3a559dff691bc1ed85089cb0870cf30a4a2d96;p=oota-llvm.git reverting thumb1 scavenging default due to test failure while I figure out what's up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83501 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h index 390b95fbe2f..e2a02fd2cb3 100644 --- a/include/llvm/Target/TargetRegisterInfo.h +++ b/include/llvm/Target/TargetRegisterInfo.h @@ -561,12 +561,6 @@ public: return false; } - /// requiresFrameIndexScavenging - returns true if the target requires post - /// PEI scavenging of registers for materializing frame index constants. - virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { - return false; - } - /// hasFP - Return true if the specified function should have a dedicated /// frame pointer register. For most targets this is true only if the function /// has variable sized allocas or if frame pointer elimination is disabled. diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp index 896689cc1ec..55298a4dded 100644 --- a/lib/CodeGen/PrologEpilogInserter.cpp +++ b/lib/CodeGen/PrologEpilogInserter.cpp @@ -44,6 +44,16 @@ char PEI::ID = 0; static RegisterPass X("prologepilog", "Prologue/Epilogue Insertion"); +// FIXME: For now, the frame index scavenging is off by default and only +// used by the Thumb1 target. When it's the default and replaces the current +// on-the-fly PEI scavenging for all targets, requiresRegisterScavenging() +// will replace this. +cl::opt +FrameIndexVirtualScavenging("enable-frame-index-scavenging", + cl::Hidden, + cl::desc("Enable frame index elimination with" + "virtual register scavenging")); + /// createPrologEpilogCodeInserter - This function returns a pass that inserts /// prolog and epilog code, and eliminates abstract frame references. /// @@ -56,7 +66,6 @@ bool PEI::runOnMachineFunction(MachineFunction &Fn) { const Function* F = Fn.getFunction(); const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL; - FrameIndexVirtualScavenging = TRI->requiresFrameIndexScavenging(Fn); // Get MachineModuleInfo so that we can track the construction of the // frame. diff --git a/lib/CodeGen/PrologEpilogInserter.h b/lib/CodeGen/PrologEpilogInserter.h index 030922a0265..ee759e8622c 100644 --- a/lib/CodeGen/PrologEpilogInserter.h +++ b/lib/CodeGen/PrologEpilogInserter.h @@ -95,11 +95,6 @@ namespace llvm { // functions. bool ShrinkWrapThisFunction; - // Flag to control whether to use the register scavenger to resolve - // frame index materialization registers. Set according to - // TRI->requiresFrameIndexScavenging() for the curren function. - bool FrameIndexVirtualScavenging; - // When using the scavenger post-pass to resolve frame reference // materialization registers, maintain a map of the registers to // the constant value and SP adjustment associated with it. diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index 7dc8e6053ff..f07c056a87d 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -37,6 +37,11 @@ #include "llvm/Support/raw_ostream.h" using namespace llvm; +// FIXME: This cmd line option conditionalizes the new register scavenging +// implemenation in PEI. Remove the option when scavenging works well enough +// to be the default. +extern cl::opt FrameIndexVirtualScavenging; + Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &sti) : ARMBaseRegisterInfo(tii, sti) { @@ -79,13 +84,7 @@ Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const { bool Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { - return true; -} - -bool -Thumb1RegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) - const { - return true; + return FrameIndexVirtualScavenging; } bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const { @@ -129,7 +128,13 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, unsigned LdReg = DestReg; if (DestReg == ARM::SP) { assert(BaseReg == ARM::SP && "Unexpected!"); - LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass); + if (FrameIndexVirtualScavenging) { + LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass); + } else { + LdReg = ARM::R3; + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12) + .addReg(ARM::R3, RegState::Kill); + } } if (NumBytes <= 255 && NumBytes >= 0) @@ -154,6 +159,10 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, else MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); AddDefaultPred(MIB); + + if (!FrameIndexVirtualScavenging && DestReg == ARM::SP) + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R3) + .addReg(ARM::R12, RegState::Kill); } /// calcNumMI - Returns the number of instructions required to materialize @@ -626,6 +635,7 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, else // tLDR has an extra register operand. MI.addOperand(MachineOperand::CreateReg(0, false)); } else if (Desc.mayStore()) { + if (FrameIndexVirtualScavenging) { VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass); assert (Value && "Frame index virtual allocated, but Value arg is NULL!"); *Value = Offset; @@ -648,6 +658,52 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MI.addOperand(MachineOperand::CreateReg(FrameReg, false)); else // tSTR has an extra register operand. MI.addOperand(MachineOperand::CreateReg(0, false)); + } else { + // FIXME! This is horrific!!! We need register scavenging. + // Our temporary workaround has marked r3 unavailable. Of course, r3 is + // also a ABI register so it's possible that is is the register that is + // being storing here. If that's the case, we do the following: + // r12 = r2 + // Use r2 to materialize sp + offset + // str r3, r2 + // r2 = r12 + unsigned ValReg = MI.getOperand(0).getReg(); + unsigned TmpReg = ARM::R3; + bool UseRR = false; + if (ValReg == ARM::R3) { + BuildMI(MBB, II, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12) + .addReg(ARM::R2, RegState::Kill); + TmpReg = ARM::R2; + } + if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) + BuildMI(MBB, II, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12) + .addReg(ARM::R3, RegState::Kill); + if (Opcode == ARM::tSpill) { + if (FrameReg == ARM::SP) + emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, + Offset, false, TII, *this, dl); + else { + emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); + UseRR = true; + } + } else + emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, + *this, dl); + MI.setDesc(TII.get(ARM::tSTR)); + MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); + if (UseRR) // Use [reg, reg] addrmode. + MI.addOperand(MachineOperand::CreateReg(FrameReg, false)); + else // tSTR has an extra register operand. + MI.addOperand(MachineOperand::CreateReg(0, false)); + + MachineBasicBlock::iterator NII = next(II); + if (ValReg == ARM::R3) + BuildMI(MBB, NII, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R2) + .addReg(ARM::R12, RegState::Kill); + if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) + BuildMI(MBB, NII, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R3) + .addReg(ARM::R12, RegState::Kill); + } } else assert(false && "Unexpected opcode!"); diff --git a/lib/Target/ARM/Thumb1RegisterInfo.h b/lib/Target/ARM/Thumb1RegisterInfo.h index bb7a6199d10..8d9efd9259c 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.h +++ b/lib/Target/ARM/Thumb1RegisterInfo.h @@ -41,7 +41,6 @@ public: getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const; bool requiresRegisterScavenging(const MachineFunction &MF) const; - bool requiresFrameIndexScavenging(const MachineFunction &MF) const; bool hasReservedCallFrame(MachineFunction &MF) const;