From: Chris Lattner <sabre@nondot.org>
Date: Wed, 15 Jan 2003 21:14:01 +0000 (+0000)
Subject: Adjust to new interfaces
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=9d4ed15c9ec97573703247fb4e0d3d8816eb0ef0;p=oota-llvm.git

Adjust to new interfaces


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5314 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp b/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
index d49b1d66398..f3c22e9898b 100644
--- a/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
+++ b/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
@@ -6,7 +6,7 @@
 
 #include "llvm/CodeGen/LiveRangeInfo.h"
 #include "RegAllocCommon.h"
-#include "llvm/CodeGen/RegClass.h"
+#include "RegClass.h"
 #include "llvm/CodeGen/IGNode.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineFunction.h"
@@ -16,6 +16,8 @@
 #include "Support/SetOperations.h"
 using std::cerr;
 
+unsigned LiveRange::getRegClassID() const { return getRegClass()->getID(); }
+
 LiveRangeInfo::LiveRangeInfo(const Function *F, const TargetMachine &tm,
 			     std::vector<RegClass *> &RCL)
   : Meth(F), TM(tm), RegClassList(RCL), MRI(tm.getRegInfo()) { }
@@ -93,7 +95,8 @@ LiveRangeInfo::createNewLiveRange(const Value* Def, bool isCC /* = false*/)
   LiveRangeMap[Def] = DefRange;           // and update the map.
 
   // set the register class of the new live range
-  DefRange->setRegClass(RegClassList[MRI.getRegClassIDOfValue(Def, isCC)]);
+  DefRange->setRegClass(RegClassList[MRI.getRegClassIDOfType(Def->getType(),
+                                                             isCC)]);
 
   if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
     cerr << "  Creating a LR for def ";
@@ -280,7 +283,6 @@ void LiveRangeInfo::coalesceLRs()
 	      continue;
 
 	    if (MRI.getRegType(LROfDef) == MRI.getRegType(LROfUse)) {
-
 	      // If the two RegTypes are the same
 	      if (!RCOfDef->getInterference(LROfDef, LROfUse) ) {
 
diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index 724dbc7744a..007d0758969 100644
--- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -6,8 +6,8 @@
 
 #include "llvm/CodeGen/RegisterAllocation.h"
 #include "RegAllocCommon.h"
+#include "RegClass.h"
 #include "llvm/CodeGen/IGNode.h"
-#include "llvm/CodeGen/RegClass.h"
 #include "llvm/CodeGen/PhyRegAlloc.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineInstrAnnot.h"
@@ -654,7 +654,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
   MachineOperand& Op = MInst->getOperand(OpNum);
   bool isDef =  MInst->operandIsDefined(OpNum);
   bool isDefAndUse =  MInst->operandIsDefinedAndUsed(OpNum);
-  unsigned RegType = MRI.getRegType( LR );
+  unsigned RegType = MRI.getRegType(LR);
   int SpillOff = LR->getSpillOffFromFP();
   RegClass *RC = LR->getRegClass();
   const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
@@ -888,7 +888,7 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
       if (MInst->getOperandType(OpNum) == MachineOperand::MO_VirtualRegister || 
           MInst->getOperandType(OpNum) == MachineOperand::MO_CCRegister)
         if (const Value* Val = Op.getVRegValue())
-          if (MRI.getRegClassIDOfValue(Val) == RC->getID())
+          if (MRI.getRegClassIDOfType(Val->getType()) == RC->getID())
             if (Op.getAllocatedRegNum() == -1)
               if (LiveRange *LROfVal = LRI.getLiveRangeForValue(Val))
                 if (LROfVal->hasColor() )
diff --git a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
index d49b1d66398..f3c22e9898b 100644
--- a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
+++ b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
@@ -6,7 +6,7 @@
 
 #include "llvm/CodeGen/LiveRangeInfo.h"
 #include "RegAllocCommon.h"
-#include "llvm/CodeGen/RegClass.h"
+#include "RegClass.h"
 #include "llvm/CodeGen/IGNode.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineFunction.h"
@@ -16,6 +16,8 @@
 #include "Support/SetOperations.h"
 using std::cerr;
 
+unsigned LiveRange::getRegClassID() const { return getRegClass()->getID(); }
+
 LiveRangeInfo::LiveRangeInfo(const Function *F, const TargetMachine &tm,
 			     std::vector<RegClass *> &RCL)
   : Meth(F), TM(tm), RegClassList(RCL), MRI(tm.getRegInfo()) { }
@@ -93,7 +95,8 @@ LiveRangeInfo::createNewLiveRange(const Value* Def, bool isCC /* = false*/)
   LiveRangeMap[Def] = DefRange;           // and update the map.
 
   // set the register class of the new live range
-  DefRange->setRegClass(RegClassList[MRI.getRegClassIDOfValue(Def, isCC)]);
+  DefRange->setRegClass(RegClassList[MRI.getRegClassIDOfType(Def->getType(),
+                                                             isCC)]);
 
   if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
     cerr << "  Creating a LR for def ";
@@ -280,7 +283,6 @@ void LiveRangeInfo::coalesceLRs()
 	      continue;
 
 	    if (MRI.getRegType(LROfDef) == MRI.getRegType(LROfUse)) {
-
 	      // If the two RegTypes are the same
 	      if (!RCOfDef->getInterference(LROfDef, LROfUse) ) {
 
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 724dbc7744a..007d0758969 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -6,8 +6,8 @@
 
 #include "llvm/CodeGen/RegisterAllocation.h"
 #include "RegAllocCommon.h"
+#include "RegClass.h"
 #include "llvm/CodeGen/IGNode.h"
-#include "llvm/CodeGen/RegClass.h"
 #include "llvm/CodeGen/PhyRegAlloc.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineInstrAnnot.h"
@@ -654,7 +654,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
   MachineOperand& Op = MInst->getOperand(OpNum);
   bool isDef =  MInst->operandIsDefined(OpNum);
   bool isDefAndUse =  MInst->operandIsDefinedAndUsed(OpNum);
-  unsigned RegType = MRI.getRegType( LR );
+  unsigned RegType = MRI.getRegType(LR);
   int SpillOff = LR->getSpillOffFromFP();
   RegClass *RC = LR->getRegClass();
   const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
@@ -888,7 +888,7 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
       if (MInst->getOperandType(OpNum) == MachineOperand::MO_VirtualRegister || 
           MInst->getOperandType(OpNum) == MachineOperand::MO_CCRegister)
         if (const Value* Val = Op.getVRegValue())
-          if (MRI.getRegClassIDOfValue(Val) == RC->getID())
+          if (MRI.getRegClassIDOfType(Val->getType()) == RC->getID())
             if (Op.getAllocatedRegNum() == -1)
               if (LiveRange *LROfVal = LRI.getLiveRangeForValue(Val))
                 if (LROfVal->hasColor() )