From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Wed, 24 Sep 2014 02:17:06 +0000 (+0000)
Subject: R600/SI: Enable named operand table for SALU instructions
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=9b50273e54a2a6afb3c663b585af24d8da6c4574;p=oota-llvm.git

R600/SI: Enable named operand table for SALU instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218358 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td
index 32b8069140c..8369a0c8687 100644
--- a/lib/Target/R600/SIInstrFormats.td
+++ b/lib/Target/R600/SIInstrFormats.td
@@ -164,6 +164,8 @@ class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
   let mayStore = 0;
   let hasSideEffects = 0;
   let SALU = 1;
+
+  let UseNamedOperandTable = 1;
 }
 
 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
@@ -174,6 +176,8 @@ class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
   let mayStore = 0;
   let hasSideEffects = 0;
   let SALU = 1;
+
+  let UseNamedOperandTable = 1;
 }
 
 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
@@ -183,6 +187,8 @@ class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
   let mayStore = 0;
   let hasSideEffects = 0;
   let SALU = 1;
+
+  let UseNamedOperandTable = 1;
 }
 
 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> :
@@ -192,6 +198,8 @@ class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> :
   let mayStore = 0;
   let hasSideEffects = 0;
   let SALU = 1;
+
+  let UseNamedOperandTable = 1;
 }
 
 class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,