From: Andrew Trick Date: Tue, 17 Jan 2012 22:27:45 +0000 (+0000) Subject: Test case rename X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=97af768ccc00962a2c16e990b89c9028f8e247be;p=oota-llvm.git Test case rename git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148344 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/Transforms/LoopStrengthReduce/2012-01-02-nopreheader.ll b/test/Transforms/LoopStrengthReduce/2012-01-02-nopreheader.ll new file mode 100644 index 00000000000..d7f5723188c --- /dev/null +++ b/test/Transforms/LoopStrengthReduce/2012-01-02-nopreheader.ll @@ -0,0 +1,88 @@ +; RUN: opt -loop-reduce -S < %s | FileCheck %s +; +; "SelectionDAGBuilder shouldn't visit PHI nodes!" assert. +; SCEVExpander segfault on simple test case + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-f128:128:128-n8:16:32" +target triple = "i386-apple-darwin" + +; LSR should convert the inner loop (bb7.us) IV (j.01.us) into float*. +; This involves a nested AddRec, the outer AddRec's loop invariant components +; cannot find a preheader, so they should be expanded in the loop header +; (bb7.lr.ph.us) below the existing phi i.12.us. +; Currently, LSR won't kick in on such loops. +; CHECK: @nopreheader +; CHECK: bb7.us: +; CHECK-NOT: phi float* +; CHECK: %j.01.us = phi i32 +; CHECK-NOT: phi float* +define void @nopreheader(float* nocapture %a, i32 %n) nounwind { +entry: + %0 = sdiv i32 %n, undef + indirectbr i8* undef, [label %bb10.preheader] + +bb10.preheader: ; preds = %bb4 + indirectbr i8* undef, [label %bb8.preheader.lr.ph, label %return] + +bb8.preheader.lr.ph: ; preds = %bb10.preheader + indirectbr i8* null, [label %bb7.lr.ph.us, label %bb9] + +bb7.lr.ph.us: ; preds = %bb9.us, %bb8.preheader.lr.ph + %i.12.us = phi i32 [ %2, %bb9.us ], [ 0, %bb8.preheader.lr.ph ] + %tmp30 = mul i32 %0, %i.12.us + indirectbr i8* undef, [label %bb7.us] + +bb7.us: ; preds = %bb7.lr.ph.us, %bb7.us + %j.01.us = phi i32 [ 0, %bb7.lr.ph.us ], [ %1, %bb7.us ] + %tmp31 = add i32 %tmp30, %j.01.us + %scevgep9 = getelementptr float* %a, i32 %tmp31 + store float undef, float* %scevgep9, align 1 + %1 = add nsw i32 %j.01.us, 1 + indirectbr i8* undef, [label %bb9.us, label %bb7.us] + +bb9.us: ; preds = %bb7.us + %2 = add nsw i32 %i.12.us, 1 + indirectbr i8* undef, [label %bb7.lr.ph.us, label %return] + +bb9: ; preds = %bb9, %bb8.preheader.lr.ph + indirectbr i8* undef, [label %bb9, label %return] + +return: ; preds = %bb9, %bb9.us, %bb10.preheader + ret void +} + +; In this case, SCEVExpander simply cannot materialize the AddRecExpr +; that LSR picks. We must detect that %bb8.preheader does not have a +; preheader and avoid performing LSR on %bb7. +; CHECK: @nopreheader2 +; CHECK: bb7: +; CHECK: %indvar = phi i32 +define fastcc void @nopreheader2([200 x i32]* nocapture %Array2) nounwind { +entry: + indirectbr i8* undef, [label %bb] + +bb: ; preds = %bb, %entry + indirectbr i8* undef, [label %bb3, label %bb] + +bb3: ; preds = %bb3, %bb + indirectbr i8* undef, [label %bb8.preheader, label %bb3] + +bb8.preheader: ; preds = %bb9, %bb3 + %indvar5 = phi i32 [ %indvar.next6, %bb9 ], [ 0, %bb3 ] + %tmp26 = add i32 %indvar5, 13 + indirectbr i8* null, [label %bb7] + +bb7: ; preds = %bb8.preheader, %bb7 + %indvar = phi i32 [ 0, %bb8.preheader ], [ %indvar.next, %bb7 ] + %scevgep = getelementptr [200 x i32]* %Array2, i32 %tmp26, i32 %indvar + store i32 undef, i32* %scevgep, align 4 + %indvar.next = add i32 %indvar, 1 + indirectbr i8* undef, [label %bb9, label %bb7] + +bb9: ; preds = %bb7 + %indvar.next6 = add i32 %indvar5, 1 + indirectbr i8* undef, [label %return, label %bb8.preheader] + +return: ; preds = %bb9 + ret void +} diff --git a/test/Transforms/LoopStrengthReduce/2012-02-nopreheader.ll b/test/Transforms/LoopStrengthReduce/2012-02-nopreheader.ll deleted file mode 100644 index d7f5723188c..00000000000 --- a/test/Transforms/LoopStrengthReduce/2012-02-nopreheader.ll +++ /dev/null @@ -1,88 +0,0 @@ -; RUN: opt -loop-reduce -S < %s | FileCheck %s -; -; "SelectionDAGBuilder shouldn't visit PHI nodes!" assert. -; SCEVExpander segfault on simple test case - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-f128:128:128-n8:16:32" -target triple = "i386-apple-darwin" - -; LSR should convert the inner loop (bb7.us) IV (j.01.us) into float*. -; This involves a nested AddRec, the outer AddRec's loop invariant components -; cannot find a preheader, so they should be expanded in the loop header -; (bb7.lr.ph.us) below the existing phi i.12.us. -; Currently, LSR won't kick in on such loops. -; CHECK: @nopreheader -; CHECK: bb7.us: -; CHECK-NOT: phi float* -; CHECK: %j.01.us = phi i32 -; CHECK-NOT: phi float* -define void @nopreheader(float* nocapture %a, i32 %n) nounwind { -entry: - %0 = sdiv i32 %n, undef - indirectbr i8* undef, [label %bb10.preheader] - -bb10.preheader: ; preds = %bb4 - indirectbr i8* undef, [label %bb8.preheader.lr.ph, label %return] - -bb8.preheader.lr.ph: ; preds = %bb10.preheader - indirectbr i8* null, [label %bb7.lr.ph.us, label %bb9] - -bb7.lr.ph.us: ; preds = %bb9.us, %bb8.preheader.lr.ph - %i.12.us = phi i32 [ %2, %bb9.us ], [ 0, %bb8.preheader.lr.ph ] - %tmp30 = mul i32 %0, %i.12.us - indirectbr i8* undef, [label %bb7.us] - -bb7.us: ; preds = %bb7.lr.ph.us, %bb7.us - %j.01.us = phi i32 [ 0, %bb7.lr.ph.us ], [ %1, %bb7.us ] - %tmp31 = add i32 %tmp30, %j.01.us - %scevgep9 = getelementptr float* %a, i32 %tmp31 - store float undef, float* %scevgep9, align 1 - %1 = add nsw i32 %j.01.us, 1 - indirectbr i8* undef, [label %bb9.us, label %bb7.us] - -bb9.us: ; preds = %bb7.us - %2 = add nsw i32 %i.12.us, 1 - indirectbr i8* undef, [label %bb7.lr.ph.us, label %return] - -bb9: ; preds = %bb9, %bb8.preheader.lr.ph - indirectbr i8* undef, [label %bb9, label %return] - -return: ; preds = %bb9, %bb9.us, %bb10.preheader - ret void -} - -; In this case, SCEVExpander simply cannot materialize the AddRecExpr -; that LSR picks. We must detect that %bb8.preheader does not have a -; preheader and avoid performing LSR on %bb7. -; CHECK: @nopreheader2 -; CHECK: bb7: -; CHECK: %indvar = phi i32 -define fastcc void @nopreheader2([200 x i32]* nocapture %Array2) nounwind { -entry: - indirectbr i8* undef, [label %bb] - -bb: ; preds = %bb, %entry - indirectbr i8* undef, [label %bb3, label %bb] - -bb3: ; preds = %bb3, %bb - indirectbr i8* undef, [label %bb8.preheader, label %bb3] - -bb8.preheader: ; preds = %bb9, %bb3 - %indvar5 = phi i32 [ %indvar.next6, %bb9 ], [ 0, %bb3 ] - %tmp26 = add i32 %indvar5, 13 - indirectbr i8* null, [label %bb7] - -bb7: ; preds = %bb8.preheader, %bb7 - %indvar = phi i32 [ 0, %bb8.preheader ], [ %indvar.next, %bb7 ] - %scevgep = getelementptr [200 x i32]* %Array2, i32 %tmp26, i32 %indvar - store i32 undef, i32* %scevgep, align 4 - %indvar.next = add i32 %indvar, 1 - indirectbr i8* undef, [label %bb9, label %bb7] - -bb9: ; preds = %bb7 - %indvar.next6 = add i32 %indvar5, 1 - indirectbr i8* undef, [label %return, label %bb8.preheader] - -return: ; preds = %bb9 - ret void -}