From: Scott Michel <scottm@aero.org>
Date: Tue, 6 Jan 2009 03:51:14 +0000 (+0000)
Subject: CellSPU: Update the README
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=939e3a7f6483c907fdf7e2063ec3381c00927228;p=oota-llvm.git

CellSPU: Update the README

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61785 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/CellSPU/README.txt b/lib/Target/CellSPU/README.txt
index 636a41d5fc0..083867ff780 100644
--- a/lib/Target/CellSPU/README.txt
+++ b/lib/Target/CellSPU/README.txt
@@ -34,16 +34,27 @@ to add 'spu' to configure's --enable-targets option, e.g.:
 
 ---------------------------------------------------------------------------
 
-The unofficially official status page (because it's not easy to get an
-officially blessed external web page from either IBM Austin or Aerospace):
+TODO:
+* Create a machine pass for performing dual-pipeline scheduling specifically
+  for CellSPU, handle inserting branch prediction instructions.
 
-              http://sites.google.com/site/llvmcellspu/
+* i32 instructions:
 
-TODO:
-* Finish branch instructions, branch prediction
+  * i32 division (work-in-progress)
+
+* i64 support (see i64operations.c test harness):
+
+  * shifts and comparison operators: done
+  * sign and zero extension: done
+  * addition: done
+  * subtraction: needed
+  * multiplication: work-in-progress
+
+* i128 support:
 
-  These instructions were started, but only insofar as to get llvm-gcc-4.2's
-  crtbegin.ll working (which doesn't.)
+  * zero extension: done
+  * sign extension: needed
+  * arithmetic operators (add, sub, mul, div): needed
 
 * Double floating point support