From: Tom Stellard Date: Wed, 5 Nov 2014 14:50:53 +0000 (+0000) Subject: R600/SI: Change all instruction assembly names to lowercase. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=8eaed0f63d99a3d6a75dcbb1edaa103d53501830;p=oota-llvm.git R600/SI: Change all instruction assembly names to lowercase. This matches the format produced by the AMD proprietary driver. //==================================================================// // Shell script for converting .ll test cases: (Pass the .ll files you want to convert to this script as arguments). //==================================================================// ; This was necessary on my system so that A-Z in sed would match only ; upper case. I'm not sure why. export LC_ALL='C' TEST_FILES="$*" MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r` for f in $TEST_FILES; do # Check that there are SI tests: grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f if [ $? -eq 0 ]; then for match in $MATCHES; do sed -i -e "s/\([ :]$match\)/\L\1/" $f done # Try to get check lines with partial instruction names sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f fi done sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll //==================================================================// // Shell script for converting .td files (run this last) //==================================================================// export LC_ALL='C' sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index 5a88ea7df78..1b28b420b16 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -298,7 +298,7 @@ class EXPCommon : InstSI< (outs), (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm, VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3), - "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3", + "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3", [] > { let EXP_CNT = 1; @@ -308,10 +308,10 @@ class EXPCommon : InstSI< multiclass EXP_m { let isPseudo = 1 in { - def "" : EXPCommon, SIMCInstr <"EXP", SISubtarget.NONE> ; + def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ; } - def _si : EXPCommon, SIMCInstr <"EXP", SISubtarget.SI>, EXPe; + def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 242dae5d122..01d2a9f3364 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -52,126 +52,126 @@ let mayLoad = 1 in { // We are using the SGPR_32 and not the SReg_32 register class for 32-bit // SMRD instructions, because the SGPR_32 register class does not include M0 // and writing to M0 from an SMRD instruction will hang the GPU. -defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>; -defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>; -defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>; -defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>; -defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>; +defm S_LOAD_DWORD : SMRD_Helper <0x00, "s_load_dword", SReg_64, SGPR_32>; +defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "s_load_dwordx2", SReg_64, SReg_64>; +defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "s_load_dwordx4", SReg_64, SReg_128>; +defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "s_load_dwordx8", SReg_64, SReg_256>; +defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "s_load_dwordx16", SReg_64, SReg_512>; defm S_BUFFER_LOAD_DWORD : SMRD_Helper < - 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32 + 0x08, "s_buffer_load_dword", SReg_128, SGPR_32 >; defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < - 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64 + 0x09, "s_buffer_load_dwordx2", SReg_128, SReg_64 >; defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < - 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128 + 0x0a, "s_buffer_load_dwordx4", SReg_128, SReg_128 >; defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < - 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256 + 0x0b, "s_buffer_load_dwordx8", SReg_128, SReg_256 >; defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < - 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512 + 0x0c, "s_buffer_load_dwordx16", SReg_128, SReg_512 >; } // mayLoad = 1 -//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>; -//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>; +//def S_MEMTIME : SMRD_ <0x0000001e, "s_memtime", []>; +//def S_DCACHE_INV : SMRD_ <0x0000001f, "s_dcache_inv", []>; //===----------------------------------------------------------------------===// // SOP1 Instructions //===----------------------------------------------------------------------===// let isMoveImm = 1 in { -def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>; -def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>; -def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>; -def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>; +def S_MOV_B32 : SOP1_32 <0x00000003, "s_mov_b32", []>; +def S_MOV_B64 : SOP1_64 <0x00000004, "s_mov_b64", []>; +def S_CMOV_B32 : SOP1_32 <0x00000005, "s_cmov_b32", []>; +def S_CMOV_B64 : SOP1_64 <0x00000006, "s_cmov_b64", []>; } // End isMoveImm = 1 -def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", +def S_NOT_B32 : SOP1_32 <0x00000007, "s_not_b32", [(set i32:$dst, (not i32:$src0))] >; -def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", +def S_NOT_B64 : SOP1_64 <0x00000008, "s_not_b64", [(set i64:$dst, (not i64:$src0))] >; -def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>; -def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>; -def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", +def S_WQM_B32 : SOP1_32 <0x00000009, "s_wqm_b32", []>; +def S_WQM_B64 : SOP1_64 <0x0000000a, "s_wqm_b64", []>; +def S_BREV_B32 : SOP1_32 <0x0000000b, "s_brev_b32", [(set i32:$dst, (AMDGPUbrev i32:$src0))] >; -def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>; +def S_BREV_B64 : SOP1_64 <0x0000000c, "s_brev_b64", []>; -////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>; -////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>; -def S_BCNT1_I32_B32 : SOP1_32 <0x0000000f, "S_BCNT1_I32_B32", +////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "s_bcnt0_i32_b32", []>; +////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "s_bcnt0_i32_b64", []>; +def S_BCNT1_I32_B32 : SOP1_32 <0x0000000f, "s_bcnt1_i32_b32", [(set i32:$dst, (ctpop i32:$src0))] >; -def S_BCNT1_I32_B64 : SOP1_32_64 <0x00000010, "S_BCNT1_I32_B64", []>; +def S_BCNT1_I32_B64 : SOP1_32_64 <0x00000010, "s_bcnt1_i32_b64", []>; -////def S_FF0_I32_B32 : SOP1_32 <0x00000011, "S_FF0_I32_B32", []>; -////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>; -def S_FF1_I32_B32 : SOP1_32 <0x00000013, "S_FF1_I32_B32", +////def S_FF0_I32_B32 : SOP1_32 <0x00000011, "s_ff0_i32_b32", []>; +////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "s_ff0_i32_b64", []>; +def S_FF1_I32_B32 : SOP1_32 <0x00000013, "s_ff1_i32_b32", [(set i32:$dst, (cttz_zero_undef i32:$src0))] >; -////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>; +////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "s_ff1_i32_b64", []>; -def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", +def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "s_flbit_i32_b32", [(set i32:$dst, (ctlz_zero_undef i32:$src0))] >; -//def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>; -def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>; -//def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>; -def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", +//def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "s_flbit_i32_b64", []>; +def S_FLBIT_I32 : SOP1_32 <0x00000017, "s_flbit_i32", []>; +//def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "s_flbit_i32_i64", []>; +def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "s_sext_i32_i8", [(set i32:$dst, (sext_inreg i32:$src0, i8))] >; -def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", +def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "s_sext_i32_i16", [(set i32:$dst, (sext_inreg i32:$src0, i16))] >; -////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>; -////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>; -////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>; -////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>; +////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "s_bitset0_b32", []>; +////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "s_bitset0_b64", []>; +////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "s_bitset1_b32", []>; +////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "s_bitset1_b64", []>; def S_GETPC_B64 : SOP1 < - 0x0000001f, (outs SReg_64:$dst), (ins), "S_GETPC_B64 $dst", [] + 0x0000001f, (outs SReg_64:$dst), (ins), "s_getpc_b64 $dst", [] > { let SSRC0 = 0; } -def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>; -def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>; -def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>; +def S_SETPC_B64 : SOP1_64 <0x00000020, "s_setpc_b64", []>; +def S_SWAPPC_B64 : SOP1_64 <0x00000021, "s_swappc_b64", []>; +def S_RFE_B64 : SOP1_64 <0x00000022, "s_rfe_b64", []>; let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in { -def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>; -def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>; -def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>; -def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>; -def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>; -def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>; -def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>; -def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>; +def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "s_and_saveexec_b64", []>; +def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "s_or_saveexec_b64", []>; +def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "s_xor_saveexec_b64", []>; +def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "s_andn2_saveexec_b64", []>; +def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "s_orn2_saveexec_b64", []>; +def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "s_nand_saveexec_b64", []>; +def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "s_nor_saveexec_b64", []>; +def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "s_xnor_saveexec_b64", []>; } // End hasSideEffects = 1 -def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>; -def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>; -def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>; -def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>; -def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>; -def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>; -//def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>; -def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>; -def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>; -def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>; +def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "s_quadmask_b32", []>; +def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "s_quadmask_b64", []>; +def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "s_movrels_b32", []>; +def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "s_movrels_b64", []>; +def S_MOVRELD_B32 : SOP1_32 <0x00000030, "s_movreld_b32", []>; +def S_MOVRELD_B64 : SOP1_64 <0x00000031, "s_movreld_b64", []>; +//def S_CBRANCH_JOIN : SOP1_ <0x00000032, "s_cbranch_join", []>; +def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "s_mov_regrd_b32", []>; +def S_ABS_I32 : SOP1_32 <0x00000034, "s_abs_i32", []>; +def S_MOV_FED_B32 : SOP1_32 <0x00000035, "s_mov_fed_b32", []>; //===----------------------------------------------------------------------===// // SOP2 Instructions @@ -179,149 +179,149 @@ def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>; let Defs = [SCC] in { // Carry out goes to SCC let isCommutable = 1 in { -def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>; -def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32", +def S_ADD_U32 : SOP2_32 <0x00000000, "s_add_u32", []>; +def S_ADD_I32 : SOP2_32 <0x00000002, "s_add_i32", [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))] >; } // End isCommutable = 1 -def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>; -def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32", +def S_SUB_U32 : SOP2_32 <0x00000001, "s_sub_u32", []>; +def S_SUB_I32 : SOP2_32 <0x00000003, "s_sub_i32", [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))] >; let Uses = [SCC] in { // Carry in comes from SCC let isCommutable = 1 in { -def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32", +def S_ADDC_U32 : SOP2_32 <0x00000004, "s_addc_u32", [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; } // End isCommutable = 1 -def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32", +def S_SUBB_U32 : SOP2_32 <0x00000005, "s_subb_u32", [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; } // End Uses = [SCC] } // End Defs = [SCC] -def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", +def S_MIN_I32 : SOP2_32 <0x00000006, "s_min_i32", [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))] >; -def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", +def S_MIN_U32 : SOP2_32 <0x00000007, "s_min_u32", [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))] >; -def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", +def S_MAX_I32 : SOP2_32 <0x00000008, "s_max_i32", [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))] >; -def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", +def S_MAX_U32 : SOP2_32 <0x00000009, "s_max_u32", [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))] >; def S_CSELECT_B32 : SOP2 < 0x0000000a, (outs SReg_32:$dst), - (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32", + (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "s_cselect_b32", [] >; -def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>; +def S_CSELECT_B64 : SOP2_64 <0x0000000b, "s_cselect_b64", []>; -def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", +def S_AND_B32 : SOP2_32 <0x0000000e, "s_and_b32", [(set i32:$dst, (and i32:$src0, i32:$src1))] >; -def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64", +def S_AND_B64 : SOP2_64 <0x0000000f, "s_and_b64", [(set i64:$dst, (and i64:$src0, i64:$src1))] >; -def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", +def S_OR_B32 : SOP2_32 <0x00000010, "s_or_b32", [(set i32:$dst, (or i32:$src0, i32:$src1))] >; -def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", +def S_OR_B64 : SOP2_64 <0x00000011, "s_or_b64", [(set i64:$dst, (or i64:$src0, i64:$src1))] >; -def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", +def S_XOR_B32 : SOP2_32 <0x00000012, "s_xor_b32", [(set i32:$dst, (xor i32:$src0, i32:$src1))] >; -def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64", +def S_XOR_B64 : SOP2_64 <0x00000013, "s_xor_b64", [(set i64:$dst, (xor i64:$src0, i64:$src1))] >; -def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>; -def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>; -def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>; -def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>; -def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>; -def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>; -def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>; -def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>; -def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>; -def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>; +def S_ANDN2_B32 : SOP2_32 <0x00000014, "s_andn2_b32", []>; +def S_ANDN2_B64 : SOP2_64 <0x00000015, "s_andn2_b64", []>; +def S_ORN2_B32 : SOP2_32 <0x00000016, "s_orn2_b32", []>; +def S_ORN2_B64 : SOP2_64 <0x00000017, "s_orn2_b64", []>; +def S_NAND_B32 : SOP2_32 <0x00000018, "s_nand_b32", []>; +def S_NAND_B64 : SOP2_64 <0x00000019, "s_nand_b64", []>; +def S_NOR_B32 : SOP2_32 <0x0000001a, "s_nor_b32", []>; +def S_NOR_B64 : SOP2_64 <0x0000001b, "s_nor_b64", []>; +def S_XNOR_B32 : SOP2_32 <0x0000001c, "s_xnor_b32", []>; +def S_XNOR_B64 : SOP2_64 <0x0000001d, "s_xnor_b64", []>; // Use added complexity so these patterns are preferred to the VALU patterns. let AddedComplexity = 1 in { -def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32", +def S_LSHL_B32 : SOP2_32 <0x0000001e, "s_lshl_b32", [(set i32:$dst, (shl i32:$src0, i32:$src1))] >; -def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64", +def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "s_lshl_b64", [(set i64:$dst, (shl i64:$src0, i32:$src1))] >; -def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32", +def S_LSHR_B32 : SOP2_32 <0x00000020, "s_lshr_b32", [(set i32:$dst, (srl i32:$src0, i32:$src1))] >; -def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64", +def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "s_lshr_b64", [(set i64:$dst, (srl i64:$src0, i32:$src1))] >; -def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32", +def S_ASHR_I32 : SOP2_32 <0x00000022, "s_ashr_i32", [(set i32:$dst, (sra i32:$src0, i32:$src1))] >; -def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64", +def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "s_ashr_i64", [(set i64:$dst, (sra i64:$src0, i32:$src1))] >; -def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>; -def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>; -def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", +def S_BFM_B32 : SOP2_32 <0x00000024, "s_bfm_b32", []>; +def S_BFM_B64 : SOP2_64 <0x00000025, "s_bfm_b64", []>; +def S_MUL_I32 : SOP2_32 <0x00000026, "s_mul_i32", [(set i32:$dst, (mul i32:$src0, i32:$src1))] >; } // End AddedComplexity = 1 -def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>; -def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>; -def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>; -def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>; -//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>; -def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>; +def S_BFE_U32 : SOP2_32 <0x00000027, "s_bfe_u32", []>; +def S_BFE_I32 : SOP2_32 <0x00000028, "s_bfe_i32", []>; +def S_BFE_U64 : SOP2_64 <0x00000029, "s_bfe_u64", []>; +def S_BFE_I64 : SOP2_64 <0x0000002a, "s_bfe_i64", []>; +//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "s_cbranch_g_fork", []>; +def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "s_absdiff_i32", []>; //===----------------------------------------------------------------------===// // SOPC Instructions //===----------------------------------------------------------------------===// -def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">; -def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">; -def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">; -def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32">; -def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32">; -def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32">; -def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32">; -def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32">; -def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32">; -def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32">; -def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32">; -def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">; -////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>; -////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>; -////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>; -////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>; -//def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>; +def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "s_cmp_eq_i32">; +def S_CMP_LG_I32 : SOPC_32 <0x00000001, "s_cmp_lg_i32">; +def S_CMP_GT_I32 : SOPC_32 <0x00000002, "s_cmp_gt_i32">; +def S_CMP_GE_I32 : SOPC_32 <0x00000003, "s_cmp_ge_i32">; +def S_CMP_LT_I32 : SOPC_32 <0x00000004, "s_cmp_lt_i32">; +def S_CMP_LE_I32 : SOPC_32 <0x00000005, "s_cmp_le_i32">; +def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "s_cmp_eq_u32">; +def S_CMP_LG_U32 : SOPC_32 <0x00000007, "s_cmp_lg_u32">; +def S_CMP_GT_U32 : SOPC_32 <0x00000008, "s_cmp_gt_u32">; +def S_CMP_GE_U32 : SOPC_32 <0x00000009, "s_cmp_ge_u32">; +def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "s_cmp_lt_u32">; +def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "s_cmp_le_u32">; +////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "s_bitcmp0_b32", []>; +////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "s_bitcmp1_b32", []>; +////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "s_bitcmp0_b64", []>; +////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "s_bitcmp1_b64", []>; +//def S_SETVSKIP : SOPC_ <0x00000010, "s_setvskip", []>; //===----------------------------------------------------------------------===// // SOPK Instructions //===----------------------------------------------------------------------===// -def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>; -def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>; +def S_MOVK_I32 : SOPK_32 <0x00000000, "s_movk_i32", []>; +def S_CMOVK_I32 : SOPK_32 <0x00000002, "s_cmovk_i32", []>; /* This instruction is disabled for now until we can figure out how to teach @@ -337,46 +337,46 @@ VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 def S_CMPK_EQ_I32 : SOPK < 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1), - "S_CMPK_EQ_I32", + "s_cmpk_eq_i32", [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))] >; */ let isCompare = 1, Defs = [SCC] in { -def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>; -def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>; -def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>; -def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>; -def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>; -def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>; -def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>; -def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>; -def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>; -def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>; -def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>; +def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "s_cmpk_lg_i32", []>; +def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "s_cmpk_gt_i32", []>; +def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "s_cmpk_ge_i32", []>; +def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "s_cmpk_lt_i32", []>; +def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "s_cmpk_le_i32", []>; +def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "s_cmpk_eq_u32", []>; +def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "s_cmpk_lg_u32", []>; +def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "s_cmpk_gt_u32", []>; +def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "s_cmpk_ge_u32", []>; +def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "s_cmpk_lt_u32", []>; +def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "s_cmpk_le_u32", []>; } // End isCompare = 1, Defs = [SCC] let Defs = [SCC], isCommutable = 1 in { - def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>; - def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>; + def S_ADDK_I32 : SOPK_32 <0x0000000f, "s_addk_i32", []>; + def S_MULK_I32 : SOPK_32 <0x00000010, "s_mulk_i32", []>; } -//def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>; -def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>; -def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>; -def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>; -//def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>; -//def EXP : EXP_ <0x00000000, "EXP", []>; +//def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "s_cbranch_i_fork", []>; +def S_GETREG_B32 : SOPK_32 <0x00000012, "s_getreg_b32", []>; +def S_SETREG_B32 : SOPK_32 <0x00000013, "s_setreg_b32", []>; +def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "s_getreg_regrd_b32", []>; +//def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "s_setreg_imm32_b32", []>; +//def EXP : EXP_ <0x00000000, "exp", []>; //===----------------------------------------------------------------------===// // SOPP Instructions //===----------------------------------------------------------------------===// -def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "S_NOP $simm16", []>; +def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16", []>; let isTerminator = 1 in { -def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM", +def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm", [(IL_retflag)]> { let simm16 = 0; let isBarrier = 1; @@ -385,7 +385,7 @@ def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM", let isBranch = 1 in { def S_BRANCH : SOPP < - 0x00000002, (ins sopp_brtarget:$simm16), "S_BRANCH $simm16", + 0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16", [(br bb:$simm16)]> { let isBarrier = 1; } @@ -393,35 +393,35 @@ def S_BRANCH : SOPP < let DisableEncoding = "$scc" in { def S_CBRANCH_SCC0 : SOPP < 0x00000004, (ins sopp_brtarget:$simm16, SCCReg:$scc), - "S_CBRANCH_SCC0 $simm16", [] + "s_cbranch_scc0 $simm16", [] >; def S_CBRANCH_SCC1 : SOPP < 0x00000005, (ins sopp_brtarget:$simm16, SCCReg:$scc), - "S_CBRANCH_SCC1 $simm16", + "s_cbranch_scc1 $simm16", [] >; } // End DisableEncoding = "$scc" def S_CBRANCH_VCCZ : SOPP < 0x00000006, (ins sopp_brtarget:$simm16, VCCReg:$vcc), - "S_CBRANCH_VCCZ $simm16", + "s_cbranch_vccz $simm16", [] >; def S_CBRANCH_VCCNZ : SOPP < 0x00000007, (ins sopp_brtarget:$simm16, VCCReg:$vcc), - "S_CBRANCH_VCCNZ $simm16", + "s_cbranch_vccnz $simm16", [] >; let DisableEncoding = "$exec" in { def S_CBRANCH_EXECZ : SOPP < 0x00000008, (ins sopp_brtarget:$simm16, EXECReg:$exec), - "S_CBRANCH_EXECZ $simm16", + "s_cbranch_execz $simm16", [] >; def S_CBRANCH_EXECNZ : SOPP < 0x00000009, (ins sopp_brtarget:$simm16, EXECReg:$exec), - "S_CBRANCH_EXECNZ $simm16", + "s_cbranch_execnz $simm16", [] >; } // End DisableEncoding = "$exec" @@ -431,7 +431,7 @@ def S_CBRANCH_EXECNZ : SOPP < } // End isTerminator = 1 let hasSideEffects = 1 in { -def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER", +def S_BARRIER : SOPP <0x0000000a, (ins), "s_barrier", [(int_AMDGPU_barrier_local)] > { let simm16 = 0; @@ -441,27 +441,27 @@ def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER", let mayStore = 1; } -def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16", +def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16", [] >; -//def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>; -//def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>; -//def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>; +//def S_SETHALT : SOPP_ <0x0000000d, "s_sethalt", []>; +//def S_SLEEP : SOPP_ <0x0000000e, "s_sleep", []>; +//def S_SETPRIO : SOPP_ <0x0000000f, "s_setprio", []>; let Uses = [EXEC] in { - def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16", + def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "s_sendmsg $simm16", [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)] > { let DisableEncoding = "$m0"; } } // End Uses = [EXEC] -//def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>; -//def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>; -//def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>; -//def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>; -//def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>; -//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>; +//def S_SENDMSGHALT : SOPP_ <0x00000011, "s_sendmsghalt", []>; +//def S_TRAP : SOPP_ <0x00000012, "s_trap", []>; +//def S_ICACHE_INV : SOPP_ <0x00000013, "s_icache_inv", []>; +//def S_INCPERFLEVEL : SOPP_ <0x00000014, "s_incperflevel", []>; +//def S_DECPERFLEVEL : SOPP_ <0x00000015, "s_decperflevel", []>; +//def S_TTRACEDATA : SOPP_ <0x00000016, "s_ttracedata", []>; } // End hasSideEffects //===----------------------------------------------------------------------===// @@ -470,256 +470,256 @@ let Uses = [EXEC] in { let isCompare = 1 in { -defm V_CMP_F_F32 : VOPC_F32 , "V_CMP_F_F32">; -defm V_CMP_LT_F32 : VOPC_F32 , "V_CMP_LT_F32", COND_OLT>; -defm V_CMP_EQ_F32 : VOPC_F32 , "V_CMP_EQ_F32", COND_OEQ>; -defm V_CMP_LE_F32 : VOPC_F32 , "V_CMP_LE_F32", COND_OLE>; -defm V_CMP_GT_F32 : VOPC_F32 , "V_CMP_GT_F32", COND_OGT>; -defm V_CMP_LG_F32 : VOPC_F32 , "V_CMP_LG_F32">; -defm V_CMP_GE_F32 : VOPC_F32 , "V_CMP_GE_F32", COND_OGE>; -defm V_CMP_O_F32 : VOPC_F32 , "V_CMP_O_F32", COND_O>; -defm V_CMP_U_F32 : VOPC_F32 , "V_CMP_U_F32", COND_UO>; -defm V_CMP_NGE_F32 : VOPC_F32 , "V_CMP_NGE_F32">; -defm V_CMP_NLG_F32 : VOPC_F32 , "V_CMP_NLG_F32">; -defm V_CMP_NGT_F32 : VOPC_F32 , "V_CMP_NGT_F32">; -defm V_CMP_NLE_F32 : VOPC_F32 , "V_CMP_NLE_F32">; -defm V_CMP_NEQ_F32 : VOPC_F32 , "V_CMP_NEQ_F32", COND_UNE>; -defm V_CMP_NLT_F32 : VOPC_F32 , "V_CMP_NLT_F32">; -defm V_CMP_TRU_F32 : VOPC_F32 , "V_CMP_TRU_F32">; +defm V_CMP_F_F32 : VOPC_F32 , "v_cmp_f_f32">; +defm V_CMP_LT_F32 : VOPC_F32 , "v_cmp_lt_f32", COND_OLT>; +defm V_CMP_EQ_F32 : VOPC_F32 , "v_cmp_eq_f32", COND_OEQ>; +defm V_CMP_LE_F32 : VOPC_F32 , "v_cmp_le_f32", COND_OLE>; +defm V_CMP_GT_F32 : VOPC_F32 , "v_cmp_gt_f32", COND_OGT>; +defm V_CMP_LG_F32 : VOPC_F32 , "v_cmp_lg_f32">; +defm V_CMP_GE_F32 : VOPC_F32 , "v_cmp_ge_f32", COND_OGE>; +defm V_CMP_O_F32 : VOPC_F32 , "v_cmp_o_f32", COND_O>; +defm V_CMP_U_F32 : VOPC_F32 , "v_cmp_u_f32", COND_UO>; +defm V_CMP_NGE_F32 : VOPC_F32 , "v_cmp_nge_f32">; +defm V_CMP_NLG_F32 : VOPC_F32 , "v_cmp_nlg_f32">; +defm V_CMP_NGT_F32 : VOPC_F32 , "v_cmp_ngt_f32">; +defm V_CMP_NLE_F32 : VOPC_F32 , "v_cmp_nle_f32">; +defm V_CMP_NEQ_F32 : VOPC_F32 , "v_cmp_neq_f32", COND_UNE>; +defm V_CMP_NLT_F32 : VOPC_F32 , "v_cmp_nlt_f32">; +defm V_CMP_TRU_F32 : VOPC_F32 , "v_cmp_tru_f32">; let hasSideEffects = 1 in { -defm V_CMPX_F_F32 : VOPCX_F32 , "V_CMPX_F_F32">; -defm V_CMPX_LT_F32 : VOPCX_F32 , "V_CMPX_LT_F32">; -defm V_CMPX_EQ_F32 : VOPCX_F32 , "V_CMPX_EQ_F32">; -defm V_CMPX_LE_F32 : VOPCX_F32 , "V_CMPX_LE_F32">; -defm V_CMPX_GT_F32 : VOPCX_F32 , "V_CMPX_GT_F32">; -defm V_CMPX_LG_F32 : VOPCX_F32 , "V_CMPX_LG_F32">; -defm V_CMPX_GE_F32 : VOPCX_F32 , "V_CMPX_GE_F32">; -defm V_CMPX_O_F32 : VOPCX_F32 , "V_CMPX_O_F32">; -defm V_CMPX_U_F32 : VOPCX_F32 , "V_CMPX_U_F32">; -defm V_CMPX_NGE_F32 : VOPCX_F32 , "V_CMPX_NGE_F32">; -defm V_CMPX_NLG_F32 : VOPCX_F32 , "V_CMPX_NLG_F32">; -defm V_CMPX_NGT_F32 : VOPCX_F32 , "V_CMPX_NGT_F32">; -defm V_CMPX_NLE_F32 : VOPCX_F32 , "V_CMPX_NLE_F32">; -defm V_CMPX_NEQ_F32 : VOPCX_F32 , "V_CMPX_NEQ_F32">; -defm V_CMPX_NLT_F32 : VOPCX_F32 , "V_CMPX_NLT_F32">; -defm V_CMPX_TRU_F32 : VOPCX_F32 , "V_CMPX_TRU_F32">; +defm V_CMPX_F_F32 : VOPCX_F32 , "v_cmpx_f_f32">; +defm V_CMPX_LT_F32 : VOPCX_F32 , "v_cmpx_lt_f32">; +defm V_CMPX_EQ_F32 : VOPCX_F32 , "v_cmpx_eq_f32">; +defm V_CMPX_LE_F32 : VOPCX_F32 , "v_cmpx_le_f32">; +defm V_CMPX_GT_F32 : VOPCX_F32 , "v_cmpx_gt_f32">; +defm V_CMPX_LG_F32 : VOPCX_F32 , "v_cmpx_lg_f32">; +defm V_CMPX_GE_F32 : VOPCX_F32 , "v_cmpx_ge_f32">; +defm V_CMPX_O_F32 : VOPCX_F32 , "v_cmpx_o_f32">; +defm V_CMPX_U_F32 : VOPCX_F32 , "v_cmpx_u_f32">; +defm V_CMPX_NGE_F32 : VOPCX_F32 , "v_cmpx_nge_f32">; +defm V_CMPX_NLG_F32 : VOPCX_F32 , "v_cmpx_nlg_f32">; +defm V_CMPX_NGT_F32 : VOPCX_F32 , "v_cmpx_ngt_f32">; +defm V_CMPX_NLE_F32 : VOPCX_F32 , "v_cmpx_nle_f32">; +defm V_CMPX_NEQ_F32 : VOPCX_F32 , "v_cmpx_neq_f32">; +defm V_CMPX_NLT_F32 : VOPCX_F32 , "v_cmpx_nlt_f32">; +defm V_CMPX_TRU_F32 : VOPCX_F32 , "v_cmpx_tru_f32">; } // End hasSideEffects = 1 -defm V_CMP_F_F64 : VOPC_F64 , "V_CMP_F_F64">; -defm V_CMP_LT_F64 : VOPC_F64 , "V_CMP_LT_F64", COND_OLT>; -defm V_CMP_EQ_F64 : VOPC_F64 , "V_CMP_EQ_F64", COND_OEQ>; -defm V_CMP_LE_F64 : VOPC_F64 , "V_CMP_LE_F64", COND_OLE>; -defm V_CMP_GT_F64 : VOPC_F64 , "V_CMP_GT_F64", COND_OGT>; -defm V_CMP_LG_F64 : VOPC_F64 , "V_CMP_LG_F64">; -defm V_CMP_GE_F64 : VOPC_F64 , "V_CMP_GE_F64", COND_OGE>; -defm V_CMP_O_F64 : VOPC_F64 , "V_CMP_O_F64", COND_O>; -defm V_CMP_U_F64 : VOPC_F64 , "V_CMP_U_F64", COND_UO>; -defm V_CMP_NGE_F64 : VOPC_F64 , "V_CMP_NGE_F64">; -defm V_CMP_NLG_F64 : VOPC_F64 , "V_CMP_NLG_F64">; -defm V_CMP_NGT_F64 : VOPC_F64 , "V_CMP_NGT_F64">; -defm V_CMP_NLE_F64 : VOPC_F64 , "V_CMP_NLE_F64">; -defm V_CMP_NEQ_F64 : VOPC_F64 , "V_CMP_NEQ_F64", COND_UNE>; -defm V_CMP_NLT_F64 : VOPC_F64 , "V_CMP_NLT_F64">; -defm V_CMP_TRU_F64 : VOPC_F64 , "V_CMP_TRU_F64">; +defm V_CMP_F_F64 : VOPC_F64 , "v_cmp_f_f64">; +defm V_CMP_LT_F64 : VOPC_F64 , "v_cmp_lt_f64", COND_OLT>; +defm V_CMP_EQ_F64 : VOPC_F64 , "v_cmp_eq_f64", COND_OEQ>; +defm V_CMP_LE_F64 : VOPC_F64 , "v_cmp_le_f64", COND_OLE>; +defm V_CMP_GT_F64 : VOPC_F64 , "v_cmp_gt_f64", COND_OGT>; +defm V_CMP_LG_F64 : VOPC_F64 , "v_cmp_lg_f64">; +defm V_CMP_GE_F64 : VOPC_F64 , "v_cmp_ge_f64", COND_OGE>; +defm V_CMP_O_F64 : VOPC_F64 , "v_cmp_o_f64", COND_O>; +defm V_CMP_U_F64 : VOPC_F64 , "v_cmp_u_f64", COND_UO>; +defm V_CMP_NGE_F64 : VOPC_F64 , "v_cmp_nge_f64">; +defm V_CMP_NLG_F64 : VOPC_F64 , "v_cmp_nlg_f64">; +defm V_CMP_NGT_F64 : VOPC_F64 , "v_cmp_ngt_f64">; +defm V_CMP_NLE_F64 : VOPC_F64 , "v_cmp_nle_f64">; +defm V_CMP_NEQ_F64 : VOPC_F64 , "v_cmp_neq_f64", COND_UNE>; +defm V_CMP_NLT_F64 : VOPC_F64 , "v_cmp_nlt_f64">; +defm V_CMP_TRU_F64 : VOPC_F64 , "v_cmp_tru_f64">; let hasSideEffects = 1 in { -defm V_CMPX_F_F64 : VOPCX_F64 , "V_CMPX_F_F64">; -defm V_CMPX_LT_F64 : VOPCX_F64 , "V_CMPX_LT_F64">; -defm V_CMPX_EQ_F64 : VOPCX_F64 , "V_CMPX_EQ_F64">; -defm V_CMPX_LE_F64 : VOPCX_F64 , "V_CMPX_LE_F64">; -defm V_CMPX_GT_F64 : VOPCX_F64 , "V_CMPX_GT_F64">; -defm V_CMPX_LG_F64 : VOPCX_F64 , "V_CMPX_LG_F64">; -defm V_CMPX_GE_F64 : VOPCX_F64 , "V_CMPX_GE_F64">; -defm V_CMPX_O_F64 : VOPCX_F64 , "V_CMPX_O_F64">; -defm V_CMPX_U_F64 : VOPCX_F64 , "V_CMPX_U_F64">; -defm V_CMPX_NGE_F64 : VOPCX_F64 , "V_CMPX_NGE_F64">; -defm V_CMPX_NLG_F64 : VOPCX_F64 , "V_CMPX_NLG_F64">; -defm V_CMPX_NGT_F64 : VOPCX_F64 , "V_CMPX_NGT_F64">; -defm V_CMPX_NLE_F64 : VOPCX_F64 , "V_CMPX_NLE_F64">; -defm V_CMPX_NEQ_F64 : VOPCX_F64 , "V_CMPX_NEQ_F64">; -defm V_CMPX_NLT_F64 : VOPCX_F64 , "V_CMPX_NLT_F64">; -defm V_CMPX_TRU_F64 : VOPCX_F64 , "V_CMPX_TRU_F64">; +defm V_CMPX_F_F64 : VOPCX_F64 , "v_cmpx_f_f64">; +defm V_CMPX_LT_F64 : VOPCX_F64 , "v_cmpx_lt_f64">; +defm V_CMPX_EQ_F64 : VOPCX_F64 , "v_cmpx_eq_f64">; +defm V_CMPX_LE_F64 : VOPCX_F64 , "v_cmpx_le_f64">; +defm V_CMPX_GT_F64 : VOPCX_F64 , "v_cmpx_gt_f64">; +defm V_CMPX_LG_F64 : VOPCX_F64 , "v_cmpx_lg_f64">; +defm V_CMPX_GE_F64 : VOPCX_F64 , "v_cmpx_ge_f64">; +defm V_CMPX_O_F64 : VOPCX_F64 , "v_cmpx_o_f64">; +defm V_CMPX_U_F64 : VOPCX_F64 , "v_cmpx_u_f64">; +defm V_CMPX_NGE_F64 : VOPCX_F64 , "v_cmpx_nge_f64">; +defm V_CMPX_NLG_F64 : VOPCX_F64 , "v_cmpx_nlg_f64">; +defm V_CMPX_NGT_F64 : VOPCX_F64 , "v_cmpx_ngt_f64">; +defm V_CMPX_NLE_F64 : VOPCX_F64 , "v_cmpx_nle_f64">; +defm V_CMPX_NEQ_F64 : VOPCX_F64 , "v_cmpx_neq_f64">; +defm V_CMPX_NLT_F64 : VOPCX_F64 , "v_cmpx_nlt_f64">; +defm V_CMPX_TRU_F64 : VOPCX_F64 , "v_cmpx_tru_f64">; } // End hasSideEffects = 1 -defm V_CMPS_F_F32 : VOPC_F32 , "V_CMPS_F_F32">; -defm V_CMPS_LT_F32 : VOPC_F32 , "V_CMPS_LT_F32">; -defm V_CMPS_EQ_F32 : VOPC_F32 , "V_CMPS_EQ_F32">; -defm V_CMPS_LE_F32 : VOPC_F32 , "V_CMPS_LE_F32">; -defm V_CMPS_GT_F32 : VOPC_F32 , "V_CMPS_GT_F32">; -defm V_CMPS_LG_F32 : VOPC_F32 , "V_CMPS_LG_F32">; -defm V_CMPS_GE_F32 : VOPC_F32 , "V_CMPS_GE_F32">; -defm V_CMPS_O_F32 : VOPC_F32 , "V_CMPS_O_F32">; -defm V_CMPS_U_F32 : VOPC_F32 , "V_CMPS_U_F32">; -defm V_CMPS_NGE_F32 : VOPC_F32 , "V_CMPS_NGE_F32">; -defm V_CMPS_NLG_F32 : VOPC_F32 , "V_CMPS_NLG_F32">; -defm V_CMPS_NGT_F32 : VOPC_F32 , "V_CMPS_NGT_F32">; -defm V_CMPS_NLE_F32 : VOPC_F32 , "V_CMPS_NLE_F32">; -defm V_CMPS_NEQ_F32 : VOPC_F32 , "V_CMPS_NEQ_F32">; -defm V_CMPS_NLT_F32 : VOPC_F32 , "V_CMPS_NLT_F32">; -defm V_CMPS_TRU_F32 : VOPC_F32 , "V_CMPS_TRU_F32">; +defm V_CMPS_F_F32 : VOPC_F32 , "v_cmps_f_f32">; +defm V_CMPS_LT_F32 : VOPC_F32 , "v_cmps_lt_f32">; +defm V_CMPS_EQ_F32 : VOPC_F32 , "v_cmps_eq_f32">; +defm V_CMPS_LE_F32 : VOPC_F32 , "v_cmps_le_f32">; +defm V_CMPS_GT_F32 : VOPC_F32 , "v_cmps_gt_f32">; +defm V_CMPS_LG_F32 : VOPC_F32 , "v_cmps_lg_f32">; +defm V_CMPS_GE_F32 : VOPC_F32 , "v_cmps_ge_f32">; +defm V_CMPS_O_F32 : VOPC_F32 , "v_cmps_o_f32">; +defm V_CMPS_U_F32 : VOPC_F32 , "v_cmps_u_f32">; +defm V_CMPS_NGE_F32 : VOPC_F32 , "v_cmps_nge_f32">; +defm V_CMPS_NLG_F32 : VOPC_F32 , "v_cmps_nlg_f32">; +defm V_CMPS_NGT_F32 : VOPC_F32 , "v_cmps_ngt_f32">; +defm V_CMPS_NLE_F32 : VOPC_F32 , "v_cmps_nle_f32">; +defm V_CMPS_NEQ_F32 : VOPC_F32 , "v_cmps_neq_f32">; +defm V_CMPS_NLT_F32 : VOPC_F32 , "v_cmps_nlt_f32">; +defm V_CMPS_TRU_F32 : VOPC_F32 , "v_cmps_tru_f32">; let hasSideEffects = 1 in { -defm V_CMPSX_F_F32 : VOPCX_F32 , "V_CMPSX_F_F32">; -defm V_CMPSX_LT_F32 : VOPCX_F32 , "V_CMPSX_LT_F32">; -defm V_CMPSX_EQ_F32 : VOPCX_F32 , "V_CMPSX_EQ_F32">; -defm V_CMPSX_LE_F32 : VOPCX_F32 , "V_CMPSX_LE_F32">; -defm V_CMPSX_GT_F32 : VOPCX_F32 , "V_CMPSX_GT_F32">; -defm V_CMPSX_LG_F32 : VOPCX_F32 , "V_CMPSX_LG_F32">; -defm V_CMPSX_GE_F32 : VOPCX_F32 , "V_CMPSX_GE_F32">; -defm V_CMPSX_O_F32 : VOPCX_F32 , "V_CMPSX_O_F32">; -defm V_CMPSX_U_F32 : VOPCX_F32 , "V_CMPSX_U_F32">; -defm V_CMPSX_NGE_F32 : VOPCX_F32 , "V_CMPSX_NGE_F32">; -defm V_CMPSX_NLG_F32 : VOPCX_F32 , "V_CMPSX_NLG_F32">; -defm V_CMPSX_NGT_F32 : VOPCX_F32 , "V_CMPSX_NGT_F32">; -defm V_CMPSX_NLE_F32 : VOPCX_F32 , "V_CMPSX_NLE_F32">; -defm V_CMPSX_NEQ_F32 : VOPCX_F32 , "V_CMPSX_NEQ_F32">; -defm V_CMPSX_NLT_F32 : VOPCX_F32 , "V_CMPSX_NLT_F32">; -defm V_CMPSX_TRU_F32 : VOPCX_F32 , "V_CMPSX_TRU_F32">; +defm V_CMPSX_F_F32 : VOPCX_F32 , "v_cmpsx_f_f32">; +defm V_CMPSX_LT_F32 : VOPCX_F32 , "v_cmpsx_lt_f32">; +defm V_CMPSX_EQ_F32 : VOPCX_F32 , "v_cmpsx_eq_f32">; +defm V_CMPSX_LE_F32 : VOPCX_F32 , "v_cmpsx_le_f32">; +defm V_CMPSX_GT_F32 : VOPCX_F32 , "v_cmpsx_gt_f32">; +defm V_CMPSX_LG_F32 : VOPCX_F32 , "v_cmpsx_lg_f32">; +defm V_CMPSX_GE_F32 : VOPCX_F32 , "v_cmpsx_ge_f32">; +defm V_CMPSX_O_F32 : VOPCX_F32 , "v_cmpsx_o_f32">; +defm V_CMPSX_U_F32 : VOPCX_F32 , "v_cmpsx_u_f32">; +defm V_CMPSX_NGE_F32 : VOPCX_F32 , "v_cmpsx_nge_f32">; +defm V_CMPSX_NLG_F32 : VOPCX_F32 , "v_cmpsx_nlg_f32">; +defm V_CMPSX_NGT_F32 : VOPCX_F32 , "v_cmpsx_ngt_f32">; +defm V_CMPSX_NLE_F32 : VOPCX_F32 , "v_cmpsx_nle_f32">; +defm V_CMPSX_NEQ_F32 : VOPCX_F32 , "v_cmpsx_neq_f32">; +defm V_CMPSX_NLT_F32 : VOPCX_F32 , "v_cmpsx_nlt_f32">; +defm V_CMPSX_TRU_F32 : VOPCX_F32 , "v_cmpsx_tru_f32">; } // End hasSideEffects = 1 -defm V_CMPS_F_F64 : VOPC_F64 , "V_CMPS_F_F64">; -defm V_CMPS_LT_F64 : VOPC_F64 , "V_CMPS_LT_F64">; -defm V_CMPS_EQ_F64 : VOPC_F64 , "V_CMPS_EQ_F64">; -defm V_CMPS_LE_F64 : VOPC_F64 , "V_CMPS_LE_F64">; -defm V_CMPS_GT_F64 : VOPC_F64 , "V_CMPS_GT_F64">; -defm V_CMPS_LG_F64 : VOPC_F64 , "V_CMPS_LG_F64">; -defm V_CMPS_GE_F64 : VOPC_F64 , "V_CMPS_GE_F64">; -defm V_CMPS_O_F64 : VOPC_F64 , "V_CMPS_O_F64">; -defm V_CMPS_U_F64 : VOPC_F64 , "V_CMPS_U_F64">; -defm V_CMPS_NGE_F64 : VOPC_F64 , "V_CMPS_NGE_F64">; -defm V_CMPS_NLG_F64 : VOPC_F64 , "V_CMPS_NLG_F64">; -defm V_CMPS_NGT_F64 : VOPC_F64 , "V_CMPS_NGT_F64">; -defm V_CMPS_NLE_F64 : VOPC_F64 , "V_CMPS_NLE_F64">; -defm V_CMPS_NEQ_F64 : VOPC_F64 , "V_CMPS_NEQ_F64">; -defm V_CMPS_NLT_F64 : VOPC_F64 , "V_CMPS_NLT_F64">; -defm V_CMPS_TRU_F64 : VOPC_F64 , "V_CMPS_TRU_F64">; +defm V_CMPS_F_F64 : VOPC_F64 , "v_cmps_f_f64">; +defm V_CMPS_LT_F64 : VOPC_F64 , "v_cmps_lt_f64">; +defm V_CMPS_EQ_F64 : VOPC_F64 , "v_cmps_eq_f64">; +defm V_CMPS_LE_F64 : VOPC_F64 , "v_cmps_le_f64">; +defm V_CMPS_GT_F64 : VOPC_F64 , "v_cmps_gt_f64">; +defm V_CMPS_LG_F64 : VOPC_F64 , "v_cmps_lg_f64">; +defm V_CMPS_GE_F64 : VOPC_F64 , "v_cmps_ge_f64">; +defm V_CMPS_O_F64 : VOPC_F64 , "v_cmps_o_f64">; +defm V_CMPS_U_F64 : VOPC_F64 , "v_cmps_u_f64">; +defm V_CMPS_NGE_F64 : VOPC_F64 , "v_cmps_nge_f64">; +defm V_CMPS_NLG_F64 : VOPC_F64 , "v_cmps_nlg_f64">; +defm V_CMPS_NGT_F64 : VOPC_F64 , "v_cmps_ngt_f64">; +defm V_CMPS_NLE_F64 : VOPC_F64 , "v_cmps_nle_f64">; +defm V_CMPS_NEQ_F64 : VOPC_F64 , "v_cmps_neq_f64">; +defm V_CMPS_NLT_F64 : VOPC_F64 , "v_cmps_nlt_f64">; +defm V_CMPS_TRU_F64 : VOPC_F64 , "v_cmps_tru_f64">; let hasSideEffects = 1, Defs = [EXEC] in { -defm V_CMPSX_F_F64 : VOPC_F64 , "V_CMPSX_F_F64">; -defm V_CMPSX_LT_F64 : VOPC_F64 , "V_CMPSX_LT_F64">; -defm V_CMPSX_EQ_F64 : VOPC_F64 , "V_CMPSX_EQ_F64">; -defm V_CMPSX_LE_F64 : VOPC_F64 , "V_CMPSX_LE_F64">; -defm V_CMPSX_GT_F64 : VOPC_F64 , "V_CMPSX_GT_F64">; -defm V_CMPSX_LG_F64 : VOPC_F64 , "V_CMPSX_LG_F64">; -defm V_CMPSX_GE_F64 : VOPC_F64 , "V_CMPSX_GE_F64">; -defm V_CMPSX_O_F64 : VOPC_F64 , "V_CMPSX_O_F64">; -defm V_CMPSX_U_F64 : VOPC_F64 , "V_CMPSX_U_F64">; -defm V_CMPSX_NGE_F64 : VOPC_F64 , "V_CMPSX_NGE_F64">; -defm V_CMPSX_NLG_F64 : VOPC_F64 , "V_CMPSX_NLG_F64">; -defm V_CMPSX_NGT_F64 : VOPC_F64 , "V_CMPSX_NGT_F64">; -defm V_CMPSX_NLE_F64 : VOPC_F64 , "V_CMPSX_NLE_F64">; -defm V_CMPSX_NEQ_F64 : VOPC_F64 , "V_CMPSX_NEQ_F64">; -defm V_CMPSX_NLT_F64 : VOPC_F64 , "V_CMPSX_NLT_F64">; -defm V_CMPSX_TRU_F64 : VOPC_F64 , "V_CMPSX_TRU_F64">; +defm V_CMPSX_F_F64 : VOPC_F64 , "v_cmpsx_f_f64">; +defm V_CMPSX_LT_F64 : VOPC_F64 , "v_cmpsx_lt_f64">; +defm V_CMPSX_EQ_F64 : VOPC_F64 , "v_cmpsx_eq_f64">; +defm V_CMPSX_LE_F64 : VOPC_F64 , "v_cmpsx_le_f64">; +defm V_CMPSX_GT_F64 : VOPC_F64 , "v_cmpsx_gt_f64">; +defm V_CMPSX_LG_F64 : VOPC_F64 , "v_cmpsx_lg_f64">; +defm V_CMPSX_GE_F64 : VOPC_F64 , "v_cmpsx_ge_f64">; +defm V_CMPSX_O_F64 : VOPC_F64 , "v_cmpsx_o_f64">; +defm V_CMPSX_U_F64 : VOPC_F64 , "v_cmpsx_u_f64">; +defm V_CMPSX_NGE_F64 : VOPC_F64 , "v_cmpsx_nge_f64">; +defm V_CMPSX_NLG_F64 : VOPC_F64 , "v_cmpsx_nlg_f64">; +defm V_CMPSX_NGT_F64 : VOPC_F64 , "v_cmpsx_ngt_f64">; +defm V_CMPSX_NLE_F64 : VOPC_F64 , "v_cmpsx_nle_f64">; +defm V_CMPSX_NEQ_F64 : VOPC_F64 , "v_cmpsx_neq_f64">; +defm V_CMPSX_NLT_F64 : VOPC_F64 , "v_cmpsx_nlt_f64">; +defm V_CMPSX_TRU_F64 : VOPC_F64 , "v_cmpsx_tru_f64">; } // End hasSideEffects = 1, Defs = [EXEC] -defm V_CMP_F_I32 : VOPC_I32 , "V_CMP_F_I32">; -defm V_CMP_LT_I32 : VOPC_I32 , "V_CMP_LT_I32", COND_SLT>; -defm V_CMP_EQ_I32 : VOPC_I32 , "V_CMP_EQ_I32", COND_EQ>; -defm V_CMP_LE_I32 : VOPC_I32 , "V_CMP_LE_I32", COND_SLE>; -defm V_CMP_GT_I32 : VOPC_I32 , "V_CMP_GT_I32", COND_SGT>; -defm V_CMP_NE_I32 : VOPC_I32 , "V_CMP_NE_I32", COND_NE>; -defm V_CMP_GE_I32 : VOPC_I32 , "V_CMP_GE_I32", COND_SGE>; -defm V_CMP_T_I32 : VOPC_I32 , "V_CMP_T_I32">; +defm V_CMP_F_I32 : VOPC_I32 , "v_cmp_f_i32">; +defm V_CMP_LT_I32 : VOPC_I32 , "v_cmp_lt_i32", COND_SLT>; +defm V_CMP_EQ_I32 : VOPC_I32 , "v_cmp_eq_i32", COND_EQ>; +defm V_CMP_LE_I32 : VOPC_I32 , "v_cmp_le_i32", COND_SLE>; +defm V_CMP_GT_I32 : VOPC_I32 , "v_cmp_gt_i32", COND_SGT>; +defm V_CMP_NE_I32 : VOPC_I32 , "v_cmp_ne_i32", COND_NE>; +defm V_CMP_GE_I32 : VOPC_I32 , "v_cmp_ge_i32", COND_SGE>; +defm V_CMP_T_I32 : VOPC_I32 , "v_cmp_t_i32">; let hasSideEffects = 1 in { -defm V_CMPX_F_I32 : VOPCX_I32 , "V_CMPX_F_I32">; -defm V_CMPX_LT_I32 : VOPCX_I32 , "V_CMPX_LT_I32">; -defm V_CMPX_EQ_I32 : VOPCX_I32 , "V_CMPX_EQ_I32">; -defm V_CMPX_LE_I32 : VOPCX_I32 , "V_CMPX_LE_I32">; -defm V_CMPX_GT_I32 : VOPCX_I32 , "V_CMPX_GT_I32">; -defm V_CMPX_NE_I32 : VOPCX_I32 , "V_CMPX_NE_I32">; -defm V_CMPX_GE_I32 : VOPCX_I32 , "V_CMPX_GE_I32">; -defm V_CMPX_T_I32 : VOPCX_I32 , "V_CMPX_T_I32">; +defm V_CMPX_F_I32 : VOPCX_I32 , "v_cmpx_f_i32">; +defm V_CMPX_LT_I32 : VOPCX_I32 , "v_cmpx_lt_i32">; +defm V_CMPX_EQ_I32 : VOPCX_I32 , "v_cmpx_eq_i32">; +defm V_CMPX_LE_I32 : VOPCX_I32 , "v_cmpx_le_i32">; +defm V_CMPX_GT_I32 : VOPCX_I32 , "v_cmpx_gt_i32">; +defm V_CMPX_NE_I32 : VOPCX_I32 , "v_cmpx_ne_i32">; +defm V_CMPX_GE_I32 : VOPCX_I32 , "v_cmpx_ge_i32">; +defm V_CMPX_T_I32 : VOPCX_I32 , "v_cmpx_t_i32">; } // End hasSideEffects = 1 -defm V_CMP_F_I64 : VOPC_I64 , "V_CMP_F_I64">; -defm V_CMP_LT_I64 : VOPC_I64 , "V_CMP_LT_I64", COND_SLT>; -defm V_CMP_EQ_I64 : VOPC_I64 , "V_CMP_EQ_I64", COND_EQ>; -defm V_CMP_LE_I64 : VOPC_I64 , "V_CMP_LE_I64", COND_SLE>; -defm V_CMP_GT_I64 : VOPC_I64 , "V_CMP_GT_I64", COND_SGT>; -defm V_CMP_NE_I64 : VOPC_I64 , "V_CMP_NE_I64", COND_NE>; -defm V_CMP_GE_I64 : VOPC_I64 , "V_CMP_GE_I64", COND_SGE>; -defm V_CMP_T_I64 : VOPC_I64 , "V_CMP_T_I64">; +defm V_CMP_F_I64 : VOPC_I64 , "v_cmp_f_i64">; +defm V_CMP_LT_I64 : VOPC_I64 , "v_cmp_lt_i64", COND_SLT>; +defm V_CMP_EQ_I64 : VOPC_I64 , "v_cmp_eq_i64", COND_EQ>; +defm V_CMP_LE_I64 : VOPC_I64 , "v_cmp_le_i64", COND_SLE>; +defm V_CMP_GT_I64 : VOPC_I64 , "v_cmp_gt_i64", COND_SGT>; +defm V_CMP_NE_I64 : VOPC_I64 , "v_cmp_ne_i64", COND_NE>; +defm V_CMP_GE_I64 : VOPC_I64 , "v_cmp_ge_i64", COND_SGE>; +defm V_CMP_T_I64 : VOPC_I64 , "v_cmp_t_i64">; let hasSideEffects = 1 in { -defm V_CMPX_F_I64 : VOPCX_I64 , "V_CMPX_F_I64">; -defm V_CMPX_LT_I64 : VOPCX_I64 , "V_CMPX_LT_I64">; -defm V_CMPX_EQ_I64 : VOPCX_I64 , "V_CMPX_EQ_I64">; -defm V_CMPX_LE_I64 : VOPCX_I64 , "V_CMPX_LE_I64">; -defm V_CMPX_GT_I64 : VOPCX_I64 , "V_CMPX_GT_I64">; -defm V_CMPX_NE_I64 : VOPCX_I64 , "V_CMPX_NE_I64">; -defm V_CMPX_GE_I64 : VOPCX_I64 , "V_CMPX_GE_I64">; -defm V_CMPX_T_I64 : VOPCX_I64 , "V_CMPX_T_I64">; +defm V_CMPX_F_I64 : VOPCX_I64 , "v_cmpx_f_i64">; +defm V_CMPX_LT_I64 : VOPCX_I64 , "v_cmpx_lt_i64">; +defm V_CMPX_EQ_I64 : VOPCX_I64 , "v_cmpx_eq_i64">; +defm V_CMPX_LE_I64 : VOPCX_I64 , "v_cmpx_le_i64">; +defm V_CMPX_GT_I64 : VOPCX_I64 , "v_cmpx_gt_i64">; +defm V_CMPX_NE_I64 : VOPCX_I64 , "v_cmpx_ne_i64">; +defm V_CMPX_GE_I64 : VOPCX_I64 , "v_cmpx_ge_i64">; +defm V_CMPX_T_I64 : VOPCX_I64 , "v_cmpx_t_i64">; } // End hasSideEffects = 1 -defm V_CMP_F_U32 : VOPC_I32 , "V_CMP_F_U32">; -defm V_CMP_LT_U32 : VOPC_I32 , "V_CMP_LT_U32", COND_ULT>; -defm V_CMP_EQ_U32 : VOPC_I32 , "V_CMP_EQ_U32", COND_EQ>; -defm V_CMP_LE_U32 : VOPC_I32 , "V_CMP_LE_U32", COND_ULE>; -defm V_CMP_GT_U32 : VOPC_I32 , "V_CMP_GT_U32", COND_UGT>; -defm V_CMP_NE_U32 : VOPC_I32 , "V_CMP_NE_U32", COND_NE>; -defm V_CMP_GE_U32 : VOPC_I32 , "V_CMP_GE_U32", COND_UGE>; -defm V_CMP_T_U32 : VOPC_I32 , "V_CMP_T_U32">; +defm V_CMP_F_U32 : VOPC_I32 , "v_cmp_f_u32">; +defm V_CMP_LT_U32 : VOPC_I32 , "v_cmp_lt_u32", COND_ULT>; +defm V_CMP_EQ_U32 : VOPC_I32 , "v_cmp_eq_u32", COND_EQ>; +defm V_CMP_LE_U32 : VOPC_I32 , "v_cmp_le_u32", COND_ULE>; +defm V_CMP_GT_U32 : VOPC_I32 , "v_cmp_gt_u32", COND_UGT>; +defm V_CMP_NE_U32 : VOPC_I32 , "v_cmp_ne_u32", COND_NE>; +defm V_CMP_GE_U32 : VOPC_I32 , "v_cmp_ge_u32", COND_UGE>; +defm V_CMP_T_U32 : VOPC_I32 , "v_cmp_t_u32">; let hasSideEffects = 1 in { -defm V_CMPX_F_U32 : VOPCX_I32 , "V_CMPX_F_U32">; -defm V_CMPX_LT_U32 : VOPCX_I32 , "V_CMPX_LT_U32">; -defm V_CMPX_EQ_U32 : VOPCX_I32 , "V_CMPX_EQ_U32">; -defm V_CMPX_LE_U32 : VOPCX_I32 , "V_CMPX_LE_U32">; -defm V_CMPX_GT_U32 : VOPCX_I32 , "V_CMPX_GT_U32">; -defm V_CMPX_NE_U32 : VOPCX_I32 , "V_CMPX_NE_U32">; -defm V_CMPX_GE_U32 : VOPCX_I32 , "V_CMPX_GE_U32">; -defm V_CMPX_T_U32 : VOPCX_I32 , "V_CMPX_T_U32">; +defm V_CMPX_F_U32 : VOPCX_I32 , "v_cmpx_f_u32">; +defm V_CMPX_LT_U32 : VOPCX_I32 , "v_cmpx_lt_u32">; +defm V_CMPX_EQ_U32 : VOPCX_I32 , "v_cmpx_eq_u32">; +defm V_CMPX_LE_U32 : VOPCX_I32 , "v_cmpx_le_u32">; +defm V_CMPX_GT_U32 : VOPCX_I32 , "v_cmpx_gt_u32">; +defm V_CMPX_NE_U32 : VOPCX_I32 , "v_cmpx_ne_u32">; +defm V_CMPX_GE_U32 : VOPCX_I32 , "v_cmpx_ge_u32">; +defm V_CMPX_T_U32 : VOPCX_I32 , "v_cmpx_t_u32">; } // End hasSideEffects = 1 -defm V_CMP_F_U64 : VOPC_I64 , "V_CMP_F_U64">; -defm V_CMP_LT_U64 : VOPC_I64 , "V_CMP_LT_U64", COND_ULT>; -defm V_CMP_EQ_U64 : VOPC_I64 , "V_CMP_EQ_U64", COND_EQ>; -defm V_CMP_LE_U64 : VOPC_I64 , "V_CMP_LE_U64", COND_ULE>; -defm V_CMP_GT_U64 : VOPC_I64 , "V_CMP_GT_U64", COND_UGT>; -defm V_CMP_NE_U64 : VOPC_I64 , "V_CMP_NE_U64", COND_NE>; -defm V_CMP_GE_U64 : VOPC_I64 , "V_CMP_GE_U64", COND_UGE>; -defm V_CMP_T_U64 : VOPC_I64 , "V_CMP_T_U64">; +defm V_CMP_F_U64 : VOPC_I64 , "v_cmp_f_u64">; +defm V_CMP_LT_U64 : VOPC_I64 , "v_cmp_lt_u64", COND_ULT>; +defm V_CMP_EQ_U64 : VOPC_I64 , "v_cmp_eq_u64", COND_EQ>; +defm V_CMP_LE_U64 : VOPC_I64 , "v_cmp_le_u64", COND_ULE>; +defm V_CMP_GT_U64 : VOPC_I64 , "v_cmp_gt_u64", COND_UGT>; +defm V_CMP_NE_U64 : VOPC_I64 , "v_cmp_ne_u64", COND_NE>; +defm V_CMP_GE_U64 : VOPC_I64 , "v_cmp_ge_u64", COND_UGE>; +defm V_CMP_T_U64 : VOPC_I64 , "v_cmp_t_u64">; let hasSideEffects = 1 in { -defm V_CMPX_F_U64 : VOPCX_I64 , "V_CMPX_F_U64">; -defm V_CMPX_LT_U64 : VOPCX_I64 , "V_CMPX_LT_U64">; -defm V_CMPX_EQ_U64 : VOPCX_I64 , "V_CMPX_EQ_U64">; -defm V_CMPX_LE_U64 : VOPCX_I64 , "V_CMPX_LE_U64">; -defm V_CMPX_GT_U64 : VOPCX_I64 , "V_CMPX_GT_U64">; -defm V_CMPX_NE_U64 : VOPCX_I64 , "V_CMPX_NE_U64">; -defm V_CMPX_GE_U64 : VOPCX_I64 , "V_CMPX_GE_U64">; -defm V_CMPX_T_U64 : VOPCX_I64 , "V_CMPX_T_U64">; +defm V_CMPX_F_U64 : VOPCX_I64 , "v_cmpx_f_u64">; +defm V_CMPX_LT_U64 : VOPCX_I64 , "v_cmpx_lt_u64">; +defm V_CMPX_EQ_U64 : VOPCX_I64 , "v_cmpx_eq_u64">; +defm V_CMPX_LE_U64 : VOPCX_I64 , "v_cmpx_le_u64">; +defm V_CMPX_GT_U64 : VOPCX_I64 , "v_cmpx_gt_u64">; +defm V_CMPX_NE_U64 : VOPCX_I64 , "v_cmpx_ne_u64">; +defm V_CMPX_GE_U64 : VOPCX_I64 , "v_cmpx_ge_u64">; +defm V_CMPX_T_U64 : VOPCX_I64 , "v_cmpx_t_u64">; } // End hasSideEffects = 1 -defm V_CMP_CLASS_F32 : VOPC_F32 , "V_CMP_CLASS_F32">; +defm V_CMP_CLASS_F32 : VOPC_F32 , "v_cmp_class_f32">; let hasSideEffects = 1 in { -defm V_CMPX_CLASS_F32 : VOPCX_F32 , "V_CMPX_CLASS_F32">; +defm V_CMPX_CLASS_F32 : VOPCX_F32 , "v_cmpx_class_f32">; } // End hasSideEffects = 1 -defm V_CMP_CLASS_F64 : VOPC_F64 , "V_CMP_CLASS_F64">; +defm V_CMP_CLASS_F64 : VOPC_F64 , "v_cmp_class_f64">; let hasSideEffects = 1 in { -defm V_CMPX_CLASS_F64 : VOPCX_F64 , "V_CMPX_CLASS_F64">; +defm V_CMPX_CLASS_F64 : VOPCX_F64 , "v_cmpx_class_f64">; } // End hasSideEffects = 1 } // End isCompare = 1 @@ -729,88 +729,88 @@ defm V_CMPX_CLASS_F64 : VOPCX_F64 , "V_CMPX_CLASS_F64">; //===----------------------------------------------------------------------===// -def DS_ADD_U32 : DS_1A1D_NORET <0x0, "DS_ADD_U32", VReg_32>; -def DS_SUB_U32 : DS_1A1D_NORET <0x1, "DS_SUB_U32", VReg_32>; -def DS_RSUB_U32 : DS_1A1D_NORET <0x2, "DS_RSUB_U32", VReg_32>; -def DS_INC_U32 : DS_1A1D_NORET <0x3, "DS_INC_U32", VReg_32>; -def DS_DEC_U32 : DS_1A1D_NORET <0x4, "DS_DEC_U32", VReg_32>; -def DS_MIN_I32 : DS_1A1D_NORET <0x5, "DS_MIN_I32", VReg_32>; -def DS_MAX_I32 : DS_1A1D_NORET <0x6, "DS_MAX_I32", VReg_32>; -def DS_MIN_U32 : DS_1A1D_NORET <0x7, "DS_MIN_U32", VReg_32>; -def DS_MAX_U32 : DS_1A1D_NORET <0x8, "DS_MAX_U32", VReg_32>; -def DS_AND_B32 : DS_1A1D_NORET <0x9, "DS_AND_B32", VReg_32>; -def DS_OR_B32 : DS_1A1D_NORET <0xa, "DS_OR_B32", VReg_32>; -def DS_XOR_B32 : DS_1A1D_NORET <0xb, "DS_XOR_B32", VReg_32>; -def DS_MSKOR_B32 : DS_1A1D_NORET <0xc, "DS_MSKOR_B32", VReg_32>; -def DS_CMPST_B32 : DS_1A2D_NORET <0x10, "DS_CMPST_B32", VReg_32>; -def DS_CMPST_F32 : DS_1A2D_NORET <0x11, "DS_CMPST_F32", VReg_32>; -def DS_MIN_F32 : DS_1A1D_NORET <0x12, "DS_MIN_F32", VReg_32>; -def DS_MAX_F32 : DS_1A1D_NORET <0x13, "DS_MAX_F32", VReg_32>; - -def DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "DS_ADD_RTN_U32", VReg_32, "DS_ADD_U32">; -def DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "DS_SUB_RTN_U32", VReg_32, "DS_SUB_U32">; -def DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "DS_RSUB_RTN_U32", VReg_32, "DS_RSUB_U32">; -def DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "DS_INC_RTN_U32", VReg_32, "DS_INC_U32">; -def DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "DS_DEC_RTN_U32", VReg_32, "DS_DEC_U32">; -def DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "DS_MIN_RTN_I32", VReg_32, "DS_MIN_I32">; -def DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "DS_MAX_RTN_I32", VReg_32, "DS_MAX_I32">; -def DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "DS_MIN_RTN_U32", VReg_32, "DS_MIN_U32">; -def DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "DS_MAX_RTN_U32", VReg_32, "DS_MAX_U32">; -def DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "DS_AND_RTN_B32", VReg_32, "DS_AND_B32">; -def DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "DS_OR_RTN_B32", VReg_32, "DS_OR_B32">; -def DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "DS_XOR_RTN_B32", VReg_32, "DS_XOR_B32">; -def DS_MSKOR_RTN_B32 : DS_1A1D_RET <0x2c, "DS_MSKOR_RTN_B32", VReg_32, "DS_MSKOR_B32">; -def DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "DS_WRXCHG_RTN_B32", VReg_32>; -//def DS_WRXCHG2_RTN_B32 : DS_2A0D_RET <0x2e, "DS_WRXCHG2_RTN_B32", VReg_32, "DS_WRXCHG2_B32">; -//def DS_WRXCHG2ST64_RTN_B32 : DS_2A0D_RET <0x2f, "DS_WRXCHG2_RTN_B32", VReg_32, "DS_WRXCHG2ST64_B32">; -def DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "DS_CMPST_RTN_B32", VReg_32, "DS_CMPST_B32">; -def DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "DS_CMPST_RTN_F32", VReg_32, "DS_CMPST_F32">; -def DS_MIN_RTN_F32 : DS_1A1D_RET <0x32, "DS_MIN_RTN_F32", VReg_32, "DS_MIN_F32">; -def DS_MAX_RTN_F32 : DS_1A1D_RET <0x33, "DS_MAX_RTN_F32", VReg_32, "DS_MAX_F32">; +def DS_ADD_U32 : DS_1A1D_NORET <0x0, "ds_add_u32", VReg_32>; +def DS_SUB_U32 : DS_1A1D_NORET <0x1, "ds_sub_u32", VReg_32>; +def DS_RSUB_U32 : DS_1A1D_NORET <0x2, "ds_rsub_u32", VReg_32>; +def DS_INC_U32 : DS_1A1D_NORET <0x3, "ds_inc_u32", VReg_32>; +def DS_DEC_U32 : DS_1A1D_NORET <0x4, "ds_dec_u32", VReg_32>; +def DS_MIN_I32 : DS_1A1D_NORET <0x5, "ds_min_i32", VReg_32>; +def DS_MAX_I32 : DS_1A1D_NORET <0x6, "ds_max_i32", VReg_32>; +def DS_MIN_U32 : DS_1A1D_NORET <0x7, "ds_min_u32", VReg_32>; +def DS_MAX_U32 : DS_1A1D_NORET <0x8, "ds_max_u32", VReg_32>; +def DS_AND_B32 : DS_1A1D_NORET <0x9, "ds_and_b32", VReg_32>; +def DS_OR_B32 : DS_1A1D_NORET <0xa, "ds_or_b32", VReg_32>; +def DS_XOR_B32 : DS_1A1D_NORET <0xb, "ds_xor_b32", VReg_32>; +def DS_MSKOR_B32 : DS_1A1D_NORET <0xc, "ds_mskor_b32", VReg_32>; +def DS_CMPST_B32 : DS_1A2D_NORET <0x10, "ds_cmpst_b32", VReg_32>; +def DS_CMPST_F32 : DS_1A2D_NORET <0x11, "ds_cmpst_f32", VReg_32>; +def DS_MIN_F32 : DS_1A1D_NORET <0x12, "ds_min_f32", VReg_32>; +def DS_MAX_F32 : DS_1A1D_NORET <0x13, "ds_max_f32", VReg_32>; + +def DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VReg_32, "ds_add_u32">; +def DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "ds_sub_rtn_u32", VReg_32, "ds_sub_u32">; +def DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "ds_rsub_rtn_u32", VReg_32, "ds_rsub_u32">; +def DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "ds_inc_rtn_u32", VReg_32, "ds_inc_u32">; +def DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "ds_dec_rtn_u32", VReg_32, "ds_dec_u32">; +def DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "ds_min_rtn_i32", VReg_32, "ds_min_i32">; +def DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "ds_max_rtn_i32", VReg_32, "ds_max_i32">; +def DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "ds_min_rtn_u32", VReg_32, "ds_min_u32">; +def DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "ds_max_rtn_u32", VReg_32, "ds_max_u32">; +def DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "ds_and_rtn_b32", VReg_32, "ds_and_b32">; +def DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "ds_or_rtn_b32", VReg_32, "ds_or_b32">; +def DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "ds_xor_rtn_b32", VReg_32, "ds_xor_b32">; +def DS_MSKOR_RTN_B32 : DS_1A1D_RET <0x2c, "ds_mskor_rtn_b32", VReg_32, "ds_mskor_b32">; +def DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "ds_wrxchg_rtn_b32", VReg_32>; +//def DS_WRXCHG2_RTN_B32 : DS_2A0D_RET <0x2e, "ds_wrxchg2_rtn_b32", VReg_32, "ds_wrxchg2_b32">; +//def DS_WRXCHG2ST64_RTN_B32 : DS_2A0D_RET <0x2f, "ds_wrxchg2_rtn_b32", VReg_32, "ds_wrxchg2st64_b32">; +def DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "ds_cmpst_rtn_b32", VReg_32, "ds_cmpst_b32">; +def DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "ds_cmpst_rtn_f32", VReg_32, "ds_cmpst_f32">; +def DS_MIN_RTN_F32 : DS_1A1D_RET <0x32, "ds_min_rtn_f32", VReg_32, "ds_min_f32">; +def DS_MAX_RTN_F32 : DS_1A1D_RET <0x33, "ds_max_rtn_f32", VReg_32, "ds_max_f32">; let SubtargetPredicate = isCI in { -def DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "DS_WRAP_RTN_F32", VReg_32, "DS_WRAP_F32">; +def DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "ds_wrap_rtn_f32", VReg_32, "ds_wrap_f32">; } // End isCI -def DS_ADD_U64 : DS_1A1D_NORET <0x40, "DS_ADD_U64", VReg_64>; -def DS_SUB_U64 : DS_1A1D_NORET <0x41, "DS_SUB_U64", VReg_64>; -def DS_RSUB_U64 : DS_1A1D_NORET <0x42, "DS_RSUB_U64", VReg_64>; -def DS_INC_U64 : DS_1A1D_NORET <0x43, "DS_INC_U64", VReg_64>; -def DS_DEC_U64 : DS_1A1D_NORET <0x44, "DS_DEC_U64", VReg_64>; -def DS_MIN_I64 : DS_1A1D_NORET <0x45, "DS_MIN_I64", VReg_64>; -def DS_MAX_I64 : DS_1A1D_NORET <0x46, "DS_MAX_I64", VReg_64>; -def DS_MIN_U64 : DS_1A1D_NORET <0x47, "DS_MIN_U64", VReg_64>; -def DS_MAX_U64 : DS_1A1D_NORET <0x48, "DS_MAX_U64", VReg_64>; -def DS_AND_B64 : DS_1A1D_NORET <0x49, "DS_AND_B64", VReg_64>; -def DS_OR_B64 : DS_1A1D_NORET <0x4a, "DS_OR_B64", VReg_64>; -def DS_XOR_B64 : DS_1A1D_NORET <0x4b, "DS_XOR_B64", VReg_64>; -def DS_MSKOR_B64 : DS_1A1D_NORET <0x4c, "DS_MSKOR_B64", VReg_64>; -def DS_CMPST_B64 : DS_1A2D_NORET <0x50, "DS_CMPST_B64", VReg_64>; -def DS_CMPST_F64 : DS_1A2D_NORET <0x51, "DS_CMPST_F64", VReg_64>; -def DS_MIN_F64 : DS_1A1D_NORET <0x52, "DS_MIN_F64", VReg_64>; -def DS_MAX_F64 : DS_1A1D_NORET <0x53, "DS_MAX_F64", VReg_64>; - -def DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "DS_ADD_RTN_U64", VReg_64, "DS_ADD_U64">; -def DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "DS_SUB_RTN_U64", VReg_64, "DS_SUB_U64">; -def DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "DS_RSUB_RTN_U64", VReg_64, "DS_RSUB_U64">; -def DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "DS_INC_RTN_U64", VReg_64, "DS_INC_U64">; -def DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "DS_DEC_RTN_U64", VReg_64, "DS_DEC_U64">; -def DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "DS_MIN_RTN_I64", VReg_64, "DS_MIN_I64">; -def DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "DS_MAX_RTN_I64", VReg_64, "DS_MAX_I64">; -def DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "DS_MIN_RTN_U64", VReg_64, "DS_MIN_U64">; -def DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "DS_MAX_RTN_U64", VReg_64, "DS_MAX_U64">; -def DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "DS_AND_RTN_B64", VReg_64, "DS_AND_B64">; -def DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "DS_OR_RTN_B64", VReg_64, "DS_OR_B64">; -def DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "DS_XOR_RTN_B64", VReg_64, "DS_XOR_B64">; -def DS_MSKOR_RTN_B64 : DS_1A1D_RET <0x6c, "DS_MSKOR_RTN_B64", VReg_64, "DS_MSKOR_B64">; -def DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "DS_WRXCHG_RTN_B64", VReg_64, "DS_WRXCHG_B64">; -//def DS_WRXCHG2_RTN_B64 : DS_2A0D_RET <0x6e, "DS_WRXCHG2_RTN_B64", VReg_64, "DS_WRXCHG2_B64">; -//def DS_WRXCHG2ST64_RTN_B64 : DS_2A0D_RET <0x6f, "DS_WRXCHG2_RTN_B64", VReg_64, "DS_WRXCHG2ST64_B64">; -def DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "DS_CMPST_RTN_B64", VReg_64, "DS_CMPST_B64">; -def DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "DS_CMPST_RTN_F64", VReg_64, "DS_CMPST_F64">; -def DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "DS_MIN_F64", VReg_64, "DS_MIN_F64">; -def DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "DS_MAX_F64", VReg_64, "DS_MAX_F64">; +def DS_ADD_U64 : DS_1A1D_NORET <0x40, "ds_add_u64", VReg_64>; +def DS_SUB_U64 : DS_1A1D_NORET <0x41, "ds_sub_u64", VReg_64>; +def DS_RSUB_U64 : DS_1A1D_NORET <0x42, "ds_rsub_u64", VReg_64>; +def DS_INC_U64 : DS_1A1D_NORET <0x43, "ds_inc_u64", VReg_64>; +def DS_DEC_U64 : DS_1A1D_NORET <0x44, "ds_dec_u64", VReg_64>; +def DS_MIN_I64 : DS_1A1D_NORET <0x45, "ds_min_i64", VReg_64>; +def DS_MAX_I64 : DS_1A1D_NORET <0x46, "ds_max_i64", VReg_64>; +def DS_MIN_U64 : DS_1A1D_NORET <0x47, "ds_min_u64", VReg_64>; +def DS_MAX_U64 : DS_1A1D_NORET <0x48, "ds_max_u64", VReg_64>; +def DS_AND_B64 : DS_1A1D_NORET <0x49, "ds_and_b64", VReg_64>; +def DS_OR_B64 : DS_1A1D_NORET <0x4a, "ds_or_b64", VReg_64>; +def DS_XOR_B64 : DS_1A1D_NORET <0x4b, "ds_xor_b64", VReg_64>; +def DS_MSKOR_B64 : DS_1A1D_NORET <0x4c, "ds_mskor_b64", VReg_64>; +def DS_CMPST_B64 : DS_1A2D_NORET <0x50, "ds_cmpst_b64", VReg_64>; +def DS_CMPST_F64 : DS_1A2D_NORET <0x51, "ds_cmpst_f64", VReg_64>; +def DS_MIN_F64 : DS_1A1D_NORET <0x52, "ds_min_f64", VReg_64>; +def DS_MAX_F64 : DS_1A1D_NORET <0x53, "ds_max_f64", VReg_64>; + +def DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "ds_add_rtn_u64", VReg_64, "ds_add_u64">; +def DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "ds_sub_rtn_u64", VReg_64, "ds_sub_u64">; +def DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">; +def DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "ds_inc_rtn_u64", VReg_64, "ds_inc_u64">; +def DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "ds_dec_rtn_u64", VReg_64, "ds_dec_u64">; +def DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "ds_min_rtn_i64", VReg_64, "ds_min_i64">; +def DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "ds_max_rtn_i64", VReg_64, "ds_max_i64">; +def DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "ds_min_rtn_u64", VReg_64, "ds_min_u64">; +def DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "ds_max_rtn_u64", VReg_64, "ds_max_u64">; +def DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "ds_and_rtn_b64", VReg_64, "ds_and_b64">; +def DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "ds_or_rtn_b64", VReg_64, "ds_or_b64">; +def DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "ds_xor_rtn_b64", VReg_64, "ds_xor_b64">; +def DS_MSKOR_RTN_B64 : DS_1A1D_RET <0x6c, "ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">; +def DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "ds_wrxchg_rtn_b64", VReg_64, "ds_wrxchg_b64">; +//def DS_WRXCHG2_RTN_B64 : DS_2A0D_RET <0x6e, "ds_wrxchg2_rtn_b64", VReg_64, "ds_wrxchg2_b64">; +//def DS_WRXCHG2ST64_RTN_B64 : DS_2A0D_RET <0x6f, "ds_wrxchg2_rtn_b64", VReg_64, "ds_wrxchg2st64_b64">; +def DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">; +def DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">; +def DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "ds_min_f64", VReg_64, "ds_min_f64">; +def DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "ds_max_f64", VReg_64, "ds_max_f64">; //let SubtargetPredicate = isCI in { // DS_CONDXCHG32_RTN_B64 @@ -819,335 +819,335 @@ def DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "DS_MAX_F64", VReg_64, "DS_MAX_F64">; // TODO: _SRC2_* forms -def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>; -def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>; -def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>; -def DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "DS_WRITE_B64", VReg_64>; +def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "ds_write_b32", VReg_32>; +def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "ds_write_b8", VReg_32>; +def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "ds_write_b16", VReg_32>; +def DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "ds_write_b64", VReg_64>; -def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>; -def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>; -def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>; -def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>; -def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>; -def DS_READ_B64 : DS_Load_Helper <0x00000076, "DS_READ_B64", VReg_64>; +def DS_READ_B32 : DS_Load_Helper <0x00000036, "ds_read_b32", VReg_32>; +def DS_READ_I8 : DS_Load_Helper <0x00000039, "ds_read_i8", VReg_32>; +def DS_READ_U8 : DS_Load_Helper <0x0000003a, "ds_read_u8", VReg_32>; +def DS_READ_I16 : DS_Load_Helper <0x0000003b, "ds_read_i16", VReg_32>; +def DS_READ_U16 : DS_Load_Helper <0x0000003c, "ds_read_u16", VReg_32>; +def DS_READ_B64 : DS_Load_Helper <0x00000076, "ds_read_b64", VReg_64>; // 2 forms. -def DS_WRITE2_B32 : DS_Store2_Helper <0x0000000E, "DS_WRITE2_B32", VReg_32>; -def DS_WRITE2ST64_B32 : DS_Store2_Helper <0x0000000F, "DS_WRITE2ST64_B32", VReg_32>; -def DS_WRITE2_B64 : DS_Store2_Helper <0x0000004E, "DS_WRITE2_B64", VReg_64>; -def DS_WRITE2ST64_B64 : DS_Store2_Helper <0x0000004F, "DS_WRITE2ST64_B64", VReg_64>; +def DS_WRITE2_B32 : DS_Store2_Helper <0x0000000E, "ds_write2_b32", VReg_32>; +def DS_WRITE2ST64_B32 : DS_Store2_Helper <0x0000000F, "ds_write2st64_b32", VReg_32>; +def DS_WRITE2_B64 : DS_Store2_Helper <0x0000004E, "ds_write2_b64", VReg_64>; +def DS_WRITE2ST64_B64 : DS_Store2_Helper <0x0000004F, "ds_write2st64_b64", VReg_64>; -def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "DS_READ2_B32", VReg_64>; -def DS_READ2ST64_B32 : DS_Load2_Helper <0x00000038, "DS_READ2ST64_B32", VReg_64>; -def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "DS_READ2_B64", VReg_128>; -def DS_READ2ST64_B64 : DS_Load2_Helper <0x00000076, "DS_READ2ST64_B64", VReg_128>; +def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "ds_read2_b32", VReg_64>; +def DS_READ2ST64_B32 : DS_Load2_Helper <0x00000038, "ds_read2st64_b32", VReg_64>; +def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "ds_read2_b64", VReg_128>; +def DS_READ2ST64_B64 : DS_Load2_Helper <0x00000076, "ds_read2st64_b64", VReg_128>; //===----------------------------------------------------------------------===// // MUBUF Instructions //===----------------------------------------------------------------------===// -//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>; -//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>; -//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>; -defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>; -//def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>; -//def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>; -//def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>; -//def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>; +//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "buffer_load_format_x", []>; +//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "buffer_load_format_xy", []>; +//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "buffer_load_format_xyz", []>; +defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "buffer_load_format_xyzw", VReg_128>; +//def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "buffer_store_format_x", []>; +//def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "buffer_store_format_xy", []>; +//def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "buffer_store_format_xyz", []>; +//def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "buffer_store_format_xyzw", []>; defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper < - 0x00000008, "BUFFER_LOAD_UBYTE", VReg_32, i32, az_extloadi8_global + 0x00000008, "buffer_load_ubyte", VReg_32, i32, az_extloadi8_global >; defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper < - 0x00000009, "BUFFER_LOAD_SBYTE", VReg_32, i32, sextloadi8_global + 0x00000009, "buffer_load_sbyte", VReg_32, i32, sextloadi8_global >; defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper < - 0x0000000a, "BUFFER_LOAD_USHORT", VReg_32, i32, az_extloadi16_global + 0x0000000a, "buffer_load_ushort", VReg_32, i32, az_extloadi16_global >; defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper < - 0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32, i32, sextloadi16_global + 0x0000000b, "buffer_load_sshort", VReg_32, i32, sextloadi16_global >; defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper < - 0x0000000c, "BUFFER_LOAD_DWORD", VReg_32, i32, global_load + 0x0000000c, "buffer_load_dword", VReg_32, i32, global_load >; defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper < - 0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64, v2i32, global_load + 0x0000000d, "buffer_load_dwordx2", VReg_64, v2i32, global_load >; defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper < - 0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128, v4i32, global_load + 0x0000000e, "buffer_load_dwordx4", VReg_128, v4i32, global_load >; defm BUFFER_STORE_BYTE : MUBUF_Store_Helper < - 0x00000018, "BUFFER_STORE_BYTE", VReg_32, i32, truncstorei8_global + 0x00000018, "buffer_store_byte", VReg_32, i32, truncstorei8_global >; defm BUFFER_STORE_SHORT : MUBUF_Store_Helper < - 0x0000001a, "BUFFER_STORE_SHORT", VReg_32, i32, truncstorei16_global + 0x0000001a, "buffer_store_short", VReg_32, i32, truncstorei16_global >; defm BUFFER_STORE_DWORD : MUBUF_Store_Helper < - 0x0000001c, "BUFFER_STORE_DWORD", VReg_32, i32, global_store + 0x0000001c, "buffer_store_dword", VReg_32, i32, global_store >; defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < - 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64, v2i32, global_store + 0x0000001d, "buffer_store_dwordx2", VReg_64, v2i32, global_store >; defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < - 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128, v4i32, global_store + 0x0000001e, "buffer_store_dwordx4", VReg_128, v4i32, global_store >; -//def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>; +//def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "buffer_atomic_swap", []>; defm BUFFER_ATOMIC_SWAP : MUBUF_Atomic < - 0x00000030, "BUFFER_ATOMIC_SWAP", VReg_32, i32, atomic_swap_global + 0x00000030, "buffer_atomic_swap", VReg_32, i32, atomic_swap_global >; -//def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>; +//def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "buffer_atomic_cmpswap", []>; defm BUFFER_ATOMIC_ADD : MUBUF_Atomic < - 0x00000032, "BUFFER_ATOMIC_ADD", VReg_32, i32, atomic_add_global + 0x00000032, "buffer_atomic_add", VReg_32, i32, atomic_add_global >; defm BUFFER_ATOMIC_SUB : MUBUF_Atomic < - 0x00000033, "BUFFER_ATOMIC_SUB", VReg_32, i32, atomic_sub_global + 0x00000033, "buffer_atomic_sub", VReg_32, i32, atomic_sub_global >; -//def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>; +//def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "buffer_atomic_rsub", []>; defm BUFFER_ATOMIC_SMIN : MUBUF_Atomic < - 0x00000035, "BUFFER_ATOMIC_SMIN", VReg_32, i32, atomic_min_global + 0x00000035, "buffer_atomic_smin", VReg_32, i32, atomic_min_global >; defm BUFFER_ATOMIC_UMIN : MUBUF_Atomic < - 0x00000036, "BUFFER_ATOMIC_UMIN", VReg_32, i32, atomic_umin_global + 0x00000036, "buffer_atomic_umin", VReg_32, i32, atomic_umin_global >; defm BUFFER_ATOMIC_SMAX : MUBUF_Atomic < - 0x00000037, "BUFFER_ATOMIC_SMAX", VReg_32, i32, atomic_max_global + 0x00000037, "buffer_atomic_smax", VReg_32, i32, atomic_max_global >; defm BUFFER_ATOMIC_UMAX : MUBUF_Atomic < - 0x00000038, "BUFFER_ATOMIC_UMAX", VReg_32, i32, atomic_umax_global + 0x00000038, "buffer_atomic_umax", VReg_32, i32, atomic_umax_global >; defm BUFFER_ATOMIC_AND : MUBUF_Atomic < - 0x00000039, "BUFFER_ATOMIC_AND", VReg_32, i32, atomic_and_global + 0x00000039, "buffer_atomic_and", VReg_32, i32, atomic_and_global >; defm BUFFER_ATOMIC_OR : MUBUF_Atomic < - 0x0000003a, "BUFFER_ATOMIC_OR", VReg_32, i32, atomic_or_global + 0x0000003a, "buffer_atomic_or", VReg_32, i32, atomic_or_global >; defm BUFFER_ATOMIC_XOR : MUBUF_Atomic < - 0x0000003b, "BUFFER_ATOMIC_XOR", VReg_32, i32, atomic_xor_global ->; -//def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>; -//def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>; -//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>; -//def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>; -//def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>; -//def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>; -//def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>; -//def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>; -//def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>; -//def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>; -//def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>; -//def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>; -//def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>; -//def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>; -//def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>; -//def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>; -//def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>; -//def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>; -//def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>; -//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>; -//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>; -//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>; -//def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>; -//def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>; + 0x0000003b, "buffer_atomic_xor", VReg_32, i32, atomic_xor_global +>; +//def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "buffer_atomic_inc", []>; +//def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "buffer_atomic_dec", []>; +//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "buffer_atomic_fcmpswap", []>; +//def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "buffer_atomic_fmin", []>; +//def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "buffer_atomic_fmax", []>; +//def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "buffer_atomic_swap_x2", []>; +//def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "buffer_atomic_cmpswap_x2", []>; +//def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "buffer_atomic_add_x2", []>; +//def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "buffer_atomic_sub_x2", []>; +//def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "buffer_atomic_rsub_x2", []>; +//def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "buffer_atomic_smin_x2", []>; +//def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "buffer_atomic_umin_x2", []>; +//def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "buffer_atomic_smax_x2", []>; +//def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "buffer_atomic_umax_x2", []>; +//def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "buffer_atomic_and_x2", []>; +//def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "buffer_atomic_or_x2", []>; +//def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "buffer_atomic_xor_x2", []>; +//def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "buffer_atomic_inc_x2", []>; +//def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "buffer_atomic_dec_x2", []>; +//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "buffer_atomic_fcmpswap_x2", []>; +//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "buffer_atomic_fmin_x2", []>; +//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "buffer_atomic_fmax_x2", []>; +//def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "buffer_wbinvl1_sc", []>; +//def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "buffer_wbinvl1", []>; //===----------------------------------------------------------------------===// // MTBUF Instructions //===----------------------------------------------------------------------===// -//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>; -//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>; -//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>; -defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>; -defm TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>; -defm TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>; -defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>; -defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>; +//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "tbuffer_load_format_x", []>; +//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "tbuffer_load_format_xy", []>; +//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "tbuffer_load_format_xyz", []>; +defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "tbuffer_load_format_xyzw", VReg_128>; +defm TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "tbuffer_store_format_x", VReg_32>; +defm TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "tbuffer_store_format_xy", VReg_64>; +defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "tbuffer_store_format_xyz", VReg_128>; +defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "tbuffer_store_format_xyzw", VReg_128>; //===----------------------------------------------------------------------===// // MIMG Instructions //===----------------------------------------------------------------------===// -defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">; -defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">; -//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>; -//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>; -//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>; -//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>; -//def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>; -//def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>; -//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>; -//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>; -defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">; -//def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>; -//def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>; -//def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>; -//def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>; -//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>; -//def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>; -//def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>; -//def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>; -//def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>; -//def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>; -//def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>; -//def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>; -//def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>; -//def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>; -//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>; -//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>; -//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>; -defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">; -defm IMAGE_SAMPLE_CL : MIMG_Sampler <0x00000021, "IMAGE_SAMPLE_CL">; -defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">; -defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "IMAGE_SAMPLE_D_CL">; -defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">; -defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">; -defm IMAGE_SAMPLE_B_CL : MIMG_Sampler <0x00000026, "IMAGE_SAMPLE_B_CL">; -defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "IMAGE_SAMPLE_LZ">; -defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">; -defm IMAGE_SAMPLE_C_CL : MIMG_Sampler <0x00000029, "IMAGE_SAMPLE_C_CL">; -defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">; -defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "IMAGE_SAMPLE_C_D_CL">; -defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">; -defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">; -defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler <0x0000002e, "IMAGE_SAMPLE_C_B_CL">; -defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "IMAGE_SAMPLE_C_LZ">; -defm IMAGE_SAMPLE_O : MIMG_Sampler <0x00000030, "IMAGE_SAMPLE_O">; -defm IMAGE_SAMPLE_CL_O : MIMG_Sampler <0x00000031, "IMAGE_SAMPLE_CL_O">; -defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "IMAGE_SAMPLE_D_O">; -defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "IMAGE_SAMPLE_D_CL_O">; -defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "IMAGE_SAMPLE_L_O">; -defm IMAGE_SAMPLE_B_O : MIMG_Sampler <0x00000035, "IMAGE_SAMPLE_B_O">; -defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler <0x00000036, "IMAGE_SAMPLE_B_CL_O">; -defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "IMAGE_SAMPLE_LZ_O">; -defm IMAGE_SAMPLE_C_O : MIMG_Sampler <0x00000038, "IMAGE_SAMPLE_C_O">; -defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler <0x00000039, "IMAGE_SAMPLE_C_CL_O">; -defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "IMAGE_SAMPLE_C_D_O">; -defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "IMAGE_SAMPLE_C_D_CL_O">; -defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "IMAGE_SAMPLE_C_L_O">; -defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler <0x0000003d, "IMAGE_SAMPLE_C_B_O">; -defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler <0x0000003e, "IMAGE_SAMPLE_C_B_CL_O">; -defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "IMAGE_SAMPLE_C_LZ_O">; -defm IMAGE_GATHER4 : MIMG_Gather <0x00000040, "IMAGE_GATHER4">; -defm IMAGE_GATHER4_CL : MIMG_Gather <0x00000041, "IMAGE_GATHER4_CL">; -defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "IMAGE_GATHER4_L">; -defm IMAGE_GATHER4_B : MIMG_Gather <0x00000045, "IMAGE_GATHER4_B">; -defm IMAGE_GATHER4_B_CL : MIMG_Gather <0x00000046, "IMAGE_GATHER4_B_CL">; -defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "IMAGE_GATHER4_LZ">; -defm IMAGE_GATHER4_C : MIMG_Gather <0x00000048, "IMAGE_GATHER4_C">; -defm IMAGE_GATHER4_C_CL : MIMG_Gather <0x00000049, "IMAGE_GATHER4_C_CL">; -defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "IMAGE_GATHER4_C_L">; -defm IMAGE_GATHER4_C_B : MIMG_Gather <0x0000004d, "IMAGE_GATHER4_C_B">; -defm IMAGE_GATHER4_C_B_CL : MIMG_Gather <0x0000004e, "IMAGE_GATHER4_C_B_CL">; -defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "IMAGE_GATHER4_C_LZ">; -defm IMAGE_GATHER4_O : MIMG_Gather <0x00000050, "IMAGE_GATHER4_O">; -defm IMAGE_GATHER4_CL_O : MIMG_Gather <0x00000051, "IMAGE_GATHER4_CL_O">; -defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "IMAGE_GATHER4_L_O">; -defm IMAGE_GATHER4_B_O : MIMG_Gather <0x00000055, "IMAGE_GATHER4_B_O">; -defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "IMAGE_GATHER4_B_CL_O">; -defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "IMAGE_GATHER4_LZ_O">; -defm IMAGE_GATHER4_C_O : MIMG_Gather <0x00000058, "IMAGE_GATHER4_C_O">; -defm IMAGE_GATHER4_C_CL_O : MIMG_Gather <0x00000059, "IMAGE_GATHER4_C_CL_O">; -defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "IMAGE_GATHER4_C_L_O">; -defm IMAGE_GATHER4_C_B_O : MIMG_Gather <0x0000005d, "IMAGE_GATHER4_C_B_O">; -defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather <0x0000005e, "IMAGE_GATHER4_C_B_CL_O">; -defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "IMAGE_GATHER4_C_LZ_O">; -defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, "IMAGE_GET_LOD">; -defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "IMAGE_SAMPLE_CD">; -defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "IMAGE_SAMPLE_CD_CL">; -defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "IMAGE_SAMPLE_C_CD">; -defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "IMAGE_SAMPLE_C_CD_CL">; -defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "IMAGE_SAMPLE_CD_O">; -defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "IMAGE_SAMPLE_CD_CL_O">; -defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "IMAGE_SAMPLE_C_CD_O">; -defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "IMAGE_SAMPLE_C_CD_CL_O">; -//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>; -//def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>; +defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load">; +defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip">; +//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"image_load_pck", 0x00000002>; +//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"image_load_pck_sgn", 0x00000003>; +//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"image_load_mip_pck", 0x00000004>; +//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"image_load_mip_pck_sgn", 0x00000005>; +//def IMAGE_STORE : MIMG_NoPattern_ <"image_store", 0x00000008>; +//def IMAGE_STORE_MIP : MIMG_NoPattern_ <"image_store_mip", 0x00000009>; +//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"image_store_pck", 0x0000000a>; +//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"image_store_mip_pck", 0x0000000b>; +defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo">; +//def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"image_atomic_swap", 0x0000000f>; +//def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"image_atomic_cmpswap", 0x00000010>; +//def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"image_atomic_add", 0x00000011>; +//def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"image_atomic_sub", 0x00000012>; +//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; +//def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"image_atomic_smin", 0x00000014>; +//def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"image_atomic_umin", 0x00000015>; +//def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"image_atomic_smax", 0x00000016>; +//def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"image_atomic_umax", 0x00000017>; +//def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"image_atomic_and", 0x00000018>; +//def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"image_atomic_or", 0x00000019>; +//def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"image_atomic_xor", 0x0000001a>; +//def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"image_atomic_inc", 0x0000001b>; +//def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"image_atomic_dec", 0x0000001c>; +//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d>; +//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; +//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; +defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "image_sample">; +defm IMAGE_SAMPLE_CL : MIMG_Sampler <0x00000021, "image_sample_cl">; +defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "image_sample_d">; +defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "image_sample_d_cl">; +defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "image_sample_l">; +defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "image_sample_b">; +defm IMAGE_SAMPLE_B_CL : MIMG_Sampler <0x00000026, "image_sample_b_cl">; +defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "image_sample_lz">; +defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "image_sample_c">; +defm IMAGE_SAMPLE_C_CL : MIMG_Sampler <0x00000029, "image_sample_c_cl">; +defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "image_sample_c_d">; +defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "image_sample_c_d_cl">; +defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "image_sample_c_l">; +defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "image_sample_c_b">; +defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler <0x0000002e, "image_sample_c_b_cl">; +defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "image_sample_c_lz">; +defm IMAGE_SAMPLE_O : MIMG_Sampler <0x00000030, "image_sample_o">; +defm IMAGE_SAMPLE_CL_O : MIMG_Sampler <0x00000031, "image_sample_cl_o">; +defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "image_sample_d_o">; +defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "image_sample_d_cl_o">; +defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "image_sample_l_o">; +defm IMAGE_SAMPLE_B_O : MIMG_Sampler <0x00000035, "image_sample_b_o">; +defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler <0x00000036, "image_sample_b_cl_o">; +defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "image_sample_lz_o">; +defm IMAGE_SAMPLE_C_O : MIMG_Sampler <0x00000038, "image_sample_c_o">; +defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler <0x00000039, "image_sample_c_cl_o">; +defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "image_sample_c_d_o">; +defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "image_sample_c_d_cl_o">; +defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "image_sample_c_l_o">; +defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler <0x0000003d, "image_sample_c_b_o">; +defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler <0x0000003e, "image_sample_c_b_cl_o">; +defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "image_sample_c_lz_o">; +defm IMAGE_GATHER4 : MIMG_Gather <0x00000040, "image_gather4">; +defm IMAGE_GATHER4_CL : MIMG_Gather <0x00000041, "image_gather4_cl">; +defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "image_gather4_l">; +defm IMAGE_GATHER4_B : MIMG_Gather <0x00000045, "image_gather4_b">; +defm IMAGE_GATHER4_B_CL : MIMG_Gather <0x00000046, "image_gather4_b_cl">; +defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "image_gather4_lz">; +defm IMAGE_GATHER4_C : MIMG_Gather <0x00000048, "image_gather4_c">; +defm IMAGE_GATHER4_C_CL : MIMG_Gather <0x00000049, "image_gather4_c_cl">; +defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "image_gather4_c_l">; +defm IMAGE_GATHER4_C_B : MIMG_Gather <0x0000004d, "image_gather4_c_b">; +defm IMAGE_GATHER4_C_B_CL : MIMG_Gather <0x0000004e, "image_gather4_c_b_cl">; +defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "image_gather4_c_lz">; +defm IMAGE_GATHER4_O : MIMG_Gather <0x00000050, "image_gather4_o">; +defm IMAGE_GATHER4_CL_O : MIMG_Gather <0x00000051, "image_gather4_cl_o">; +defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "image_gather4_l_o">; +defm IMAGE_GATHER4_B_O : MIMG_Gather <0x00000055, "image_gather4_b_o">; +defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "image_gather4_b_cl_o">; +defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "image_gather4_lz_o">; +defm IMAGE_GATHER4_C_O : MIMG_Gather <0x00000058, "image_gather4_c_o">; +defm IMAGE_GATHER4_C_CL_O : MIMG_Gather <0x00000059, "image_gather4_c_cl_o">; +defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "image_gather4_c_l_o">; +defm IMAGE_GATHER4_C_B_O : MIMG_Gather <0x0000005d, "image_gather4_c_b_o">; +defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather <0x0000005e, "image_gather4_c_b_cl_o">; +defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "image_gather4_c_lz_o">; +defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, "image_get_lod">; +defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "image_sample_cd">; +defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "image_sample_cd_cl">; +defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "image_sample_c_cd">; +defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "image_sample_c_cd_cl">; +defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "image_sample_cd_o">; +defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "image_sample_cd_cl_o">; +defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "image_sample_c_cd_o">; +defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "image_sample_c_cd_cl_o">; +//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>; +//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>; //===----------------------------------------------------------------------===// // Flat Instructions //===----------------------------------------------------------------------===// let Predicates = [HasFlatAddressSpace] in { -def FLAT_LOAD_UBYTE : FLAT_Load_Helper <0x00000008, "FLAT_LOAD_UBYTE", VReg_32>; -def FLAT_LOAD_SBYTE : FLAT_Load_Helper <0x00000009, "FLAT_LOAD_SBYTE", VReg_32>; -def FLAT_LOAD_USHORT : FLAT_Load_Helper <0x0000000a, "FLAT_LOAD_USHORT", VReg_32>; -def FLAT_LOAD_SSHORT : FLAT_Load_Helper <0x0000000b, "FLAT_LOAD_SSHORT", VReg_32>; -def FLAT_LOAD_DWORD : FLAT_Load_Helper <0x0000000c, "FLAT_LOAD_DWORD", VReg_32>; -def FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <0x0000000d, "FLAT_LOAD_DWORDX2", VReg_64>; -def FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <0x0000000e, "FLAT_LOAD_DWORDX4", VReg_128>; -def FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <0x00000010, "FLAT_LOAD_DWORDX3", VReg_96>; +def FLAT_LOAD_UBYTE : FLAT_Load_Helper <0x00000008, "flat_load_ubyte", VReg_32>; +def FLAT_LOAD_SBYTE : FLAT_Load_Helper <0x00000009, "flat_load_sbyte", VReg_32>; +def FLAT_LOAD_USHORT : FLAT_Load_Helper <0x0000000a, "flat_load_ushort", VReg_32>; +def FLAT_LOAD_SSHORT : FLAT_Load_Helper <0x0000000b, "flat_load_sshort", VReg_32>; +def FLAT_LOAD_DWORD : FLAT_Load_Helper <0x0000000c, "flat_load_dword", VReg_32>; +def FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <0x0000000d, "flat_load_dwordx2", VReg_64>; +def FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <0x0000000e, "flat_load_dwordx4", VReg_128>; +def FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <0x00000010, "flat_load_dwordx3", VReg_96>; def FLAT_STORE_BYTE : FLAT_Store_Helper < - 0x00000018, "FLAT_STORE_BYTE", VReg_32 + 0x00000018, "flat_store_byte", VReg_32 >; def FLAT_STORE_SHORT : FLAT_Store_Helper < - 0x0000001a, "FLAT_STORE_SHORT", VReg_32 + 0x0000001a, "flat_store_short", VReg_32 >; def FLAT_STORE_DWORD : FLAT_Store_Helper < - 0x0000001c, "FLAT_STORE_DWORD", VReg_32 + 0x0000001c, "flat_store_dword", VReg_32 >; def FLAT_STORE_DWORDX2 : FLAT_Store_Helper < - 0x0000001d, "FLAT_STORE_DWORDX2", VReg_64 + 0x0000001d, "flat_store_dwordx2", VReg_64 >; def FLAT_STORE_DWORDX4 : FLAT_Store_Helper < - 0x0000001e, "FLAT_STORE_DWORDX4", VReg_128 + 0x0000001e, "flat_store_dwordx4", VReg_128 >; def FLAT_STORE_DWORDX3 : FLAT_Store_Helper < - 0x0000001e, "FLAT_STORE_DWORDX3", VReg_96 ->; - -//def FLAT_ATOMIC_SWAP : FLAT_ <0x00000030, "FLAT_ATOMIC_SWAP", []>; -//def FLAT_ATOMIC_CMPSWAP : FLAT_ <0x00000031, "FLAT_ATOMIC_CMPSWAP", []>; -//def FLAT_ATOMIC_ADD : FLAT_ <0x00000032, "FLAT_ATOMIC_ADD", []>; -//def FLAT_ATOMIC_SUB : FLAT_ <0x00000033, "FLAT_ATOMIC_SUB", []>; -//def FLAT_ATOMIC_RSUB : FLAT_ <0x00000034, "FLAT_ATOMIC_RSUB", []>; -//def FLAT_ATOMIC_SMIN : FLAT_ <0x00000035, "FLAT_ATOMIC_SMIN", []>; -//def FLAT_ATOMIC_UMIN : FLAT_ <0x00000036, "FLAT_ATOMIC_UMIN", []>; -//def FLAT_ATOMIC_SMAX : FLAT_ <0x00000037, "FLAT_ATOMIC_SMAX", []>; -//def FLAT_ATOMIC_UMAX : FLAT_ <0x00000038, "FLAT_ATOMIC_UMAX", []>; -//def FLAT_ATOMIC_AND : FLAT_ <0x00000039, "FLAT_ATOMIC_AND", []>; -//def FLAT_ATOMIC_OR : FLAT_ <0x0000003a, "FLAT_ATOMIC_OR", []>; -//def FLAT_ATOMIC_XOR : FLAT_ <0x0000003b, "FLAT_ATOMIC_XOR", []>; -//def FLAT_ATOMIC_INC : FLAT_ <0x0000003c, "FLAT_ATOMIC_INC", []>; -//def FLAT_ATOMIC_DEC : FLAT_ <0x0000003d, "FLAT_ATOMIC_DEC", []>; -//def FLAT_ATOMIC_FCMPSWAP : FLAT_ <0x0000003e, "FLAT_ATOMIC_FCMPSWAP", []>; -//def FLAT_ATOMIC_FMIN : FLAT_ <0x0000003f, "FLAT_ATOMIC_FMIN", []>; -//def FLAT_ATOMIC_FMAX : FLAT_ <0x00000040, "FLAT_ATOMIC_FMAX", []>; -//def FLAT_ATOMIC_SWAP_X2 : FLAT_X2 <0x00000050, "FLAT_ATOMIC_SWAP_X2", []>; -//def FLAT_ATOMIC_CMPSWAP_X2 : FLAT_X2 <0x00000051, "FLAT_ATOMIC_CMPSWAP_X2", []>; -//def FLAT_ATOMIC_ADD_X2 : FLAT_X2 <0x00000052, "FLAT_ATOMIC_ADD_X2", []>; -//def FLAT_ATOMIC_SUB_X2 : FLAT_X2 <0x00000053, "FLAT_ATOMIC_SUB_X2", []>; -//def FLAT_ATOMIC_RSUB_X2 : FLAT_X2 <0x00000054, "FLAT_ATOMIC_RSUB_X2", []>; -//def FLAT_ATOMIC_SMIN_X2 : FLAT_X2 <0x00000055, "FLAT_ATOMIC_SMIN_X2", []>; -//def FLAT_ATOMIC_UMIN_X2 : FLAT_X2 <0x00000056, "FLAT_ATOMIC_UMIN_X2", []>; -//def FLAT_ATOMIC_SMAX_X2 : FLAT_X2 <0x00000057, "FLAT_ATOMIC_SMAX_X2", []>; -//def FLAT_ATOMIC_UMAX_X2 : FLAT_X2 <0x00000058, "FLAT_ATOMIC_UMAX_X2", []>; -//def FLAT_ATOMIC_AND_X2 : FLAT_X2 <0x00000059, "FLAT_ATOMIC_AND_X2", []>; -//def FLAT_ATOMIC_OR_X2 : FLAT_X2 <0x0000005a, "FLAT_ATOMIC_OR_X2", []>; -//def FLAT_ATOMIC_XOR_X2 : FLAT_X2 <0x0000005b, "FLAT_ATOMIC_XOR_X2", []>; -//def FLAT_ATOMIC_INC_X2 : FLAT_X2 <0x0000005c, "FLAT_ATOMIC_INC_X2", []>; -//def FLAT_ATOMIC_DEC_X2 : FLAT_X2 <0x0000005d, "FLAT_ATOMIC_DEC_X2", []>; -//def FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_X2 <0x0000005e, "FLAT_ATOMIC_FCMPSWAP_X2", []>; -//def FLAT_ATOMIC_FMIN_X2 : FLAT_X2 <0x0000005f, "FLAT_ATOMIC_FMIN_X2", []>; -//def FLAT_ATOMIC_FMAX_X2 : FLAT_X2 <0x00000060, "FLAT_ATOMIC_FMAX_X2", []>; + 0x0000001e, "flat_store_dwordx3", VReg_96 +>; + +//def FLAT_ATOMIC_SWAP : FLAT_ <0x00000030, "flat_atomic_swap", []>; +//def FLAT_ATOMIC_CMPSWAP : FLAT_ <0x00000031, "flat_atomic_cmpswap", []>; +//def FLAT_ATOMIC_ADD : FLAT_ <0x00000032, "flat_atomic_add", []>; +//def FLAT_ATOMIC_SUB : FLAT_ <0x00000033, "flat_atomic_sub", []>; +//def FLAT_ATOMIC_RSUB : FLAT_ <0x00000034, "flat_atomic_rsub", []>; +//def FLAT_ATOMIC_SMIN : FLAT_ <0x00000035, "flat_atomic_smin", []>; +//def FLAT_ATOMIC_UMIN : FLAT_ <0x00000036, "flat_atomic_umin", []>; +//def FLAT_ATOMIC_SMAX : FLAT_ <0x00000037, "flat_atomic_smax", []>; +//def FLAT_ATOMIC_UMAX : FLAT_ <0x00000038, "flat_atomic_umax", []>; +//def FLAT_ATOMIC_AND : FLAT_ <0x00000039, "flat_atomic_and", []>; +//def FLAT_ATOMIC_OR : FLAT_ <0x0000003a, "flat_atomic_or", []>; +//def FLAT_ATOMIC_XOR : FLAT_ <0x0000003b, "flat_atomic_xor", []>; +//def FLAT_ATOMIC_INC : FLAT_ <0x0000003c, "flat_atomic_inc", []>; +//def FLAT_ATOMIC_DEC : FLAT_ <0x0000003d, "flat_atomic_dec", []>; +//def FLAT_ATOMIC_FCMPSWAP : FLAT_ <0x0000003e, "flat_atomic_fcmpswap", []>; +//def FLAT_ATOMIC_FMIN : FLAT_ <0x0000003f, "flat_atomic_fmin", []>; +//def FLAT_ATOMIC_FMAX : FLAT_ <0x00000040, "flat_atomic_fmax", []>; +//def FLAT_ATOMIC_SWAP_X2 : FLAT_X2 <0x00000050, "flat_atomic_swap_x2", []>; +//def FLAT_ATOMIC_CMPSWAP_X2 : FLAT_X2 <0x00000051, "flat_atomic_cmpswap_x2", []>; +//def FLAT_ATOMIC_ADD_X2 : FLAT_X2 <0x00000052, "flat_atomic_add_x2", []>; +//def FLAT_ATOMIC_SUB_X2 : FLAT_X2 <0x00000053, "flat_atomic_sub_x2", []>; +//def FLAT_ATOMIC_RSUB_X2 : FLAT_X2 <0x00000054, "flat_atomic_rsub_x2", []>; +//def FLAT_ATOMIC_SMIN_X2 : FLAT_X2 <0x00000055, "flat_atomic_smin_x2", []>; +//def FLAT_ATOMIC_UMIN_X2 : FLAT_X2 <0x00000056, "flat_atomic_umin_x2", []>; +//def FLAT_ATOMIC_SMAX_X2 : FLAT_X2 <0x00000057, "flat_atomic_smax_x2", []>; +//def FLAT_ATOMIC_UMAX_X2 : FLAT_X2 <0x00000058, "flat_atomic_umax_x2", []>; +//def FLAT_ATOMIC_AND_X2 : FLAT_X2 <0x00000059, "flat_atomic_and_x2", []>; +//def FLAT_ATOMIC_OR_X2 : FLAT_X2 <0x0000005a, "flat_atomic_or_x2", []>; +//def FLAT_ATOMIC_XOR_X2 : FLAT_X2 <0x0000005b, "flat_atomic_xor_x2", []>; +//def FLAT_ATOMIC_INC_X2 : FLAT_X2 <0x0000005c, "flat_atomic_inc_x2", []>; +//def FLAT_ATOMIC_DEC_X2 : FLAT_X2 <0x0000005d, "flat_atomic_dec_x2", []>; +//def FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_X2 <0x0000005e, "flat_atomic_fcmpswap_x2", []>; +//def FLAT_ATOMIC_FMIN_X2 : FLAT_X2 <0x0000005f, "flat_atomic_fmin_x2", []>; +//def FLAT_ATOMIC_FMAX_X2 : FLAT_X2 <0x00000060, "flat_atomic_fmax_x2", []>; } // End HasFlatAddressSpace predicate //===----------------------------------------------------------------------===// // VOP1 Instructions //===----------------------------------------------------------------------===// -//def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; +//def V_NOP : VOP1_ <0x00000000, "v_nop", []>; let isMoveImm = 1 in { -defm V_MOV_B32 : VOP1Inst , "V_MOV_B32", VOP_I32_I32>; +defm V_MOV_B32 : VOP1Inst , "v_mov_b32", VOP_I32_I32>; } // End isMoveImm = 1 let Uses = [EXEC] in { @@ -1156,139 +1156,139 @@ def V_READFIRSTLANE_B32 : VOP1 < 0x00000002, (outs SReg_32:$vdst), (ins VReg_32:$src0), - "V_READFIRSTLANE_B32 $vdst, $src0", + "v_readfirstlane_b32 $vdst, $src0", [] >; } -defm V_CVT_I32_F64 : VOP1Inst , "V_CVT_I32_F64", +defm V_CVT_I32_F64 : VOP1Inst , "v_cvt_i32_f64", VOP_I32_F64, fp_to_sint >; -defm V_CVT_F64_I32 : VOP1Inst , "V_CVT_F64_I32", +defm V_CVT_F64_I32 : VOP1Inst , "v_cvt_f64_i32", VOP_F64_I32, sint_to_fp >; -defm V_CVT_F32_I32 : VOP1Inst , "V_CVT_F32_I32", +defm V_CVT_F32_I32 : VOP1Inst , "v_cvt_f32_i32", VOP_F32_I32, sint_to_fp >; -defm V_CVT_F32_U32 : VOP1Inst , "V_CVT_F32_U32", +defm V_CVT_F32_U32 : VOP1Inst , "v_cvt_f32_u32", VOP_F32_I32, uint_to_fp >; -defm V_CVT_U32_F32 : VOP1Inst , "V_CVT_U32_F32", +defm V_CVT_U32_F32 : VOP1Inst , "v_cvt_u32_f32", VOP_I32_F32, fp_to_uint >; -defm V_CVT_I32_F32 : VOP1Inst , "V_CVT_I32_F32", +defm V_CVT_I32_F32 : VOP1Inst , "v_cvt_i32_f32", VOP_I32_F32, fp_to_sint >; -defm V_MOV_FED_B32 : VOP1Inst , "V_MOV_FED_B32", VOP_I32_I32>; -defm V_CVT_F16_F32 : VOP1Inst , "V_CVT_F16_F32", +defm V_MOV_FED_B32 : VOP1Inst , "v_mov_fed_b32", VOP_I32_I32>; +defm V_CVT_F16_F32 : VOP1Inst , "v_cvt_f16_f32", VOP_I32_F32, fp_to_f16 >; -defm V_CVT_F32_F16 : VOP1Inst , "V_CVT_F32_F16", +defm V_CVT_F32_F16 : VOP1Inst , "v_cvt_f32_f16", VOP_F32_I32, f16_to_fp >; -//defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; -//defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; -//defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; -defm V_CVT_F32_F64 : VOP1Inst , "V_CVT_F32_F64", +//defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "v_cvt_rpi_i32_f32", []>; +//defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "v_cvt_flr_i32_f32", []>; +//defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "v_cvt_off_f32_i4", []>; +defm V_CVT_F32_F64 : VOP1Inst , "v_cvt_f32_f64", VOP_F32_F64, fround >; -defm V_CVT_F64_F32 : VOP1Inst , "V_CVT_F64_F32", +defm V_CVT_F64_F32 : VOP1Inst , "v_cvt_f64_f32", VOP_F64_F32, fextend >; -defm V_CVT_F32_UBYTE0 : VOP1Inst , "V_CVT_F32_UBYTE0", +defm V_CVT_F32_UBYTE0 : VOP1Inst , "v_cvt_f32_ubyte0", VOP_F32_I32, AMDGPUcvt_f32_ubyte0 >; -defm V_CVT_F32_UBYTE1 : VOP1Inst , "V_CVT_F32_UBYTE1", +defm V_CVT_F32_UBYTE1 : VOP1Inst , "v_cvt_f32_ubyte1", VOP_F32_I32, AMDGPUcvt_f32_ubyte1 >; -defm V_CVT_F32_UBYTE2 : VOP1Inst , "V_CVT_F32_UBYTE2", +defm V_CVT_F32_UBYTE2 : VOP1Inst , "v_cvt_f32_ubyte2", VOP_F32_I32, AMDGPUcvt_f32_ubyte2 >; -defm V_CVT_F32_UBYTE3 : VOP1Inst , "V_CVT_F32_UBYTE3", +defm V_CVT_F32_UBYTE3 : VOP1Inst , "v_cvt_f32_ubyte3", VOP_F32_I32, AMDGPUcvt_f32_ubyte3 >; -defm V_CVT_U32_F64 : VOP1Inst , "V_CVT_U32_F64", +defm V_CVT_U32_F64 : VOP1Inst , "v_cvt_u32_f64", VOP_I32_F64, fp_to_uint >; -defm V_CVT_F64_U32 : VOP1Inst , "V_CVT_F64_U32", +defm V_CVT_F64_U32 : VOP1Inst , "v_cvt_f64_u32", VOP_F64_I32, uint_to_fp >; -defm V_FRACT_F32 : VOP1Inst , "V_FRACT_F32", +defm V_FRACT_F32 : VOP1Inst , "v_fract_f32", VOP_F32_F32, AMDGPUfract >; -defm V_TRUNC_F32 : VOP1Inst , "V_TRUNC_F32", +defm V_TRUNC_F32 : VOP1Inst , "v_trunc_f32", VOP_F32_F32, ftrunc >; -defm V_CEIL_F32 : VOP1Inst , "V_CEIL_F32", +defm V_CEIL_F32 : VOP1Inst , "v_ceil_f32", VOP_F32_F32, fceil >; -defm V_RNDNE_F32 : VOP1Inst , "V_RNDNE_F32", +defm V_RNDNE_F32 : VOP1Inst , "v_rndne_f32", VOP_F32_F32, frint >; -defm V_FLOOR_F32 : VOP1Inst , "V_FLOOR_F32", +defm V_FLOOR_F32 : VOP1Inst , "v_floor_f32", VOP_F32_F32, ffloor >; -defm V_EXP_F32 : VOP1Inst , "V_EXP_F32", +defm V_EXP_F32 : VOP1Inst , "v_exp_f32", VOP_F32_F32, fexp2 >; -defm V_LOG_CLAMP_F32 : VOP1Inst , "V_LOG_CLAMP_F32", VOP_F32_F32>; -defm V_LOG_F32 : VOP1Inst , "V_LOG_F32", +defm V_LOG_CLAMP_F32 : VOP1Inst , "v_log_clamp_f32", VOP_F32_F32>; +defm V_LOG_F32 : VOP1Inst , "v_log_f32", VOP_F32_F32, flog2 >; -defm V_RCP_CLAMP_F32 : VOP1Inst , "V_RCP_CLAMP_F32", VOP_F32_F32>; -defm V_RCP_LEGACY_F32 : VOP1Inst , "V_RCP_LEGACY_F32", VOP_F32_F32>; -defm V_RCP_F32 : VOP1Inst , "V_RCP_F32", +defm V_RCP_CLAMP_F32 : VOP1Inst , "v_rcp_clamp_f32", VOP_F32_F32>; +defm V_RCP_LEGACY_F32 : VOP1Inst , "v_rcp_legacy_f32", VOP_F32_F32>; +defm V_RCP_F32 : VOP1Inst , "v_rcp_f32", VOP_F32_F32, AMDGPUrcp >; -defm V_RCP_IFLAG_F32 : VOP1Inst , "V_RCP_IFLAG_F32", VOP_F32_F32>; -defm V_RSQ_CLAMP_F32 : VOP1Inst , "V_RSQ_CLAMP_F32", +defm V_RCP_IFLAG_F32 : VOP1Inst , "v_rcp_iflag_f32", VOP_F32_F32>; +defm V_RSQ_CLAMP_F32 : VOP1Inst , "v_rsq_clamp_f32", VOP_F32_F32, AMDGPUrsq_clamped >; -defm V_RSQ_LEGACY_F32 : VOP1Inst , "V_RSQ_LEGACY_F32", +defm V_RSQ_LEGACY_F32 : VOP1Inst , "v_rsq_legacy_f32", VOP_F32_F32, AMDGPUrsq_legacy >; -defm V_RSQ_F32 : VOP1Inst , "V_RSQ_F32", +defm V_RSQ_F32 : VOP1Inst , "v_rsq_f32", VOP_F32_F32, AMDGPUrsq >; -defm V_RCP_F64 : VOP1Inst , "V_RCP_F64", +defm V_RCP_F64 : VOP1Inst , "v_rcp_f64", VOP_F64_F64, AMDGPUrcp >; -defm V_RCP_CLAMP_F64 : VOP1Inst , "V_RCP_CLAMP_F64", VOP_F64_F64>; -defm V_RSQ_F64 : VOP1Inst , "V_RSQ_F64", +defm V_RCP_CLAMP_F64 : VOP1Inst , "v_rcp_clamp_f64", VOP_F64_F64>; +defm V_RSQ_F64 : VOP1Inst , "v_rsq_f64", VOP_F64_F64, AMDGPUrsq >; -defm V_RSQ_CLAMP_F64 : VOP1Inst , "V_RSQ_CLAMP_F64", +defm V_RSQ_CLAMP_F64 : VOP1Inst , "v_rsq_clamp_f64", VOP_F64_F64, AMDGPUrsq_clamped >; -defm V_SQRT_F32 : VOP1Inst , "V_SQRT_F32", +defm V_SQRT_F32 : VOP1Inst , "v_sqrt_f32", VOP_F32_F32, fsqrt >; -defm V_SQRT_F64 : VOP1Inst , "V_SQRT_F64", +defm V_SQRT_F64 : VOP1Inst , "v_sqrt_f64", VOP_F64_F64, fsqrt >; -defm V_SIN_F32 : VOP1Inst , "V_SIN_F32", +defm V_SIN_F32 : VOP1Inst , "v_sin_f32", VOP_F32_F32, AMDGPUsin >; -defm V_COS_F32 : VOP1Inst , "V_COS_F32", +defm V_COS_F32 : VOP1Inst , "v_cos_f32", VOP_F32_F32, AMDGPUcos >; -defm V_NOT_B32 : VOP1Inst , "V_NOT_B32", VOP_I32_I32>; -defm V_BFREV_B32 : VOP1Inst , "V_BFREV_B32", VOP_I32_I32>; -defm V_FFBH_U32 : VOP1Inst , "V_FFBH_U32", VOP_I32_I32>; -defm V_FFBL_B32 : VOP1Inst , "V_FFBL_B32", VOP_I32_I32>; -defm V_FFBH_I32 : VOP1Inst , "V_FFBH_I32", VOP_I32_I32>; -//defm V_FREXP_EXP_I32_F64 : VOPInst <0x0000003c, "V_FREXP_EXP_I32_F64", VOP_I32_F32>; -defm V_FREXP_MANT_F64 : VOP1Inst , "V_FREXP_MANT_F64", VOP_F64_F64>; -defm V_FRACT_F64 : VOP1Inst , "V_FRACT_F64", VOP_F64_F64>; -//defm V_FREXP_EXP_I32_F32 : VOPInst <0x0000003f, "V_FREXP_EXP_I32_F32", VOP_I32_F32>; -defm V_FREXP_MANT_F32 : VOP1Inst , "V_FREXP_MANT_F32", VOP_F32_F32>; -//def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; -defm V_MOVRELD_B32 : VOP1Inst , "V_MOVRELD_B32", VOP_I32_I32>; -defm V_MOVRELS_B32 : VOP1Inst , "V_MOVRELS_B32", VOP_I32_I32>; -defm V_MOVRELSD_B32 : VOP1Inst , "V_MOVRELSD_B32", VOP_I32_I32>; +defm V_NOT_B32 : VOP1Inst , "v_not_b32", VOP_I32_I32>; +defm V_BFREV_B32 : VOP1Inst , "v_bfrev_b32", VOP_I32_I32>; +defm V_FFBH_U32 : VOP1Inst , "v_ffbh_u32", VOP_I32_I32>; +defm V_FFBL_B32 : VOP1Inst , "v_ffbl_b32", VOP_I32_I32>; +defm V_FFBH_I32 : VOP1Inst , "v_ffbh_i32", VOP_I32_I32>; +//defm V_FREXP_EXP_I32_F64 : VOPInst <0x0000003c, "v_frexp_exp_i32_f64", VOP_I32_F32>; +defm V_FREXP_MANT_F64 : VOP1Inst , "v_frexp_mant_f64", VOP_F64_F64>; +defm V_FRACT_F64 : VOP1Inst , "v_fract_f64", VOP_F64_F64>; +//defm V_FREXP_EXP_I32_F32 : VOPInst <0x0000003f, "v_frexp_exp_i32_f32", VOP_I32_F32>; +defm V_FREXP_MANT_F32 : VOP1Inst , "v_frexp_mant_f32", VOP_F32_F32>; +//def V_CLREXCP : VOP1_ <0x00000041, "v_clrexcp", []>; +defm V_MOVRELD_B32 : VOP1Inst , "v_movreld_b32", VOP_I32_I32>; +defm V_MOVRELS_B32 : VOP1Inst , "v_movrels_b32", VOP_I32_I32>; +defm V_MOVRELSD_B32 : VOP1Inst , "v_movrelsd_b32", VOP_I32_I32>; //===----------------------------------------------------------------------===// @@ -1299,7 +1299,7 @@ def V_INTERP_P1_F32 : VINTRP < 0x00000000, (outs VReg_32:$dst), (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), - "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]", + "v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [$m0]", []> { let DisableEncoding = "$m0"; } @@ -1308,7 +1308,7 @@ def V_INTERP_P2_F32 : VINTRP < 0x00000001, (outs VReg_32:$dst), (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), - "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]", + "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]", []> { let Constraints = "$src0 = $dst"; @@ -1320,7 +1320,7 @@ def V_INTERP_MOV_F32 : VINTRP < 0x00000002, (outs VReg_32:$dst), (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), - "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]", + "v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [$m0]", []> { let DisableEncoding = "$m0"; } @@ -1331,7 +1331,7 @@ def V_INTERP_MOV_F32 : VINTRP < def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc), - "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]", + "v_cndmask_b32_e32 $dst, $src0, $src1, [$vcc]", [] >{ let DisableEncoding = "$vcc"; @@ -1339,7 +1339,7 @@ def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst), def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst), (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2), - "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2", + "v_cndmask_b32_e64 $dst, $src0, $src1, $src2", [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))] > { let src0_modifiers = 0; @@ -1351,7 +1351,7 @@ def V_READLANE_B32 : VOP2 < 0x00000001, (outs SReg_32:$vdst), (ins VReg_32:$src0, SSrc_32:$vsrc1), - "V_READLANE_B32 $vdst, $src0, $vsrc1", + "v_readlane_b32 $vdst, $src0, $vsrc1", [] >; @@ -1359,287 +1359,287 @@ def V_WRITELANE_B32 : VOP2 < 0x00000002, (outs VReg_32:$vdst), (ins SReg_32:$src0, SSrc_32:$vsrc1), - "V_WRITELANE_B32 $vdst, $src0, $vsrc1", + "v_writelane_b32 $vdst, $src0, $vsrc1", [] >; let isCommutable = 1 in { -defm V_ADD_F32 : VOP2Inst , "V_ADD_F32", +defm V_ADD_F32 : VOP2Inst , "v_add_f32", VOP_F32_F32_F32, fadd >; -defm V_SUB_F32 : VOP2Inst , "V_SUB_F32", VOP_F32_F32_F32, fsub>; -defm V_SUBREV_F32 : VOP2Inst , "V_SUBREV_F32", - VOP_F32_F32_F32, null_frag, "V_SUB_F32" +defm V_SUB_F32 : VOP2Inst , "v_sub_f32", VOP_F32_F32_F32, fsub>; +defm V_SUBREV_F32 : VOP2Inst , "v_subrev_f32", + VOP_F32_F32_F32, null_frag, "v_sub_f32" >; } // End isCommutable = 1 -defm V_MAC_LEGACY_F32 : VOP2Inst , "V_MAC_LEGACY_F32", +defm V_MAC_LEGACY_F32 : VOP2Inst , "v_mac_legacy_f32", VOP_F32_F32_F32 >; let isCommutable = 1 in { -defm V_MUL_LEGACY_F32 : VOP2Inst , "V_MUL_LEGACY_F32", +defm V_MUL_LEGACY_F32 : VOP2Inst , "v_mul_legacy_f32", VOP_F32_F32_F32, int_AMDGPU_mul >; -defm V_MUL_F32 : VOP2Inst , "V_MUL_F32", +defm V_MUL_F32 : VOP2Inst , "v_mul_f32", VOP_F32_F32_F32, fmul >; -defm V_MUL_I32_I24 : VOP2Inst , "V_MUL_I32_I24", +defm V_MUL_I32_I24 : VOP2Inst , "v_mul_i32_i24", VOP_I32_I32_I32, AMDGPUmul_i24 >; -//defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>; -defm V_MUL_U32_U24 : VOP2Inst , "V_MUL_U32_U24", +//defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "v_mul_hi_i32_i24", []>; +defm V_MUL_U32_U24 : VOP2Inst , "v_mul_u32_u24", VOP_I32_I32_I32, AMDGPUmul_u24 >; -//defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>; +//defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "v_mul_hi_u32_u24", []>; -defm V_MIN_LEGACY_F32 : VOP2Inst , "V_MIN_LEGACY_F32", +defm V_MIN_LEGACY_F32 : VOP2Inst , "v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin >; -defm V_MAX_LEGACY_F32 : VOP2Inst , "V_MAX_LEGACY_F32", +defm V_MAX_LEGACY_F32 : VOP2Inst , "v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax >; -defm V_MIN_F32 : VOP2Inst , "V_MIN_F32", VOP_F32_F32_F32, fminnum>; -defm V_MAX_F32 : VOP2Inst , "V_MAX_F32", VOP_F32_F32_F32, fmaxnum>; -defm V_MIN_I32 : VOP2Inst , "V_MIN_I32", VOP_I32_I32_I32, AMDGPUsmin>; -defm V_MAX_I32 : VOP2Inst , "V_MAX_I32", VOP_I32_I32_I32, AMDGPUsmax>; -defm V_MIN_U32 : VOP2Inst , "V_MIN_U32", VOP_I32_I32_I32, AMDGPUumin>; -defm V_MAX_U32 : VOP2Inst , "V_MAX_U32", VOP_I32_I32_I32, AMDGPUumax>; +defm V_MIN_F32 : VOP2Inst , "v_min_f32", VOP_F32_F32_F32, fminnum>; +defm V_MAX_F32 : VOP2Inst , "v_max_f32", VOP_F32_F32_F32, fmaxnum>; +defm V_MIN_I32 : VOP2Inst , "v_min_i32", VOP_I32_I32_I32, AMDGPUsmin>; +defm V_MAX_I32 : VOP2Inst , "v_max_i32", VOP_I32_I32_I32, AMDGPUsmax>; +defm V_MIN_U32 : VOP2Inst , "v_min_u32", VOP_I32_I32_I32, AMDGPUumin>; +defm V_MAX_U32 : VOP2Inst , "v_max_u32", VOP_I32_I32_I32, AMDGPUumax>; -defm V_LSHR_B32 : VOP2Inst , "V_LSHR_B32", VOP_I32_I32_I32, srl>; +defm V_LSHR_B32 : VOP2Inst , "v_lshr_b32", VOP_I32_I32_I32, srl>; defm V_LSHRREV_B32 : VOP2Inst < - vop2<0x16>, "V_LSHRREV_B32", VOP_I32_I32_I32, null_frag, "V_LSHR_B32" + vop2<0x16>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag, "v_lshr_b32" >; -defm V_ASHR_I32 : VOP2Inst , "V_ASHR_I32", +defm V_ASHR_I32 : VOP2Inst , "v_ashr_i32", VOP_I32_I32_I32, sra >; defm V_ASHRREV_I32 : VOP2Inst < - vop2<0x18>, "V_ASHRREV_I32", VOP_I32_I32_I32, null_frag, "V_ASHR_I32" + vop2<0x18>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag, "v_ashr_i32" >; let hasPostISelHook = 1 in { -defm V_LSHL_B32 : VOP2Inst , "V_LSHL_B32", VOP_I32_I32_I32, shl>; +defm V_LSHL_B32 : VOP2Inst , "v_lshl_b32", VOP_I32_I32_I32, shl>; } defm V_LSHLREV_B32 : VOP2Inst < - vop2<0x1a>, "V_LSHLREV_B32", VOP_I32_I32_I32, null_frag, "V_LSHL_B32" + vop2<0x1a>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag, "v_lshl_b32" >; -defm V_AND_B32 : VOP2Inst , "V_AND_B32", +defm V_AND_B32 : VOP2Inst , "v_and_b32", VOP_I32_I32_I32, and>; -defm V_OR_B32 : VOP2Inst , "V_OR_B32", +defm V_OR_B32 : VOP2Inst , "v_or_b32", VOP_I32_I32_I32, or >; -defm V_XOR_B32 : VOP2Inst , "V_XOR_B32", +defm V_XOR_B32 : VOP2Inst , "v_xor_b32", VOP_I32_I32_I32, xor >; } // End isCommutable = 1 -defm V_BFM_B32 : VOP2Inst , "V_BFM_B32", +defm V_BFM_B32 : VOP2Inst , "v_bfm_b32", VOP_I32_I32_I32, AMDGPUbfm>; -defm V_MAC_F32 : VOP2Inst , "V_MAC_F32", VOP_F32_F32_F32>; -defm V_MADMK_F32 : VOP2Inst , "V_MADMK_F32", VOP_F32_F32_F32>; -defm V_MADAK_F32 : VOP2Inst , "V_MADAK_F32", VOP_F32_F32_F32>; -defm V_BCNT_U32_B32 : VOP2Inst , "V_BCNT_U32_B32", VOP_I32_I32_I32>; -defm V_MBCNT_LO_U32_B32 : VOP2Inst , "V_MBCNT_LO_U32_B32", +defm V_MAC_F32 : VOP2Inst , "v_mac_f32", VOP_F32_F32_F32>; +defm V_MADMK_F32 : VOP2Inst , "v_madmk_f32", VOP_F32_F32_F32>; +defm V_MADAK_F32 : VOP2Inst , "v_madak_f32", VOP_F32_F32_F32>; +defm V_BCNT_U32_B32 : VOP2Inst , "v_bcnt_u32_b32", VOP_I32_I32_I32>; +defm V_MBCNT_LO_U32_B32 : VOP2Inst , "v_mbcnt_lo_u32_b32", VOP_I32_I32_I32 >; -defm V_MBCNT_HI_U32_B32 : VOP2Inst , "V_MBCNT_HI_U32_B32", +defm V_MBCNT_HI_U32_B32 : VOP2Inst , "v_mbcnt_hi_u32_b32", VOP_I32_I32_I32 >; let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC // No patterns so that the scalar instructions are always selected. // The scalar versions will be replaced with vector when needed later. -defm V_ADD_I32 : VOP2bInst , "V_ADD_I32", +defm V_ADD_I32 : VOP2bInst , "v_add_i32", VOP_I32_I32_I32, add >; -defm V_SUB_I32 : VOP2bInst , "V_SUB_I32", +defm V_SUB_I32 : VOP2bInst , "v_sub_i32", VOP_I32_I32_I32, sub >; -defm V_SUBREV_I32 : VOP2bInst , "V_SUBREV_I32", - VOP_I32_I32_I32, null_frag, "V_SUB_I32" +defm V_SUBREV_I32 : VOP2bInst , "v_subrev_i32", + VOP_I32_I32_I32, null_frag, "v_sub_i32" >; let Uses = [VCC] in { // Carry-in comes from VCC -defm V_ADDC_U32 : VOP2bInst , "V_ADDC_U32", +defm V_ADDC_U32 : VOP2bInst , "v_addc_u32", VOP_I32_I32_I32_VCC, adde >; -defm V_SUBB_U32 : VOP2bInst , "V_SUBB_U32", +defm V_SUBB_U32 : VOP2bInst , "v_subb_u32", VOP_I32_I32_I32_VCC, sube >; -defm V_SUBBREV_U32 : VOP2bInst , "V_SUBBREV_U32", - VOP_I32_I32_I32_VCC, null_frag, "V_SUBB_U32" +defm V_SUBBREV_U32 : VOP2bInst , "v_subbrev_u32", + VOP_I32_I32_I32_VCC, null_frag, "v_subb_u32" >; } // End Uses = [VCC] } // End isCommutable = 1, Defs = [VCC] -defm V_LDEXP_F32 : VOP2Inst , "V_LDEXP_F32", +defm V_LDEXP_F32 : VOP2Inst , "v_ldexp_f32", VOP_F32_F32_I32, AMDGPUldexp >; -////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; -////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; -////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>; -defm V_CVT_PKRTZ_F16_F32 : VOP2Inst , "V_CVT_PKRTZ_F16_F32", +////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "v_cvt_pkaccum_u8_f32", []>; +////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "v_cvt_pknorm_i16_f32", []>; +////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "v_cvt_pknorm_u16_f32", []>; +defm V_CVT_PKRTZ_F16_F32 : VOP2Inst , "v_cvt_pkrtz_f16_f32", VOP_I32_F32_F32, int_SI_packf16 >; -////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>; -////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>; +////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "v_cvt_pk_u16_u32", []>; +////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "v_cvt_pk_i16_i32", []>; //===----------------------------------------------------------------------===// // VOP3 Instructions //===----------------------------------------------------------------------===// -defm V_MAD_LEGACY_F32 : VOP3Inst , "V_MAD_LEGACY_F32", +defm V_MAD_LEGACY_F32 : VOP3Inst , "v_mad_legacy_f32", VOP_F32_F32_F32_F32 >; -defm V_MAD_F32 : VOP3Inst , "V_MAD_F32", +defm V_MAD_F32 : VOP3Inst , "v_mad_f32", VOP_F32_F32_F32_F32, fmad >; -defm V_MAD_I32_I24 : VOP3Inst , "V_MAD_I32_I24", +defm V_MAD_I32_I24 : VOP3Inst , "v_mad_i32_i24", VOP_I32_I32_I32_I32, AMDGPUmad_i24 >; -defm V_MAD_U32_U24 : VOP3Inst , "V_MAD_U32_U24", +defm V_MAD_U32_U24 : VOP3Inst , "v_mad_u32_u24", VOP_I32_I32_I32_I32, AMDGPUmad_u24 >; -defm V_CUBEID_F32 : VOP3Inst , "V_CUBEID_F32", +defm V_CUBEID_F32 : VOP3Inst , "v_cubeid_f32", VOP_F32_F32_F32_F32 >; -defm V_CUBESC_F32 : VOP3Inst , "V_CUBESC_F32", +defm V_CUBESC_F32 : VOP3Inst , "v_cubesc_f32", VOP_F32_F32_F32_F32 >; -defm V_CUBETC_F32 : VOP3Inst , "V_CUBETC_F32", +defm V_CUBETC_F32 : VOP3Inst , "v_cubetc_f32", VOP_F32_F32_F32_F32 >; -defm V_CUBEMA_F32 : VOP3Inst , "V_CUBEMA_F32", +defm V_CUBEMA_F32 : VOP3Inst , "v_cubema_f32", VOP_F32_F32_F32_F32 >; -defm V_BFE_U32 : VOP3Inst , "V_BFE_U32", +defm V_BFE_U32 : VOP3Inst , "v_bfe_u32", VOP_I32_I32_I32_I32, AMDGPUbfe_u32 >; -defm V_BFE_I32 : VOP3Inst , "V_BFE_I32", +defm V_BFE_I32 : VOP3Inst , "v_bfe_i32", VOP_I32_I32_I32_I32, AMDGPUbfe_i32 >; -defm V_BFI_B32 : VOP3Inst , "V_BFI_B32", +defm V_BFI_B32 : VOP3Inst , "v_bfi_b32", VOP_I32_I32_I32_I32, AMDGPUbfi >; -defm V_FMA_F32 : VOP3Inst , "V_FMA_F32", +defm V_FMA_F32 : VOP3Inst , "v_fma_f32", VOP_F32_F32_F32_F32, fma >; -defm V_FMA_F64 : VOP3Inst , "V_FMA_F64", +defm V_FMA_F64 : VOP3Inst , "v_fma_f64", VOP_F64_F64_F64_F64, fma >; -//def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; -defm V_ALIGNBIT_B32 : VOP3Inst , "V_ALIGNBIT_B32", +//def V_LERP_U8 : VOP3_U8 <0x0000014d, "v_lerp_u8", []>; +defm V_ALIGNBIT_B32 : VOP3Inst , "v_alignbit_b32", VOP_I32_I32_I32_I32 >; -defm V_ALIGNBYTE_B32 : VOP3Inst , "V_ALIGNBYTE_B32", +defm V_ALIGNBYTE_B32 : VOP3Inst , "v_alignbyte_b32", VOP_I32_I32_I32_I32 >; -defm V_MULLIT_F32 : VOP3Inst , "V_MULLIT_F32", +defm V_MULLIT_F32 : VOP3Inst , "v_mullit_f32", VOP_F32_F32_F32_F32>; -////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; -////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; -////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>; -////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>; -////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>; -////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>; -////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>; -////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>; -////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>; -//def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; -//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; -//def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; -defm V_SAD_U32 : VOP3Inst , "V_SAD_U32", +////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "v_min3_f32", []>; +////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "v_min3_i32", []>; +////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "v_min3_u32", []>; +////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "v_max3_f32", []>; +////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "v_max3_i32", []>; +////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "v_max3_u32", []>; +////def V_MED3_F32 : VOP3_MED3 <0x00000157, "v_med3_f32", []>; +////def V_MED3_I32 : VOP3_MED3 <0x00000158, "v_med3_i32", []>; +////def V_MED3_U32 : VOP3_MED3 <0x00000159, "v_med3_u32", []>; +//def V_SAD_U8 : VOP3_U8 <0x0000015a, "v_sad_u8", []>; +//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "v_sad_hi_u8", []>; +//def V_SAD_U16 : VOP3_U16 <0x0000015c, "v_sad_u16", []>; +defm V_SAD_U32 : VOP3Inst , "v_sad_u32", VOP_I32_I32_I32_I32 >; -////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; +////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "v_cvt_pk_u8_f32", []>; defm V_DIV_FIXUP_F32 : VOP3Inst < - vop3<0x15f>, "V_DIV_FIXUP_F32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup + vop3<0x15f>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup >; defm V_DIV_FIXUP_F64 : VOP3Inst < - vop3<0x160>, "V_DIV_FIXUP_F64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup + vop3<0x160>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup >; -defm V_LSHL_B64 : VOP3Inst , "V_LSHL_B64", +defm V_LSHL_B64 : VOP3Inst , "v_lshl_b64", VOP_I64_I64_I32, shl >; -defm V_LSHR_B64 : VOP3Inst , "V_LSHR_B64", +defm V_LSHR_B64 : VOP3Inst , "v_lshr_b64", VOP_I64_I64_I32, srl >; -defm V_ASHR_I64 : VOP3Inst , "V_ASHR_I64", +defm V_ASHR_I64 : VOP3Inst , "v_ashr_i64", VOP_I64_I64_I32, sra >; let isCommutable = 1 in { -defm V_ADD_F64 : VOP3Inst , "V_ADD_F64", +defm V_ADD_F64 : VOP3Inst , "v_add_f64", VOP_F64_F64_F64, fadd >; -defm V_MUL_F64 : VOP3Inst , "V_MUL_F64", +defm V_MUL_F64 : VOP3Inst , "v_mul_f64", VOP_F64_F64_F64, fmul >; -defm V_MIN_F64 : VOP3Inst , "V_MIN_F64", +defm V_MIN_F64 : VOP3Inst , "v_min_f64", VOP_F64_F64_F64, fminnum >; -defm V_MAX_F64 : VOP3Inst , "V_MAX_F64", +defm V_MAX_F64 : VOP3Inst , "v_max_f64", VOP_F64_F64_F64, fmaxnum >; } // isCommutable = 1 -defm V_LDEXP_F64 : VOP3Inst , "V_LDEXP_F64", +defm V_LDEXP_F64 : VOP3Inst , "v_ldexp_f64", VOP_F64_F64_I32, AMDGPUldexp >; let isCommutable = 1 in { -defm V_MUL_LO_U32 : VOP3Inst , "V_MUL_LO_U32", +defm V_MUL_LO_U32 : VOP3Inst , "v_mul_lo_u32", VOP_I32_I32_I32 >; -defm V_MUL_HI_U32 : VOP3Inst , "V_MUL_HI_U32", +defm V_MUL_HI_U32 : VOP3Inst , "v_mul_hi_u32", VOP_I32_I32_I32 >; -defm V_MUL_LO_I32 : VOP3Inst , "V_MUL_LO_I32", +defm V_MUL_LO_I32 : VOP3Inst , "v_mul_lo_i32", VOP_I32_I32_I32 >; -defm V_MUL_HI_I32 : VOP3Inst , "V_MUL_HI_I32", +defm V_MUL_HI_I32 : VOP3Inst , "v_mul_hi_i32", VOP_I32_I32_I32 >; } // isCommutable = 1 -defm V_DIV_SCALE_F32 : VOP3b_32 , "V_DIV_SCALE_F32", []>; +defm V_DIV_SCALE_F32 : VOP3b_32 , "v_div_scale_f32", []>; // Double precision division pre-scale. -defm V_DIV_SCALE_F64 : VOP3b_64 , "V_DIV_SCALE_F64", []>; +defm V_DIV_SCALE_F64 : VOP3b_64 , "v_div_scale_f64", []>; -defm V_DIV_FMAS_F32 : VOP3Inst , "V_DIV_FMAS_F32", +defm V_DIV_FMAS_F32 : VOP3Inst , "v_div_fmas_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fmas >; -defm V_DIV_FMAS_F64 : VOP3Inst , "V_DIV_FMAS_F64", +defm V_DIV_FMAS_F64 : VOP3Inst , "v_div_fmas_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fmas >; -//def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; -//def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; -//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; +//def V_MSAD_U8 : VOP3_U8 <0x00000171, "v_msad_u8", []>; +//def V_QSAD_U8 : VOP3_U8 <0x00000172, "v_qsad_u8", []>; +//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "v_mqsad_u8", []>; defm V_TRIG_PREOP_F64 : VOP3Inst < - vop3<0x174>, "V_TRIG_PREOP_F64", VOP_F64_F64_I32, AMDGPUtrig_preop + vop3<0x174>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop >; //===----------------------------------------------------------------------===// @@ -1700,7 +1700,7 @@ def SI_ELSE : InstSI < def SI_LOOP : InstSI < (outs), (ins SReg_64:$saved, brtarget:$target), - "SI_LOOP $saved, $target", + "si_loop $saved, $target", [(int_SI_loop i64:$saved, bb:$target)] >; @@ -1709,35 +1709,35 @@ def SI_LOOP : InstSI < def SI_BREAK : InstSI < (outs SReg_64:$dst), (ins SReg_64:$src), - "SI_ELSE $dst, $src", + "si_else $dst, $src", [(set i64:$dst, (int_SI_break i64:$src))] >; def SI_IF_BREAK : InstSI < (outs SReg_64:$dst), (ins SReg_64:$vcc, SReg_64:$src), - "SI_IF_BREAK $dst, $vcc, $src", + "si_if_break $dst, $vcc, $src", [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))] >; def SI_ELSE_BREAK : InstSI < (outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1), - "SI_ELSE_BREAK $dst, $src0, $src1", + "si_else_break $dst, $src0, $src1", [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))] >; def SI_END_CF : InstSI < (outs), (ins SReg_64:$saved), - "SI_END_CF $saved", + "si_end_cf $saved", [(int_SI_end_cf i64:$saved)] >; def SI_KILL : InstSI < (outs), (ins VSrc_32:$src), - "SI_KILL $src", + "si_kill $src", [(int_AMDGPU_kill f32:$src)] >; @@ -1779,14 +1779,14 @@ def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>; def SI_INDIRECT_SRC : InstSI < (outs VReg_32:$dst, SReg_64:$temp), (ins unknown:$src, VSrc_32:$idx, i32imm:$off), - "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off", + "si_indirect_src $dst, $temp, $src, $idx, $off", [] >; class SI_INDIRECT_DST : InstSI < (outs rc:$dst, SReg_64:$temp), (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val), - "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val", + "si_indirect_dst $dst, $temp, $src, $idx, $off, $val", [] > { let Constraints = "$src = $dst"; @@ -1813,7 +1813,7 @@ def SI_ADDR64_RSRC : InstSI < def V_SUB_F64 : InstSI < (outs VReg_64:$dst), (ins VReg_64:$src0, VReg_64:$src1), - "V_SUB_F64 $dst, $src0, $src1", + "v_sub_f64 $dst, $src0, $src1", [(set f64:$dst, (fsub f64:$src0, f64:$src1))] >; @@ -2377,7 +2377,7 @@ def : BitConvert ; def FCLAMP_SI : AMDGPUShaderInst < (outs VReg_32:$dst), (ins VSrc_32:$src0), - "FCLAMP_SI $dst, $src0", + "fclamp_si $dst, $src0", [] > { let usesCustomInserter = 1; @@ -2826,34 +2826,34 @@ def : MTBUF_StoreResource ; let SubtargetPredicate = isCI in { // Sea island new arithmetic instructinos -defm V_TRUNC_F64 : VOP1Inst , "V_TRUNC_F64", +defm V_TRUNC_F64 : VOP1Inst , "v_trunc_f64", VOP_F64_F64, ftrunc >; -defm V_CEIL_F64 : VOP1Inst , "V_CEIL_F64", +defm V_CEIL_F64 : VOP1Inst , "v_ceil_f64", VOP_F64_F64, fceil >; -defm V_FLOOR_F64 : VOP1Inst , "V_FLOOR_F64", +defm V_FLOOR_F64 : VOP1Inst , "v_floor_f64", VOP_F64_F64, ffloor >; -defm V_RNDNE_F64 : VOP1Inst , "V_RNDNE_F64", +defm V_RNDNE_F64 : VOP1Inst , "v_rndne_f64", VOP_F64_F64, frint >; -defm V_QSAD_PK_U16_U8 : VOP3Inst , "V_QSAD_PK_U16_U8", +defm V_QSAD_PK_U16_U8 : VOP3Inst , "v_qsad_pk_u16_u8", VOP_I32_I32_I32 >; -defm V_MQSAD_U16_U8 : VOP3Inst , "V_MQSAD_U16_U8", +defm V_MQSAD_U16_U8 : VOP3Inst , "v_mqsad_u16_u8", VOP_I32_I32_I32 >; -defm V_MQSAD_U32_U8 : VOP3Inst , "V_MQSAD_U32_U8", +defm V_MQSAD_U32_U8 : VOP3Inst , "v_mqsad_u32_u8", VOP_I32_I32_I32 >; -defm V_MAD_U64_U32 : VOP3Inst , "V_MAD_U64_U32", +defm V_MAD_U64_U32 : VOP3Inst , "v_mad_u64_u32", VOP_I64_I32_I32_I64 >; // XXX - Does this set VCC? -defm V_MAD_I64_I32 : VOP3Inst , "V_MAD_I64_I32", +defm V_MAD_I64_I32 : VOP3Inst , "v_mad_i64_i32", VOP_I64_I32_I32_I64 >; diff --git a/test/CodeGen/R600/128bit-kernel-args.ll b/test/CodeGen/R600/128bit-kernel-args.ll index 27fae51ce76..d9b0ff258a1 100644 --- a/test/CodeGen/R600/128bit-kernel-args.ll +++ b/test/CodeGen/R600/128bit-kernel-args.ll @@ -7,7 +7,7 @@ ; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].Z, KC0[3].W ; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].W, KC0[4].X ; SI-CHECK: {{^}}v4i32_kernel_arg: -; SI-CHECK: BUFFER_STORE_DWORDX4 +; SI-CHECK: buffer_store_dwordx4 define void @v4i32_kernel_arg(<4 x i32> addrspace(1)* %out, <4 x i32> %in) { entry: store <4 x i32> %in, <4 x i32> addrspace(1)* %out @@ -20,7 +20,7 @@ entry: ; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].Z, KC0[3].W ; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].W, KC0[4].X ; SI-CHECK: {{^}}v4f32_kernel_arg: -; SI-CHECK: BUFFER_STORE_DWORDX4 +; SI-CHECK: buffer_store_dwordx4 define void @v4f32_kernel_arg(<4 x float> addrspace(1)* %out, <4 x float> %in) { entry: store <4 x float> %in, <4 x float> addrspace(1)* %out diff --git a/test/CodeGen/R600/32-bit-local-address-space.ll b/test/CodeGen/R600/32-bit-local-address-space.ll index 3618f8271b5..10fed83f289 100644 --- a/test/CodeGen/R600/32-bit-local-address-space.ll +++ b/test/CodeGen/R600/32-bit-local-address-space.ll @@ -11,8 +11,8 @@ ; instructions with B64, U64, and I64 take 64-bit operands. ; FUNC-LABEL: {{^}}local_address_load: -; CHECK: V_MOV_B32_e{{32|64}} [[PTR:v[0-9]]] -; CHECK: DS_READ_B32 v{{[0-9]+}}, [[PTR]] +; CHECK: v_mov_b32_e{{32|64}} [[PTR:v[0-9]]] +; CHECK: ds_read_b32 v{{[0-9]+}}, [[PTR]] define void @local_address_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { entry: %0 = load i32 addrspace(3)* %in @@ -21,9 +21,9 @@ entry: } ; FUNC-LABEL: {{^}}local_address_gep: -; CHECK: S_ADD_I32 [[SPTR:s[0-9]]] -; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]] -; CHECK: DS_READ_B32 [[VPTR]] +; CHECK: s_add_i32 [[SPTR:s[0-9]]] +; CHECK: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] +; CHECK: ds_read_b32 [[VPTR]] define void @local_address_gep(i32 addrspace(1)* %out, i32 addrspace(3)* %in, i32 %offset) { entry: %0 = getelementptr i32 addrspace(3)* %in, i32 %offset @@ -33,8 +33,8 @@ entry: } ; FUNC-LABEL: {{^}}local_address_gep_const_offset: -; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}} -; CHECK: DS_READ_B32 v{{[0-9]+}}, [[VPTR]], 0x4, +; CHECK: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}} +; CHECK: ds_read_b32 v{{[0-9]+}}, [[VPTR]], 0x4, define void @local_address_gep_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { entry: %0 = getelementptr i32 addrspace(3)* %in, i32 1 @@ -45,9 +45,9 @@ entry: ; Offset too large, can't fold into 16-bit immediate offset. ; FUNC-LABEL: {{^}}local_address_gep_large_const_offset: -; CHECK: S_ADD_I32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004 -; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]] -; CHECK: DS_READ_B32 [[VPTR]] +; CHECK: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004 +; CHECK: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] +; CHECK: ds_read_b32 [[VPTR]] define void @local_address_gep_large_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { entry: %0 = getelementptr i32 addrspace(3)* %in, i32 16385 @@ -57,8 +57,8 @@ entry: } ; FUNC-LABEL: {{^}}null_32bit_lds_ptr: -; CHECK: V_CMP_NE_I32 -; CHECK-NOT: V_CMP_NE_I32 +; CHECK: v_cmp_ne_i32 +; CHECK-NOT: v_cmp_ne_i32 ; CHECK: V_CNDMASK_B32 define void @null_32bit_lds_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %lds) nounwind { %cmp = icmp ne i32 addrspace(3)* %lds, null @@ -68,9 +68,9 @@ define void @null_32bit_lds_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %lds) } ; FUNC-LABEL: {{^}}mul_32bit_ptr: -; CHECK: V_MUL_LO_I32 -; CHECK-NEXT: V_ADD_I32_e32 -; CHECK-NEXT: DS_READ_B32 +; CHECK: v_mul_lo_i32 +; CHECK-NEXT: v_add_i32_e32 +; CHECK-NEXT: ds_read_b32 define void @mul_32bit_ptr(float addrspace(1)* %out, [3 x float] addrspace(3)* %lds, i32 %tid) { %ptr = getelementptr [3 x float] addrspace(3)* %lds, i32 %tid, i32 0 %val = load float addrspace(3)* %ptr @@ -81,8 +81,8 @@ define void @mul_32bit_ptr(float addrspace(1)* %out, [3 x float] addrspace(3)* % @g_lds = addrspace(3) global float zeroinitializer, align 4 ; FUNC-LABEL: {{^}}infer_ptr_alignment_global_offset: -; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0 -; CHECK: DS_READ_B32 v{{[0-9]+}}, [[REG]] +; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0 +; CHECK: ds_read_b32 v{{[0-9]+}}, [[REG]] define void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %tid) { %val = load float addrspace(3)* @g_lds store float %val, float addrspace(1)* %out @@ -94,23 +94,23 @@ define void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %ti @dst = addrspace(3) global [16384 x i32] zeroinitializer ; FUNC-LABEL: {{^}}global_ptr: -; CHECK: DS_WRITE_B32 +; CHECK: ds_write_b32 define void @global_ptr() nounwind { store i32 addrspace(3)* getelementptr ([16384 x i32] addrspace(3)* @dst, i32 0, i32 16), i32 addrspace(3)* addrspace(3)* @ptr ret void } ; FUNC-LABEL: {{^}}local_address_store: -; CHECK: DS_WRITE_B32 +; CHECK: ds_write_b32 define void @local_address_store(i32 addrspace(3)* %out, i32 %val) { store i32 %val, i32 addrspace(3)* %out ret void } ; FUNC-LABEL: {{^}}local_address_gep_store: -; CHECK: S_ADD_I32 [[SADDR:s[0-9]+]], -; CHECK: V_MOV_B32_e32 [[ADDR:v[0-9]+]], [[SADDR]] -; CHECK: DS_WRITE_B32 [[ADDR]], v{{[0-9]+}}, +; CHECK: s_add_i32 [[SADDR:s[0-9]+]], +; CHECK: v_mov_b32_e32 [[ADDR:v[0-9]+]], [[SADDR]] +; CHECK: ds_write_b32 [[ADDR]], v{{[0-9]+}}, define void @local_address_gep_store(i32 addrspace(3)* %out, i32, i32 %val, i32 %offset) { %gep = getelementptr i32 addrspace(3)* %out, i32 %offset store i32 %val, i32 addrspace(3)* %gep, align 4 @@ -118,9 +118,9 @@ define void @local_address_gep_store(i32 addrspace(3)* %out, i32, i32 %val, i32 } ; FUNC-LABEL: {{^}}local_address_gep_const_offset_store: -; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}} -; CHECK: V_MOV_B32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}} -; CHECK: DS_WRITE_B32 [[VPTR]], [[VAL]], 0x4 +; CHECK: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}} +; CHECK: v_mov_b32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}} +; CHECK: ds_write_b32 [[VPTR]], [[VAL]], 0x4 define void @local_address_gep_const_offset_store(i32 addrspace(3)* %out, i32 %val) { %gep = getelementptr i32 addrspace(3)* %out, i32 1 store i32 %val, i32 addrspace(3)* %gep, align 4 @@ -129,9 +129,9 @@ define void @local_address_gep_const_offset_store(i32 addrspace(3)* %out, i32 %v ; Offset too large, can't fold into 16-bit immediate offset. ; FUNC-LABEL: {{^}}local_address_gep_large_const_offset_store: -; CHECK: S_ADD_I32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004 -; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]] -; CHECK: DS_WRITE_B32 [[VPTR]], v{{[0-9]+}}, 0 +; CHECK: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004 +; CHECK: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] +; CHECK: ds_write_b32 [[VPTR]], v{{[0-9]+}}, 0 define void @local_address_gep_large_const_offset_store(i32 addrspace(3)* %out, i32 %val) { %gep = getelementptr i32 addrspace(3)* %out, i32 16385 store i32 %val, i32 addrspace(3)* %gep, align 4 diff --git a/test/CodeGen/R600/64bit-kernel-args.ll b/test/CodeGen/R600/64bit-kernel-args.ll index 9e1f02baab7..cf4e055f496 100644 --- a/test/CodeGen/R600/64bit-kernel-args.ll +++ b/test/CodeGen/R600/64bit-kernel-args.ll @@ -1,9 +1,9 @@ ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK ; SI-CHECK: {{^}}f64_kernel_arg: -; SI-CHECK-DAG: S_LOAD_DWORDX2 s[{{[0-9]:[0-9]}}], s[0:1], 0x9 -; SI-CHECK-DAG: S_LOAD_DWORDX2 s[{{[0-9]:[0-9]}}], s[0:1], 0xb -; SI-CHECK: BUFFER_STORE_DWORDX2 +; SI-CHECK-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x9 +; SI-CHECK-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0xb +; SI-CHECK: buffer_store_dwordx2 define void @f64_kernel_arg(double addrspace(1)* %out, double %in) { entry: store double %in, double addrspace(1)* %out diff --git a/test/CodeGen/R600/add.ll b/test/CodeGen/R600/add.ll index 9bea9be8485..767a6420908 100644 --- a/test/CodeGen/R600/add.ll +++ b/test/CodeGen/R600/add.ll @@ -4,9 +4,9 @@ ;FUNC-LABEL: {{^}}test1: ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: V_ADD_I32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}} ;SI-CHECK-NOT: [[REG]] -;SI-CHECK: BUFFER_STORE_DWORD [[REG]], +;SI-CHECK: buffer_store_dword [[REG]], define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1 %a = load i32 addrspace(1)* %in @@ -20,8 +20,8 @@ define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -38,10 +38,10 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 @@ -61,14 +61,14 @@ define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { ; EG-CHECK: ADD_INT ; EG-CHECK: ADD_INT ; EG-CHECK: ADD_INT -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 define void @test8(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) { entry: %0 = add <8 x i32> %a, %b @@ -93,22 +93,22 @@ entry: ; EG-CHECK: ADD_INT ; EG-CHECK: ADD_INT ; EG-CHECK: ADD_INT -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 define void @test16(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) { entry: %0 = add <16 x i32> %a, %b @@ -117,8 +117,8 @@ entry: } ; FUNC-LABEL: {{^}}add64: -; SI-CHECK: S_ADD_U32 -; SI-CHECK: S_ADDC_U32 +; SI-CHECK: s_add_u32 +; SI-CHECK: s_addc_u32 define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) { entry: %0 = add i64 %a, %b @@ -126,13 +126,13 @@ entry: ret void } -; The V_ADDC_U32 and V_ADD_I32 instruction can't read SGPRs, because they +; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they ; use VCC. The test is designed so that %a will be stored in an SGPR and ; %0 will be stored in a VGPR, so the comiler will be forced to copy %a ; to a VGPR before doing the add. ; FUNC-LABEL: {{^}}add64_sgpr_vgpr: -; SI-CHECK-NOT: V_ADDC_U32_e32 s +; SI-CHECK-NOT: v_addc_u32_e32 s define void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) { entry: %0 = load i64 addrspace(1)* %in @@ -143,8 +143,8 @@ entry: ; Test i64 add inside a branch. ; FUNC-LABEL: {{^}}add64_in_branch: -; SI-CHECK: S_ADD_U32 -; SI-CHECK: S_ADDC_U32 +; SI-CHECK: s_add_u32 +; SI-CHECK: s_addc_u32 define void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) { entry: %0 = icmp eq i64 %a, 0 diff --git a/test/CodeGen/R600/add_i64.ll b/test/CodeGen/R600/add_i64.ll index 0e3789e4c02..47ecf6d8774 100644 --- a/test/CodeGen/R600/add_i64.ll +++ b/test/CodeGen/R600/add_i64.ll @@ -4,8 +4,8 @@ declare i32 @llvm.r600.read.tidig.x() readnone ; SI-LABEL: {{^}}test_i64_vreg: -; SI: V_ADD_I32 -; SI: V_ADDC_U32 +; SI: v_add_i32 +; SI: v_addc_u32 define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) { %tid = call i32 @llvm.r600.read.tidig.x() readnone %a_ptr = getelementptr i64 addrspace(1)* %inA, i32 %tid @@ -19,8 +19,8 @@ define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noa ; Check that the SGPR add operand is correctly moved to a VGPR. ; SI-LABEL: {{^}}sgpr_operand: -; SI: V_ADD_I32 -; SI: V_ADDC_U32 +; SI: v_add_i32 +; SI: v_addc_u32 define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) { %foo = load i64 addrspace(1)* %in, align 8 %result = add i64 %foo, %a @@ -32,8 +32,8 @@ define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noal ; SGPR as other operand. ; ; SI-LABEL: {{^}}sgpr_operand_reversed: -; SI: V_ADD_I32 -; SI: V_ADDC_U32 +; SI: v_add_i32 +; SI: v_addc_u32 define void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) { %foo = load i64 addrspace(1)* %in, align 8 %result = add i64 %a, %foo @@ -43,10 +43,10 @@ define void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace ; SI-LABEL: {{^}}test_v2i64_sreg: -; SI: S_ADD_U32 -; SI: S_ADDC_U32 -; SI: S_ADD_U32 -; SI: S_ADDC_U32 +; SI: s_add_u32 +; SI: s_addc_u32 +; SI: s_add_u32 +; SI: s_addc_u32 define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, <2 x i64> %b) { %result = add <2 x i64> %a, %b store <2 x i64> %result, <2 x i64> addrspace(1)* %out @@ -54,10 +54,10 @@ define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, } ; SI-LABEL: {{^}}test_v2i64_vreg: -; SI: V_ADD_I32 -; SI: V_ADDC_U32 -; SI: V_ADD_I32 -; SI: V_ADDC_U32 +; SI: v_add_i32 +; SI: v_addc_u32 +; SI: v_add_i32 +; SI: v_addc_u32 define void @test_v2i64_vreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) { %tid = call i32 @llvm.r600.read.tidig.x() readnone %a_ptr = getelementptr <2 x i64> addrspace(1)* %inA, i32 %tid @@ -70,12 +70,12 @@ define void @test_v2i64_vreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> add } ; SI-LABEL: {{^}}trunc_i64_add_to_i32: -; SI: S_LOAD_DWORD s[[SREG0:[0-9]+]] -; SI: S_LOAD_DWORD s[[SREG1:[0-9]+]] -; SI: S_ADD_I32 [[SRESULT:s[0-9]+]], s[[SREG1]], s[[SREG0]] -; SI-NOT: ADDC -; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] -; SI: BUFFER_STORE_DWORD [[VRESULT]], +; SI: s_load_dword s[[SREG0:[0-9]+]] +; SI: s_load_dword s[[SREG1:[0-9]+]] +; SI: s_add_i32 [[SRESULT:s[0-9]+]], s[[SREG1]], s[[SREG0]] +; SI-NOT: addc +; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] +; SI: buffer_store_dword [[VRESULT]], define void @trunc_i64_add_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) { %add = add i64 %b, %a %trunc = trunc i64 %add to i32 diff --git a/test/CodeGen/R600/address-space.ll b/test/CodeGen/R600/address-space.ll index a1f9d9183af..d04afe634ba 100644 --- a/test/CodeGen/R600/address-space.ll +++ b/test/CodeGen/R600/address-space.ll @@ -8,10 +8,10 @@ ; already in a VGPR after the first read. ; CHECK-LABEL: {{^}}do_as_ptr_calcs: -; CHECK: S_LOAD_DWORD [[SREG1:s[0-9]+]], -; CHECK: V_MOV_B32_e32 [[VREG1:v[0-9]+]], [[SREG1]] -; CHECK-DAG: DS_READ_B32 v{{[0-9]+}}, [[VREG1]] offset:12 -; CHECK-DAG: DS_READ_B32 v{{[0-9]+}}, v{{[0-9]+}} offset:20 +; CHECK: s_load_dword [[SREG1:s[0-9]+]], +; CHECK: v_mov_b32_e32 [[VREG1:v[0-9]+]], [[SREG1]] +; CHECK-DAG: ds_read_b32 v{{[0-9]+}}, [[VREG1]] offset:12 +; CHECK-DAG: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:20 define void @do_as_ptr_calcs(%struct.foo addrspace(3)* nocapture %ptr) nounwind { entry: %x = getelementptr inbounds %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 0 diff --git a/test/CodeGen/R600/and.ll b/test/CodeGen/R600/and.ll index 9c0eb89e7df..9a76fce3c34 100644 --- a/test/CodeGen/R600/and.ll +++ b/test/CodeGen/R600/and.ll @@ -5,8 +5,8 @@ ; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; SI: V_AND_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; SI: V_AND_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -23,10 +23,10 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { ; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; SI: V_AND_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; SI: V_AND_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; SI: V_AND_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; SI: V_AND_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 @@ -38,7 +38,7 @@ define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}s_and_i32: -; SI: S_AND_B32 +; SI: s_and_b32 define void @s_and_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { %and = and i32 %a, %b store i32 %and, i32 addrspace(1)* %out, align 4 @@ -46,7 +46,7 @@ define void @s_and_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { } ; FUNC-LABEL: {{^}}s_and_constant_i32: -; SI: S_AND_B32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687 +; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687 define void @s_and_constant_i32(i32 addrspace(1)* %out, i32 %a) { %and = and i32 %a, 1234567 store i32 %and, i32 addrspace(1)* %out, align 4 @@ -54,7 +54,7 @@ define void @s_and_constant_i32(i32 addrspace(1)* %out, i32 %a) { } ; FUNC-LABEL: {{^}}v_and_i32: -; SI: V_AND_B32 +; SI: v_and_b32 define void @v_and_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) { %a = load i32 addrspace(1)* %aptr, align 4 %b = load i32 addrspace(1)* %bptr, align 4 @@ -64,7 +64,7 @@ define void @v_and_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addr } ; FUNC-LABEL: {{^}}v_and_constant_i32: -; SI: V_AND_B32 +; SI: v_and_b32 define void @v_and_constant_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) { %a = load i32 addrspace(1)* %aptr, align 4 %and = and i32 %a, 1234567 @@ -73,7 +73,7 @@ define void @v_and_constant_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) } ; FUNC-LABEL: {{^}}s_and_i64: -; SI: S_AND_B64 +; SI: s_and_b64 define void @s_and_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { %and = and i64 %a, %b store i64 %and, i64 addrspace(1)* %out, align 8 @@ -82,7 +82,7 @@ define void @s_and_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { ; FIXME: Should use SGPRs ; FUNC-LABEL: {{^}}s_and_i1: -; SI: V_AND_B32 +; SI: v_and_b32 define void @s_and_i1(i1 addrspace(1)* %out, i1 %a, i1 %b) { %and = and i1 %a, %b store i1 %and, i1 addrspace(1)* %out @@ -90,7 +90,7 @@ define void @s_and_i1(i1 addrspace(1)* %out, i1 %a, i1 %b) { } ; FUNC-LABEL: {{^}}s_and_constant_i64: -; SI: S_AND_B64 +; SI: s_and_b64 define void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) { %and = and i64 %a, 281474976710655 store i64 %and, i64 addrspace(1)* %out, align 8 @@ -98,8 +98,8 @@ define void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) { } ; FUNC-LABEL: {{^}}v_and_i64: -; SI: V_AND_B32 -; SI: V_AND_B32 +; SI: v_and_b32 +; SI: v_and_b32 define void @v_and_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) { %a = load i64 addrspace(1)* %aptr, align 8 %b = load i64 addrspace(1)* %bptr, align 8 @@ -109,8 +109,8 @@ define void @v_and_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addr } ; FUNC-LABEL: {{^}}v_and_i64_br: -; SI: V_AND_B32 -; SI: V_AND_B32 +; SI: v_and_b32 +; SI: v_and_b32 define void @v_and_i64_br(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i32 %cond) { entry: %tmp0 = icmp eq i32 %cond, 0 @@ -129,8 +129,8 @@ endif: } ; FUNC-LABEL: {{^}}v_and_constant_i64: -; SI: V_AND_B32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} -; SI: V_AND_B32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} +; SI: v_and_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} +; SI: v_and_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} define void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { %a = load i64 addrspace(1)* %aptr, align 8 %and = and i64 %a, 1234567 @@ -140,8 +140,8 @@ define void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) ; FIXME: Replace and 0 with mov 0 ; FUNC-LABEL: {{^}}v_and_inline_imm_i64: -; SI: V_AND_B32_e32 {{v[0-9]+}}, 64, {{v[0-9]+}} -; SI: V_AND_B32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}} +; SI: v_and_b32_e32 {{v[0-9]+}}, 64, {{v[0-9]+}} +; SI: v_and_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}} define void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { %a = load i64 addrspace(1)* %aptr, align 8 %and = and i64 %a, 64 @@ -150,7 +150,7 @@ define void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %apt } ; FUNC-LABEL: {{^}}s_and_inline_imm_i64: -; SI: S_AND_B64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 64 +; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 64 define void @s_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { %and = and i64 %a, 64 store i64 %and, i64 addrspace(1)* %out, align 8 diff --git a/test/CodeGen/R600/anyext.ll b/test/CodeGen/R600/anyext.ll index e120951d3c8..23fdcbb69a6 100644 --- a/test/CodeGen/R600/anyext.ll +++ b/test/CodeGen/R600/anyext.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ; CHECK-LABEL: {{^}}anyext_i1_i32: -; CHECK: V_CNDMASK_B32_e64 +; CHECK: v_cndmask_b32_e64 define void @anyext_i1_i32(i32 addrspace(1)* %out, i32 %cond) { entry: %0 = icmp eq i32 %cond, 0 diff --git a/test/CodeGen/R600/array-ptr-calc-i32.ll b/test/CodeGen/R600/array-ptr-calc-i32.ll index 413aba3f17d..84d35401b68 100644 --- a/test/CodeGen/R600/array-ptr-calc-i32.ll +++ b/test/CodeGen/R600/array-ptr-calc-i32.ll @@ -14,16 +14,16 @@ declare void @llvm.AMDGPU.barrier.local() nounwind noduplicate ; FIXME: We end up with zero argument for ADD, because ; SIRegisterInfo::eliminateFrameIndex() blindly replaces the frame index ; with the appropriate offset. We should fold this into the store. -; SI-ALLOCA: V_ADD_I32_e32 [[PTRREG:v[0-9]+]], 0, v{{[0-9]+}} -; SI-ALLOCA: BUFFER_STORE_DWORD {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}] +; SI-ALLOCA: v_add_i32_e32 [[PTRREG:v[0-9]+]], 0, v{{[0-9]+}} +; SI-ALLOCA: buffer_store_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}] ; ; FIXME: The AMDGPUPromoteAlloca pass should be able to convert this ; alloca to a vector. It currently fails because it does not know how ; to interpret: ; getelementptr [4 x i32]* %alloca, i32 1, i32 %b -; SI-PROMOTE: V_ADD_I32_e32 [[PTRREG:v[0-9]+]], 16 -; SI-PROMOTE: DS_WRITE_B32 [[PTRREG]] +; SI-PROMOTE: v_add_i32_e32 [[PTRREG:v[0-9]+]], 16 +; SI-PROMOTE: ds_write_b32 [[PTRREG]] define void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) { %alloca = alloca [4 x i32], i32 4, align 16 %tid = call i32 @llvm.SI.tid() readnone diff --git a/test/CodeGen/R600/array-ptr-calc-i64.ll b/test/CodeGen/R600/array-ptr-calc-i64.ll index 3ffc0b8c348..75f6394873e 100644 --- a/test/CodeGen/R600/array-ptr-calc-i64.ll +++ b/test/CodeGen/R600/array-ptr-calc-i64.ll @@ -3,8 +3,8 @@ declare i32 @llvm.SI.tid() readnone ; SI-LABEL: {{^}}test_array_ptr_calc: -; SI: V_MUL_LO_I32 -; SI: V_MUL_HI_I32 +; SI: v_mul_lo_i32 +; SI: v_mul_hi_i32 define void @test_array_ptr_calc(i32 addrspace(1)* noalias %out, [1025 x i32] addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) { %tid = call i32 @llvm.SI.tid() readnone %a_ptr = getelementptr [1025 x i32] addrspace(1)* %inA, i32 %tid, i32 0 diff --git a/test/CodeGen/R600/atomic_cmp_swap_local.ll b/test/CodeGen/R600/atomic_cmp_swap_local.ll index d5265b3a675..223f4d38d83 100644 --- a/test/CodeGen/R600/atomic_cmp_swap_local.ll +++ b/test/CodeGen/R600/atomic_cmp_swap_local.ll @@ -2,13 +2,13 @@ ; RUN: llc -march=r600 -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=CI -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_offset: -; SI: S_LOAD_DWORD [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI: S_LOAD_DWORD [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI-DAG: V_MOV_B32_e32 [[VCMP:v[0-9]+]], 7 -; SI-DAG: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[PTR]] -; SI-DAG: V_MOV_B32_e32 [[VSWAP:v[0-9]+]], [[SWAP]] -; SI: DS_CMPST_RTN_B32 [[RESULT:v[0-9]+]], [[VPTR]], [[VCMP]], [[VSWAP]] offset:16 [M0] -; SI: S_ENDPGM +; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI-DAG: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7 +; SI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] +; SI-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]] +; SI: ds_cmpst_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[VCMP]], [[VSWAP]] offset:16 [M0] +; SI: s_endpgm define void @lds_atomic_cmpxchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %swap) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic @@ -18,17 +18,17 @@ define void @lds_atomic_cmpxchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrs } ; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i64_offset: -; SI: S_LOAD_DWORD [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI: S_LOAD_DWORDX2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI: S_MOV_B64 s{{\[}}[[LOSCMP:[0-9]+]]:[[HISCMP:[0-9]+]]{{\]}}, 7 -; SI-DAG: V_MOV_B32_e32 v[[LOVCMP:[0-9]+]], s[[LOSCMP]] -; SI-DAG: V_MOV_B32_e32 v[[HIVCMP:[0-9]+]], s[[HISCMP]] -; SI-DAG: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[PTR]] -; SI-DAG: V_MOV_B32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]] -; SI-DAG: V_MOV_B32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]] -; SI: DS_CMPST_RTN_B64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32 [M0] -; SI: BUFFER_STORE_DWORDX2 [[RESULT]], -; SI: S_ENDPGM +; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd +; SI: s_mov_b64 s{{\[}}[[LOSCMP:[0-9]+]]:[[HISCMP:[0-9]+]]{{\]}}, 7 +; SI-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], s[[LOSCMP]] +; SI-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], s[[HISCMP]] +; SI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] +; SI-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]] +; SI-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]] +; SI: ds_cmpst_rtn_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32 [M0] +; SI: buffer_store_dwordx2 [[RESULT]], +; SI: s_endpgm define void @lds_atomic_cmpxchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr, i64 %swap) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %pair = cmpxchg i64 addrspace(3)* %gep, i64 7, i64 %swap seq_cst monotonic @@ -38,9 +38,9 @@ define void @lds_atomic_cmpxchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrs } ; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_bad_si_offset -; SI: DS_CMPST_RTN_B32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} -; CI: DS_CMPST_RTN_B32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 [M0] -; SI: S_ENDPGM +; SI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; CI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 [M0] +; SI: s_endpgm define void @lds_atomic_cmpxchg_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %swap, i32 %a, i32 %b) nounwind { %sub = sub i32 %a, %b %add = add i32 %sub, 4 @@ -52,13 +52,13 @@ define void @lds_atomic_cmpxchg_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i3 } ; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_noret_i32_offset: -; SI: S_LOAD_DWORD [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9 -; SI: S_LOAD_DWORD [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xa -; SI-DAG: V_MOV_B32_e32 [[VCMP:v[0-9]+]], 7 -; SI-DAG: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[PTR]] -; SI-DAG: V_MOV_B32_e32 [[VSWAP:v[0-9]+]], [[SWAP]] -; SI: DS_CMPST_B32 [[VPTR]], [[VCMP]], [[VSWAP]] offset:16 [M0] -; SI: S_ENDPGM +; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9 +; SI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xa +; SI-DAG: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7 +; SI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] +; SI-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]] +; SI: ds_cmpst_b32 [[VPTR]], [[VCMP]], [[VSWAP]] offset:16 [M0] +; SI: s_endpgm define void @lds_atomic_cmpxchg_noret_i32_offset(i32 addrspace(3)* %ptr, i32 %swap) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic @@ -67,16 +67,16 @@ define void @lds_atomic_cmpxchg_noret_i32_offset(i32 addrspace(3)* %ptr, i32 %sw } ; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_noret_i64_offset: -; SI: S_LOAD_DWORD [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9 -; SI: S_LOAD_DWORDX2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI: S_MOV_B64 s{{\[}}[[LOSCMP:[0-9]+]]:[[HISCMP:[0-9]+]]{{\]}}, 7 -; SI-DAG: V_MOV_B32_e32 v[[LOVCMP:[0-9]+]], s[[LOSCMP]] -; SI-DAG: V_MOV_B32_e32 v[[HIVCMP:[0-9]+]], s[[HISCMP]] -; SI-DAG: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[PTR]] -; SI-DAG: V_MOV_B32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]] -; SI-DAG: V_MOV_B32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]] -; SI: DS_CMPST_B64 [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32 [M0] -; SI: S_ENDPGM +; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9 +; SI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI: s_mov_b64 s{{\[}}[[LOSCMP:[0-9]+]]:[[HISCMP:[0-9]+]]{{\]}}, 7 +; SI-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], s[[LOSCMP]] +; SI-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], s[[HISCMP]] +; SI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] +; SI-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]] +; SI-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]] +; SI: ds_cmpst_b64 [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32 [M0] +; SI: s_endpgm define void @lds_atomic_cmpxchg_noret_i64_offset(i64 addrspace(3)* %ptr, i64 %swap) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %pair = cmpxchg i64 addrspace(3)* %gep, i64 7, i64 %swap seq_cst monotonic diff --git a/test/CodeGen/R600/atomic_load_add.ll b/test/CodeGen/R600/atomic_load_add.ll index 7ce123ff71c..f0eff2157b9 100644 --- a/test/CodeGen/R600/atomic_load_add.ll +++ b/test/CodeGen/R600/atomic_load_add.ll @@ -3,7 +3,7 @@ ; FUNC-LABEL: {{^}}atomic_add_local: ; R600: LDS_ADD * -; SI: DS_ADD_U32 +; SI: ds_add_u32 define void @atomic_add_local(i32 addrspace(3)* %local) { %unused = atomicrmw volatile add i32 addrspace(3)* %local, i32 5 seq_cst ret void @@ -11,7 +11,7 @@ define void @atomic_add_local(i32 addrspace(3)* %local) { ; FUNC-LABEL: {{^}}atomic_add_local_const_offset: ; R600: LDS_ADD * -; SI: DS_ADD_U32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 define void @atomic_add_local_const_offset(i32 addrspace(3)* %local) { %gep = getelementptr i32 addrspace(3)* %local, i32 4 %val = atomicrmw volatile add i32 addrspace(3)* %gep, i32 5 seq_cst @@ -20,7 +20,7 @@ define void @atomic_add_local_const_offset(i32 addrspace(3)* %local) { ; FUNC-LABEL: {{^}}atomic_add_ret_local: ; R600: LDS_ADD_RET * -; SI: DS_ADD_RTN_U32 +; SI: ds_add_rtn_u32 define void @atomic_add_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %local) { %val = atomicrmw volatile add i32 addrspace(3)* %local, i32 5 seq_cst store i32 %val, i32 addrspace(1)* %out @@ -29,7 +29,7 @@ define void @atomic_add_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %loc ; FUNC-LABEL: {{^}}atomic_add_ret_local_const_offset: ; R600: LDS_ADD_RET * -; SI: DS_ADD_RTN_U32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:20 +; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:20 define void @atomic_add_ret_local_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %local) { %gep = getelementptr i32 addrspace(3)* %local, i32 5 %val = atomicrmw volatile add i32 addrspace(3)* %gep, i32 5 seq_cst diff --git a/test/CodeGen/R600/atomic_load_sub.ll b/test/CodeGen/R600/atomic_load_sub.ll index f1e975ddb34..61ff296308d 100644 --- a/test/CodeGen/R600/atomic_load_sub.ll +++ b/test/CodeGen/R600/atomic_load_sub.ll @@ -3,7 +3,7 @@ ; FUNC-LABEL: {{^}}atomic_sub_local: ; R600: LDS_SUB * -; SI: DS_SUB_U32 +; SI: ds_sub_u32 define void @atomic_sub_local(i32 addrspace(3)* %local) { %unused = atomicrmw volatile sub i32 addrspace(3)* %local, i32 5 seq_cst ret void @@ -11,7 +11,7 @@ define void @atomic_sub_local(i32 addrspace(3)* %local) { ; FUNC-LABEL: {{^}}atomic_sub_local_const_offset: ; R600: LDS_SUB * -; SI: DS_SUB_U32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: ds_sub_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 define void @atomic_sub_local_const_offset(i32 addrspace(3)* %local) { %gep = getelementptr i32 addrspace(3)* %local, i32 4 %val = atomicrmw volatile sub i32 addrspace(3)* %gep, i32 5 seq_cst @@ -20,7 +20,7 @@ define void @atomic_sub_local_const_offset(i32 addrspace(3)* %local) { ; FUNC-LABEL: {{^}}atomic_sub_ret_local: ; R600: LDS_SUB_RET * -; SI: DS_SUB_RTN_U32 +; SI: ds_sub_rtn_u32 define void @atomic_sub_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %local) { %val = atomicrmw volatile sub i32 addrspace(3)* %local, i32 5 seq_cst store i32 %val, i32 addrspace(1)* %out @@ -29,7 +29,7 @@ define void @atomic_sub_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %loc ; FUNC-LABEL: {{^}}atomic_sub_ret_local_const_offset: ; R600: LDS_SUB_RET * -; SI: DS_SUB_RTN_U32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:20 +; SI: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:20 define void @atomic_sub_ret_local_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %local) { %gep = getelementptr i32 addrspace(3)* %local, i32 5 %val = atomicrmw volatile sub i32 addrspace(3)* %gep, i32 5 seq_cst diff --git a/test/CodeGen/R600/bfi_int.ll b/test/CodeGen/R600/bfi_int.ll index 0514ae1da43..2a0bb375737 100644 --- a/test/CodeGen/R600/bfi_int.ll +++ b/test/CodeGen/R600/bfi_int.ll @@ -7,7 +7,7 @@ ; R600-CHECK: {{^}}bfi_def: ; R600-CHECK: BFI_INT ; SI-CHECK: @bfi_def -; SI-CHECK: V_BFI_B32 +; SI-CHECK: v_bfi_b32 define void @bfi_def(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) { entry: %0 = xor i32 %x, -1 @@ -23,7 +23,7 @@ entry: ; R600-CHECK: {{^}}bfi_sha256_ch: ; R600-CHECK: BFI_INT ; SI-CHECK: @bfi_sha256_ch -; SI-CHECK: V_BFI_B32 +; SI-CHECK: v_bfi_b32 define void @bfi_sha256_ch(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) { entry: %0 = xor i32 %y, %z @@ -38,8 +38,8 @@ entry: ; R600-CHECK: {{^}}bfi_sha256_ma: ; R600-CHECK: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], KC0[2].Z, KC0[2].W ; R600-CHECK: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, KC0[3].X, KC0[2].W -; SI-CHECK: V_XOR_B32_e32 [[DST:v[0-9]+]], {{s[0-9]+, v[0-9]+}} -; SI-CHECK: V_BFI_B32 {{v[0-9]+}}, [[DST]], {{s[0-9]+, v[0-9]+}} +; SI-CHECK: v_xor_b32_e32 [[DST:v[0-9]+]], {{s[0-9]+, v[0-9]+}} +; SI-CHECK: v_bfi_b32 {{v[0-9]+}}, [[DST]], {{s[0-9]+, v[0-9]+}} define void @bfi_sha256_ma(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) { entry: diff --git a/test/CodeGen/R600/bitcast.ll b/test/CodeGen/R600/bitcast.ll index cd1e719a4c1..725d5ba3727 100644 --- a/test/CodeGen/R600/bitcast.ll +++ b/test/CodeGen/R600/bitcast.ll @@ -5,7 +5,7 @@ declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) ; FUNC-LABEL: {{^}}v32i8_to_v8i32: -; SI: S_ENDPGM +; SI: s_endpgm define void @v32i8_to_v8i32(<32 x i8> addrspace(2)* inreg) #0 { entry: %1 = load <32 x i8> addrspace(2)* %0 @@ -18,7 +18,7 @@ entry: } ; FUNC-LABEL: {{^}}i8ptr_v16i8ptr: -; SI: S_ENDPGM +; SI: s_endpgm define void @i8ptr_v16i8ptr(<16 x i8> addrspace(1)* %out, i8 addrspace(1)* %in) { entry: %0 = bitcast i8 addrspace(1)* %in to <16 x i8> addrspace(1)* @@ -56,7 +56,7 @@ define void @i32_to_v4i8(<4 x i8> addrspace(1)* %out, i32 addrspace(1)* %in) nou } ; FUNC-LABEL: {{^}}bitcast_v2i32_to_f64: -; SI: S_ENDPGM +; SI: s_endpgm define void @bitcast_v2i32_to_f64(double addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %val = load <2 x i32> addrspace(1)* %in, align 8 %add = add <2 x i32> %val, @@ -66,7 +66,7 @@ define void @bitcast_v2i32_to_f64(double addrspace(1)* %out, <2 x i32> addrspace } ; FUNC-LABEL: {{^}}bitcast_f64_to_v2i32: -; SI: S_ENDPGM +; SI: s_endpgm define void @bitcast_f64_to_v2i32(<2 x i32> addrspace(1)* %out, double addrspace(1)* %in) { %val = load double addrspace(1)* %in, align 8 %add = fadd double %val, 4.0 diff --git a/test/CodeGen/R600/bswap.ll b/test/CodeGen/R600/bswap.ll index 002ac6504c6..1c5a0c6529f 100644 --- a/test/CodeGen/R600/bswap.ll +++ b/test/CodeGen/R600/bswap.ll @@ -9,13 +9,13 @@ declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>) nounwind readnone declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>) nounwind readnone ; FUNC-LABEL: @test_bswap_i32 -; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]] -; SI-DAG: V_ALIGNBIT_B32 [[TMP0:v[0-9]+]], [[VAL]], [[VAL]], 8 -; SI-DAG: V_ALIGNBIT_B32 [[TMP1:v[0-9]+]], [[VAL]], [[VAL]], 24 -; SI-DAG: S_MOV_B32 [[K:s[0-9]+]], 0xff00ff -; SI: V_BFI_B32 [[RESULT:v[0-9]+]], [[K]], [[TMP1]], [[TMP0]] -; SI: BUFFER_STORE_DWORD [[RESULT]] -; SI: S_ENDPGM +; SI: buffer_load_dword [[VAL:v[0-9]+]] +; SI-DAG: v_alignbit_b32 [[TMP0:v[0-9]+]], [[VAL]], [[VAL]], 8 +; SI-DAG: v_alignbit_b32 [[TMP1:v[0-9]+]], [[VAL]], [[VAL]], 24 +; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0xff00ff +; SI: v_bfi_b32 [[RESULT:v[0-9]+]], [[K]], [[TMP1]], [[TMP0]] +; SI: buffer_store_dword [[RESULT]] +; SI: s_endpgm define void @test_bswap_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %val = load i32 addrspace(1)* %in, align 4 %bswap = call i32 @llvm.bswap.i32(i32 %val) nounwind readnone @@ -24,13 +24,13 @@ define void @test_bswap_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: @test_bswap_v2i32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_BFI_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_BFI_B32 -; SI: S_ENDPGM +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_bfi_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_bfi_b32 +; SI: s_endpgm define void @test_bswap_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) nounwind { %val = load <2 x i32> addrspace(1)* %in, align 8 %bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %val) nounwind readnone @@ -39,19 +39,19 @@ define void @test_bswap_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace( } ; FUNC-LABEL: @test_bswap_v4i32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_BFI_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_BFI_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_BFI_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_BFI_B32 -; SI: S_ENDPGM +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_bfi_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_bfi_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_bfi_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_bfi_b32 +; SI: s_endpgm define void @test_bswap_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) nounwind { %val = load <4 x i32> addrspace(1)* %in, align 16 %bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val) nounwind readnone @@ -60,31 +60,31 @@ define void @test_bswap_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace( } ; FUNC-LABEL: @test_bswap_v8i32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_BFI_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_BFI_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_BFI_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_BFI_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_BFI_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_BFI_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_BFI_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_BFI_B32 -; SI: S_ENDPGM +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_bfi_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_bfi_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_bfi_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_bfi_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_bfi_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_bfi_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_bfi_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_bfi_b32 +; SI: s_endpgm define void @test_bswap_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) nounwind { %val = load <8 x i32> addrspace(1)* %in, align 32 %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %val) nounwind readnone diff --git a/test/CodeGen/R600/build_vector.ll b/test/CodeGen/R600/build_vector.ll index d1709187577..9137eee0e96 100644 --- a/test/CodeGen/R600/build_vector.ll +++ b/test/CodeGen/R600/build_vector.ll @@ -6,9 +6,9 @@ ; R600-CHECK: MOV ; R600-CHECK-NOT: MOV ; SI-CHECK: {{^}}build_vector2: -; SI-CHECK-DAG: V_MOV_B32_e32 v[[X:[0-9]]], 5 -; SI-CHECK-DAG: V_MOV_B32_e32 v[[Y:[0-9]]], 6 -; SI-CHECK: BUFFER_STORE_DWORDX2 v{{\[}}[[X]]:[[Y]]{{\]}} +; SI-CHECK-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5 +; SI-CHECK-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6 +; SI-CHECK: buffer_store_dwordx2 v{{\[}}[[X]]:[[Y]]{{\]}} define void @build_vector2 (<2 x i32> addrspace(1)* %out) { entry: store <2 x i32> , <2 x i32> addrspace(1)* %out @@ -22,11 +22,11 @@ entry: ; R600-CHECK: MOV ; R600-CHECK-NOT: MOV ; SI-CHECK: {{^}}build_vector4: -; SI-CHECK-DAG: V_MOV_B32_e32 v[[X:[0-9]]], 5 -; SI-CHECK-DAG: V_MOV_B32_e32 v[[Y:[0-9]]], 6 -; SI-CHECK-DAG: V_MOV_B32_e32 v[[Z:[0-9]]], 7 -; SI-CHECK-DAG: V_MOV_B32_e32 v[[W:[0-9]]], 8 -; SI-CHECK: BUFFER_STORE_DWORDX4 v{{\[}}[[X]]:[[W]]{{\]}} +; SI-CHECK-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5 +; SI-CHECK-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6 +; SI-CHECK-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7 +; SI-CHECK-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8 +; SI-CHECK: buffer_store_dwordx4 v{{\[}}[[X]]:[[W]]{{\]}} define void @build_vector4 (<4 x i32> addrspace(1)* %out) { entry: store <4 x i32> , <4 x i32> addrspace(1)* %out diff --git a/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll b/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll index 9c91d16dcb0..b42b904e53e 100644 --- a/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll +++ b/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll @@ -8,8 +8,8 @@ target triple = "r600--" ; OPT: mul nsw i32 ; OPT-NEXT: sext ; SI-LLC-LABEL: {{^}}test: -; SI-LLC: S_MUL_I32 -; SI-LLC-NOT: MUL +; SI-LLC: s_mul_i32 +; SI-LLC-NOT: mul define void @test(i8 addrspace(1)* nocapture readonly %in, i32 %a, i8 %b) { entry: %0 = mul nsw i32 %a, 3 diff --git a/test/CodeGen/R600/commute_modifiers.ll b/test/CodeGen/R600/commute_modifiers.ll index 97038f19003..2504688bbc4 100644 --- a/test/CodeGen/R600/commute_modifiers.ll +++ b/test/CodeGen/R600/commute_modifiers.ll @@ -4,9 +4,9 @@ declare i32 @llvm.r600.read.tidig.x() #1 declare float @llvm.fabs.f32(float) #1 ; FUNC-LABEL: @commute_add_imm_fabs_f32 -; SI: BUFFER_LOAD_DWORD [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; SI: V_ADD_F32_e64 [[REG:v[0-9]+]], 2.0, |[[X]]| -; SI-NEXT: BUFFER_STORE_DWORD [[REG]] +; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; SI: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, |[[X]]| +; SI-NEXT: buffer_store_dword [[REG]] define void @commute_add_imm_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { %tid = call i32 @llvm.r600.read.tidig.x() #1 %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid @@ -18,9 +18,9 @@ define void @commute_add_imm_fabs_f32(float addrspace(1)* %out, float addrspace( } ; FUNC-LABEL: @commute_mul_imm_fneg_fabs_f32 -; SI: BUFFER_LOAD_DWORD [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; SI: V_MUL_F32_e64 [[REG:v[0-9]+]], -4.0, |[[X]]| -; SI-NEXT: BUFFER_STORE_DWORD [[REG]] +; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; SI: v_mul_f32_e64 [[REG:v[0-9]+]], -4.0, |[[X]]| +; SI-NEXT: buffer_store_dword [[REG]] define void @commute_mul_imm_fneg_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { %tid = call i32 @llvm.r600.read.tidig.x() #1 %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid @@ -33,9 +33,9 @@ define void @commute_mul_imm_fneg_fabs_f32(float addrspace(1)* %out, float addrs } ; FUNC-LABEL: @commute_mul_imm_fneg_f32 -; SI: BUFFER_LOAD_DWORD [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; SI: V_MUL_F32_e32 [[REG:v[0-9]+]], -4.0, [[X]] -; SI-NEXT: BUFFER_STORE_DWORD [[REG]] +; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; SI: v_mul_f32_e32 [[REG:v[0-9]+]], -4.0, [[X]] +; SI-NEXT: buffer_store_dword [[REG]] define void @commute_mul_imm_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { %tid = call i32 @llvm.r600.read.tidig.x() #1 %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid diff --git a/test/CodeGen/R600/concat_vectors.ll b/test/CodeGen/R600/concat_vectors.ll index 8a17a04f3e0..19992ebde8c 100644 --- a/test/CodeGen/R600/concat_vectors.ll +++ b/test/CodeGen/R600/concat_vectors.ll @@ -5,8 +5,8 @@ ; instructions that access scratch memory. Bit 23, which is the add_tid_enable ; bit, is only set for scratch access, so we can check for the absence of this ; value if we want to ensure scratch memory is not being used. -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v1i32(<2 x i32> addrspace(1)* %out, <1 x i32> %a, <1 x i32> %b) nounwind { %concat = shufflevector <1 x i32> %a, <1 x i32> %b, <2 x i32> store <2 x i32> %concat, <2 x i32> addrspace(1)* %out, align 8 @@ -14,8 +14,8 @@ define void @test_concat_v1i32(<2 x i32> addrspace(1)* %out, <1 x i32> %a, <1 x } ; FUNC-LABEL: {{^}}test_concat_v2i32: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v2i32(<4 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind { %concat = shufflevector <2 x i32> %a, <2 x i32> %b, <4 x i32> store <4 x i32> %concat, <4 x i32> addrspace(1)* %out, align 16 @@ -23,8 +23,8 @@ define void @test_concat_v2i32(<4 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x } ; FUNC-LABEL: {{^}}test_concat_v4i32: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v4i32(<8 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) nounwind { %concat = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> store <8 x i32> %concat, <8 x i32> addrspace(1)* %out, align 32 @@ -32,8 +32,8 @@ define void @test_concat_v4i32(<8 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x } ; FUNC-LABEL: {{^}}test_concat_v8i32: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v8i32(<16 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) nounwind { %concat = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> store <16 x i32> %concat, <16 x i32> addrspace(1)* %out, align 64 @@ -41,8 +41,8 @@ define void @test_concat_v8i32(<16 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x } ; FUNC-LABEL: {{^}}test_concat_v16i32: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v16i32(<32 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) nounwind { %concat = shufflevector <16 x i32> %a, <16 x i32> %b, <32 x i32> store <32 x i32> %concat, <32 x i32> addrspace(1)* %out, align 128 @@ -50,8 +50,8 @@ define void @test_concat_v16i32(<32 x i32> addrspace(1)* %out, <16 x i32> %a, <1 } ; FUNC-LABEL: {{^}}test_concat_v1f32: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v1f32(<2 x float> addrspace(1)* %out, <1 x float> %a, <1 x float> %b) nounwind { %concat = shufflevector <1 x float> %a, <1 x float> %b, <2 x i32> store <2 x float> %concat, <2 x float> addrspace(1)* %out, align 8 @@ -59,8 +59,8 @@ define void @test_concat_v1f32(<2 x float> addrspace(1)* %out, <1 x float> %a, < } ; FUNC-LABEL: {{^}}test_concat_v2f32: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v2f32(<4 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) nounwind { %concat = shufflevector <2 x float> %a, <2 x float> %b, <4 x i32> store <4 x float> %concat, <4 x float> addrspace(1)* %out, align 16 @@ -68,8 +68,8 @@ define void @test_concat_v2f32(<4 x float> addrspace(1)* %out, <2 x float> %a, < } ; FUNC-LABEL: {{^}}test_concat_v4f32: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v4f32(<8 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) nounwind { %concat = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> store <8 x float> %concat, <8 x float> addrspace(1)* %out, align 32 @@ -77,8 +77,8 @@ define void @test_concat_v4f32(<8 x float> addrspace(1)* %out, <4 x float> %a, < } ; FUNC-LABEL: {{^}}test_concat_v8f32: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v8f32(<16 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) nounwind { %concat = shufflevector <8 x float> %a, <8 x float> %b, <16 x i32> store <16 x float> %concat, <16 x float> addrspace(1)* %out, align 64 @@ -86,8 +86,8 @@ define void @test_concat_v8f32(<16 x float> addrspace(1)* %out, <8 x float> %a, } ; FUNC-LABEL: {{^}}test_concat_v16f32: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v16f32(<32 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) nounwind { %concat = shufflevector <16 x float> %a, <16 x float> %b, <32 x i32> store <32 x float> %concat, <32 x float> addrspace(1)* %out, align 128 @@ -95,8 +95,8 @@ define void @test_concat_v16f32(<32 x float> addrspace(1)* %out, <16 x float> %a } ; FUNC-LABEL: {{^}}test_concat_v1i64: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v1i64(<2 x double> addrspace(1)* %out, <1 x double> %a, <1 x double> %b) nounwind { %concat = shufflevector <1 x double> %a, <1 x double> %b, <2 x i32> store <2 x double> %concat, <2 x double> addrspace(1)* %out, align 16 @@ -104,8 +104,8 @@ define void @test_concat_v1i64(<2 x double> addrspace(1)* %out, <1 x double> %a, } ; FUNC-LABEL: {{^}}test_concat_v2i64: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v2i64(<4 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b) nounwind { %concat = shufflevector <2 x double> %a, <2 x double> %b, <4 x i32> store <4 x double> %concat, <4 x double> addrspace(1)* %out, align 32 @@ -113,8 +113,8 @@ define void @test_concat_v2i64(<4 x double> addrspace(1)* %out, <2 x double> %a, } ; FUNC-LABEL: {{^}}test_concat_v4i64: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v4i64(<8 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b) nounwind { %concat = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> store <8 x double> %concat, <8 x double> addrspace(1)* %out, align 64 @@ -122,8 +122,8 @@ define void @test_concat_v4i64(<8 x double> addrspace(1)* %out, <4 x double> %a, } ; FUNC-LABEL: {{^}}test_concat_v8i64: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v8i64(<16 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b) nounwind { %concat = shufflevector <8 x double> %a, <8 x double> %b, <16 x i32> store <16 x double> %concat, <16 x double> addrspace(1)* %out, align 128 @@ -131,8 +131,8 @@ define void @test_concat_v8i64(<16 x double> addrspace(1)* %out, <8 x double> %a } ; FUNC-LABEL: {{^}}test_concat_v16i64: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v16i64(<32 x double> addrspace(1)* %out, <16 x double> %a, <16 x double> %b) nounwind { %concat = shufflevector <16 x double> %a, <16 x double> %b, <32 x i32> store <32 x double> %concat, <32 x double> addrspace(1)* %out, align 256 @@ -140,8 +140,8 @@ define void @test_concat_v16i64(<32 x double> addrspace(1)* %out, <16 x double> } ; FUNC-LABEL: {{^}}test_concat_v1f64: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v1f64(<2 x double> addrspace(1)* %out, <1 x double> %a, <1 x double> %b) nounwind { %concat = shufflevector <1 x double> %a, <1 x double> %b, <2 x i32> store <2 x double> %concat, <2 x double> addrspace(1)* %out, align 16 @@ -149,8 +149,8 @@ define void @test_concat_v1f64(<2 x double> addrspace(1)* %out, <1 x double> %a, } ; FUNC-LABEL: {{^}}test_concat_v2f64: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v2f64(<4 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b) nounwind { %concat = shufflevector <2 x double> %a, <2 x double> %b, <4 x i32> store <4 x double> %concat, <4 x double> addrspace(1)* %out, align 32 @@ -158,8 +158,8 @@ define void @test_concat_v2f64(<4 x double> addrspace(1)* %out, <2 x double> %a, } ; FUNC-LABEL: {{^}}test_concat_v4f64: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v4f64(<8 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b) nounwind { %concat = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> store <8 x double> %concat, <8 x double> addrspace(1)* %out, align 64 @@ -167,8 +167,8 @@ define void @test_concat_v4f64(<8 x double> addrspace(1)* %out, <4 x double> %a, } ; FUNC-LABEL: {{^}}test_concat_v8f64: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v8f64(<16 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b) nounwind { %concat = shufflevector <8 x double> %a, <8 x double> %b, <16 x i32> store <16 x double> %concat, <16 x double> addrspace(1)* %out, align 128 @@ -176,8 +176,8 @@ define void @test_concat_v8f64(<16 x double> addrspace(1)* %out, <8 x double> %a } ; FUNC-LABEL: {{^}}test_concat_v16f64: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v16f64(<32 x double> addrspace(1)* %out, <16 x double> %a, <16 x double> %b) nounwind { %concat = shufflevector <16 x double> %a, <16 x double> %b, <32 x i32> store <32 x double> %concat, <32 x double> addrspace(1)* %out, align 256 @@ -185,8 +185,8 @@ define void @test_concat_v16f64(<32 x double> addrspace(1)* %out, <16 x double> } ; FUNC-LABEL: {{^}}test_concat_v1i1: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v1i1(<2 x i1> addrspace(1)* %out, <1 x i1> %a, <1 x i1> %b) nounwind { %concat = shufflevector <1 x i1> %a, <1 x i1> %b, <2 x i32> store <2 x i1> %concat, <2 x i1> addrspace(1)* %out @@ -194,8 +194,8 @@ define void @test_concat_v1i1(<2 x i1> addrspace(1)* %out, <1 x i1> %a, <1 x i1> } ; FUNC-LABEL: {{^}}test_concat_v2i1: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v2i1(<4 x i1> addrspace(1)* %out, <2 x i1> %a, <2 x i1> %b) nounwind { %concat = shufflevector <2 x i1> %a, <2 x i1> %b, <4 x i32> store <4 x i1> %concat, <4 x i1> addrspace(1)* %out @@ -203,8 +203,8 @@ define void @test_concat_v2i1(<4 x i1> addrspace(1)* %out, <2 x i1> %a, <2 x i1> } ; FUNC-LABEL: {{^}}test_concat_v4i1: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v4i1(<8 x i1> addrspace(1)* %out, <4 x i1> %a, <4 x i1> %b) nounwind { %concat = shufflevector <4 x i1> %a, <4 x i1> %b, <8 x i32> store <8 x i1> %concat, <8 x i1> addrspace(1)* %out @@ -212,8 +212,8 @@ define void @test_concat_v4i1(<8 x i1> addrspace(1)* %out, <4 x i1> %a, <4 x i1> } ; FUNC-LABEL: {{^}}test_concat_v8i1: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v8i1(<16 x i1> addrspace(1)* %out, <8 x i1> %a, <8 x i1> %b) nounwind { %concat = shufflevector <8 x i1> %a, <8 x i1> %b, <16 x i32> store <16 x i1> %concat, <16 x i1> addrspace(1)* %out @@ -221,8 +221,8 @@ define void @test_concat_v8i1(<16 x i1> addrspace(1)* %out, <8 x i1> %a, <8 x i1 } ; FUNC-LABEL: {{^}}test_concat_v16i1: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v16i1(<32 x i1> addrspace(1)* %out, <16 x i1> %a, <16 x i1> %b) nounwind { %concat = shufflevector <16 x i1> %a, <16 x i1> %b, <32 x i32> store <32 x i1> %concat, <32 x i1> addrspace(1)* %out @@ -230,8 +230,8 @@ define void @test_concat_v16i1(<32 x i1> addrspace(1)* %out, <16 x i1> %a, <16 x } ; FUNC-LABEL: {{^}}test_concat_v32i1: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v32i1(<64 x i1> addrspace(1)* %out, <32 x i1> %a, <32 x i1> %b) nounwind { %concat = shufflevector <32 x i1> %a, <32 x i1> %b, <64 x i32> store <64 x i1> %concat, <64 x i1> addrspace(1)* %out @@ -239,8 +239,8 @@ define void @test_concat_v32i1(<64 x i1> addrspace(1)* %out, <32 x i1> %a, <32 x } ; FUNC-LABEL: {{^}}test_concat_v1i16: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v1i16(<2 x i16> addrspace(1)* %out, <1 x i16> %a, <1 x i16> %b) nounwind { %concat = shufflevector <1 x i16> %a, <1 x i16> %b, <2 x i32> store <2 x i16> %concat, <2 x i16> addrspace(1)* %out, align 4 @@ -248,8 +248,8 @@ define void @test_concat_v1i16(<2 x i16> addrspace(1)* %out, <1 x i16> %a, <1 x } ; FUNC-LABEL: {{^}}test_concat_v2i16: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v2i16(<4 x i16> addrspace(1)* %out, <2 x i16> %a, <2 x i16> %b) nounwind { %concat = shufflevector <2 x i16> %a, <2 x i16> %b, <4 x i32> store <4 x i16> %concat, <4 x i16> addrspace(1)* %out, align 8 @@ -257,8 +257,8 @@ define void @test_concat_v2i16(<4 x i16> addrspace(1)* %out, <2 x i16> %a, <2 x } ; FUNC-LABEL: {{^}}test_concat_v4i16: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v4i16(<8 x i16> addrspace(1)* %out, <4 x i16> %a, <4 x i16> %b) nounwind { %concat = shufflevector <4 x i16> %a, <4 x i16> %b, <8 x i32> store <8 x i16> %concat, <8 x i16> addrspace(1)* %out, align 16 @@ -266,8 +266,8 @@ define void @test_concat_v4i16(<8 x i16> addrspace(1)* %out, <4 x i16> %a, <4 x } ; FUNC-LABEL: {{^}}test_concat_v8i16: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v8i16(<16 x i16> addrspace(1)* %out, <8 x i16> %a, <8 x i16> %b) nounwind { %concat = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> store <16 x i16> %concat, <16 x i16> addrspace(1)* %out, align 32 @@ -275,8 +275,8 @@ define void @test_concat_v8i16(<16 x i16> addrspace(1)* %out, <8 x i16> %a, <8 x } ; FUNC-LABEL: {{^}}test_concat_v16i16: -; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000 -; SI-NOT: MOVREL +; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000 +; SI-NOT: movrel define void @test_concat_v16i16(<32 x i16> addrspace(1)* %out, <16 x i16> %a, <16 x i16> %b) nounwind { %concat = shufflevector <16 x i16> %a, <16 x i16> %b, <32 x i32> store <32 x i16> %concat, <32 x i16> addrspace(1)* %out, align 64 diff --git a/test/CodeGen/R600/copy-illegal-type.ll b/test/CodeGen/R600/copy-illegal-type.ll index 264a570c556..66ea88e2b0d 100644 --- a/test/CodeGen/R600/copy-illegal-type.ll +++ b/test/CodeGen/R600/copy-illegal-type.ll @@ -1,9 +1,9 @@ ; RUN: llc -march=r600 -mcpu=tahiti < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}test_copy_v4i8: -; SI: BUFFER_LOAD_DWORD [[REG:v[0-9]+]] -; SI: BUFFER_STORE_DWORD [[REG]] -; SI: S_ENDPGM +; SI: buffer_load_dword [[REG:v[0-9]+]] +; SI: buffer_store_dword [[REG]] +; SI: s_endpgm define void @test_copy_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind { %val = load <4 x i8> addrspace(1)* %in, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4 @@ -11,10 +11,10 @@ define void @test_copy_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* } ; FUNC-LABEL: {{^}}test_copy_v4i8_x2: -; SI: BUFFER_LOAD_DWORD [[REG:v[0-9]+]] -; SI: BUFFER_STORE_DWORD [[REG]] -; SI: BUFFER_STORE_DWORD [[REG]] -; SI: S_ENDPGM +; SI: buffer_load_dword [[REG:v[0-9]+]] +; SI: buffer_store_dword [[REG]] +; SI: buffer_store_dword [[REG]] +; SI: s_endpgm define void @test_copy_v4i8_x2(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %in) nounwind { %val = load <4 x i8> addrspace(1)* %in, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4 @@ -23,11 +23,11 @@ define void @test_copy_v4i8_x2(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace( } ; FUNC-LABEL: {{^}}test_copy_v4i8_x3: -; SI: BUFFER_LOAD_DWORD [[REG:v[0-9]+]] -; SI: BUFFER_STORE_DWORD [[REG]] -; SI: BUFFER_STORE_DWORD [[REG]] -; SI: BUFFER_STORE_DWORD [[REG]] -; SI: S_ENDPGM +; SI: buffer_load_dword [[REG:v[0-9]+]] +; SI: buffer_store_dword [[REG]] +; SI: buffer_store_dword [[REG]] +; SI: buffer_store_dword [[REG]] +; SI: s_endpgm define void @test_copy_v4i8_x3(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind { %val = load <4 x i8> addrspace(1)* %in, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4 @@ -37,12 +37,12 @@ define void @test_copy_v4i8_x3(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace( } ; FUNC-LABEL: {{^}}test_copy_v4i8_x4: -; SI: BUFFER_LOAD_DWORD [[REG:v[0-9]+]] -; SI: BUFFER_STORE_DWORD [[REG]] -; SI: BUFFER_STORE_DWORD [[REG]] -; SI: BUFFER_STORE_DWORD [[REG]] -; SI: BUFFER_STORE_DWORD [[REG]] -; SI: S_ENDPGM +; SI: buffer_load_dword [[REG:v[0-9]+]] +; SI: buffer_store_dword [[REG]] +; SI: buffer_store_dword [[REG]] +; SI: buffer_store_dword [[REG]] +; SI: buffer_store_dword [[REG]] +; SI: s_endpgm define void @test_copy_v4i8_x4(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %out3, <4 x i8> addrspace(1)* %in) nounwind { %val = load <4 x i8> addrspace(1)* %in, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4 @@ -53,33 +53,33 @@ define void @test_copy_v4i8_x4(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace( } ; FUNC-LABEL: {{^}}test_copy_v4i8_extra_use: -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_LOAD_UBYTE -; SI-DAG: V_ADD -; SI-DAG: V_ADD -; SI-DAG: V_ADD -; SI-DAG: V_ADD -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI_DAG: BUFFER_STORE_BYTE +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI-DAG: v_add +; SI-DAG: v_add +; SI-DAG: v_add +; SI-DAG: v_add +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_store_byte +; SI_DAG: buffer_store_byte ; After scalarizing v4i8 loads is fixed. -; XSI: BUFFER_LOAD_DWORD +; XSI: buffer_load_dword ; XSI: V_BFE ; XSI: V_ADD ; XSI: V_ADD ; XSI: V_ADD -; XSI: BUFFER_STORE_DWORD -; XSI: BUFFER_STORE_DWORD +; XSI: buffer_store_dword +; XSI: buffer_store_dword -; SI: S_ENDPGM +; SI: s_endpgm define void @test_copy_v4i8_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %in) nounwind { %val = load <4 x i8> addrspace(1)* %in, align 4 %add = add <4 x i8> %val, @@ -89,35 +89,35 @@ define void @test_copy_v4i8_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> add } ; FUNC-LABEL: {{^}}test_copy_v4i8_x2_extra_use: -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_LOAD_UBYTE -; SI-DAG: V_ADD -; SI-DAG: V_ADD -; SI-DAG: V_ADD -; SI-DAG: V_ADD -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI_DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI_DAG: BUFFER_STORE_BYTE +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI-DAG: v_add +; SI-DAG: v_add +; SI-DAG: v_add +; SI-DAG: v_add +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_store_byte +; SI_DAG: buffer_store_byte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_store_byte +; SI_DAG: buffer_store_byte -; XSI: BUFFER_LOAD_DWORD +; XSI: buffer_load_dword ; XSI: BFE -; XSI: BUFFER_STORE_DWORD +; XSI: buffer_store_dword ; XSI: V_ADD -; XSI: BUFFER_STORE_DWORD -; XSI-NEXT: BUFFER_STORE_DWORD +; XSI: buffer_store_dword +; XSI-NEXT: buffer_store_dword -; SI: S_ENDPGM +; SI: s_endpgm define void @test_copy_v4i8_x2_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind { %val = load <4 x i8> addrspace(1)* %in, align 4 %add = add <4 x i8> %val, @@ -128,9 +128,9 @@ define void @test_copy_v4i8_x2_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> } ; FUNC-LABEL: {{^}}test_copy_v3i8: -; SI-NOT: BFE -; SI-NOT: BFI -; SI: S_ENDPGM +; SI-NOT: bfe +; SI-NOT: bfi +; SI: s_endpgm define void @test_copy_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %in) nounwind { %val = load <3 x i8> addrspace(1)* %in, align 4 store <3 x i8> %val, <3 x i8> addrspace(1)* %out, align 4 @@ -138,11 +138,11 @@ define void @test_copy_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* } ; FUNC-LABEL: {{^}}test_copy_v4i8_volatile_load: -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_LOAD_UBYTE -; SI: S_ENDPGM +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: s_endpgm define void @test_copy_v4i8_volatile_load(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind { %val = load volatile <4 x i8> addrspace(1)* %in, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4 @@ -150,15 +150,15 @@ define void @test_copy_v4i8_volatile_load(<4 x i8> addrspace(1)* %out, <4 x i8> } ; FUNC-LABEL: {{^}}test_copy_v4i8_volatile_store: -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_STORE_BYTE -; SI: BUFFER_STORE_BYTE -; SI: BUFFER_STORE_BYTE -; SI: BUFFER_STORE_BYTE -; SI: S_ENDPGM +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_store_byte +; SI: buffer_store_byte +; SI: buffer_store_byte +; SI: buffer_store_byte +; SI: s_endpgm define void @test_copy_v4i8_volatile_store(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind { %val = load <4 x i8> addrspace(1)* %in, align 4 store volatile <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4 diff --git a/test/CodeGen/R600/ctlz_zero_undef.ll b/test/CodeGen/R600/ctlz_zero_undef.ll index c7f91650729..f699127fb60 100644 --- a/test/CodeGen/R600/ctlz_zero_undef.ll +++ b/test/CodeGen/R600/ctlz_zero_undef.ll @@ -6,11 +6,11 @@ declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone ; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i32: -; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], -; SI: S_FLBIT_I32_B32 [[SRESULT:s[0-9]+]], [[VAL]] -; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] -; SI: BUFFER_STORE_DWORD [[VRESULT]], -; SI: S_ENDPGM +; SI: s_load_dword [[VAL:s[0-9]+]], +; SI: s_flbit_i32_b32 [[SRESULT:s[0-9]+]], [[VAL]] +; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] +; SI: buffer_store_dword [[VRESULT]], +; SI: s_endpgm ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] ; EG: FFBH_UINT {{\*? *}}[[RESULT]] define void @s_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { @@ -20,10 +20,10 @@ define void @s_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nou } ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32: -; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]], -; SI: V_FFBH_U32_e32 [[RESULT:v[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: buffer_load_dword [[VAL:v[0-9]+]], +; SI: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] ; EG: FFBH_UINT {{\*? *}}[[RESULT]] define void @v_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { @@ -34,11 +34,11 @@ define void @v_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace } ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v2i32: -; SI: BUFFER_LOAD_DWORDX2 -; SI: V_FFBH_U32_e32 -; SI: V_FFBH_U32_e32 -; SI: BUFFER_STORE_DWORDX2 -; SI: S_ENDPGM +; SI: buffer_load_dwordx2 +; SI: v_ffbh_u32_e32 +; SI: v_ffbh_u32_e32 +; SI: buffer_store_dwordx2 +; SI: s_endpgm ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} ; EG: FFBH_UINT {{\*? *}}[[RESULT]] ; EG: FFBH_UINT {{\*? *}}[[RESULT]] @@ -50,13 +50,13 @@ define void @v_ctlz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x } ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v4i32: -; SI: BUFFER_LOAD_DWORDX4 -; SI: V_FFBH_U32_e32 -; SI: V_FFBH_U32_e32 -; SI: V_FFBH_U32_e32 -; SI: V_FFBH_U32_e32 -; SI: BUFFER_STORE_DWORDX4 -; SI: S_ENDPGM +; SI: buffer_load_dwordx4 +; SI: v_ffbh_u32_e32 +; SI: v_ffbh_u32_e32 +; SI: v_ffbh_u32_e32 +; SI: v_ffbh_u32_e32 +; SI: buffer_store_dwordx4 +; SI: s_endpgm ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} ; EG: FFBH_UINT {{\*? *}}[[RESULT]] ; EG: FFBH_UINT {{\*? *}}[[RESULT]] diff --git a/test/CodeGen/R600/ctpop.ll b/test/CodeGen/R600/ctpop.ll index 1e9a1553595..5cfdaefdfd0 100644 --- a/test/CodeGen/R600/ctpop.ll +++ b/test/CodeGen/R600/ctpop.ll @@ -8,11 +8,11 @@ declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>) nounwind readnone declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>) nounwind readnone ; FUNC-LABEL: {{^}}s_ctpop_i32: -; SI: S_LOAD_DWORD [[SVAL:s[0-9]+]], -; SI: S_BCNT1_I32_B32 [[SRESULT:s[0-9]+]], [[SVAL]] -; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] -; SI: BUFFER_STORE_DWORD [[VRESULT]], -; SI: S_ENDPGM +; SI: s_load_dword [[SVAL:s[0-9]+]], +; SI: s_bcnt1_i32_b32 [[SRESULT:s[0-9]+]], [[SVAL]] +; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] +; SI: buffer_store_dword [[VRESULT]], +; SI: s_endpgm ; EG: BCNT_INT define void @s_ctpop_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { @@ -23,11 +23,11 @@ define void @s_ctpop_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { ; XXX - Why 0 in register? ; FUNC-LABEL: {{^}}v_ctpop_i32: -; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]], -; SI: V_MOV_B32_e32 [[VZERO:v[0-9]+]], 0 -; SI: V_BCNT_U32_B32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[VZERO]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: buffer_load_dword [[VAL:v[0-9]+]], +; SI: v_mov_b32_e32 [[VZERO:v[0-9]+]], 0 +; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[VZERO]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm ; EG: BCNT_INT define void @v_ctpop_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { @@ -38,13 +38,13 @@ define void @v_ctpop_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noali } ; FUNC-LABEL: {{^}}v_ctpop_add_chain_i32: -; SI: BUFFER_LOAD_DWORD [[VAL0:v[0-9]+]], -; SI: BUFFER_LOAD_DWORD [[VAL1:v[0-9]+]], -; SI: V_MOV_B32_e32 [[VZERO:v[0-9]+]], 0 -; SI: V_BCNT_U32_B32_e32 [[MIDRESULT:v[0-9]+]], [[VAL1]], [[VZERO]] -; SI-NEXT: V_BCNT_U32_B32_e32 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: buffer_load_dword [[VAL0:v[0-9]+]], +; SI: buffer_load_dword [[VAL1:v[0-9]+]], +; SI: v_mov_b32_e32 [[VZERO:v[0-9]+]], 0 +; SI: v_bcnt_u32_b32_e32 [[MIDRESULT:v[0-9]+]], [[VAL1]], [[VZERO]] +; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm ; EG: BCNT_INT ; EG: BCNT_INT @@ -59,11 +59,11 @@ define void @v_ctpop_add_chain_i32(i32 addrspace(1)* noalias %out, i32 addrspace } ; FUNC-LABEL: {{^}}v_ctpop_add_sgpr_i32: -; SI: BUFFER_LOAD_DWORD [[VAL0:v[0-9]+]], -; SI-NEXT: S_WAITCNT -; SI-NEXT: V_BCNT_U32_B32_e64 [[RESULT:v[0-9]+]], [[VAL0]], s{{[0-9]+}} -; SI-NEXT: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: buffer_load_dword [[VAL0:v[0-9]+]], +; SI-NEXT: s_waitcnt +; SI-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], s{{[0-9]+}} +; SI-NEXT: buffer_store_dword [[RESULT]], +; SI: s_endpgm define void @v_ctpop_add_sgpr_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in0, i32 addrspace(1)* noalias %in1, i32 %sval) nounwind { %val0 = load i32 addrspace(1)* %in0, align 4 %ctpop0 = call i32 @llvm.ctpop.i32(i32 %val0) nounwind readnone @@ -73,9 +73,9 @@ define void @v_ctpop_add_sgpr_i32(i32 addrspace(1)* noalias %out, i32 addrspace( } ; FUNC-LABEL: {{^}}v_ctpop_v2i32: -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: S_ENDPGM +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: s_endpgm ; EG: BCNT_INT ; EG: BCNT_INT @@ -87,11 +87,11 @@ define void @v_ctpop_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrs } ; FUNC-LABEL: {{^}}v_ctpop_v4i32: -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: S_ENDPGM +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: s_endpgm ; EG: BCNT_INT ; EG: BCNT_INT @@ -105,15 +105,15 @@ define void @v_ctpop_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrs } ; FUNC-LABEL: {{^}}v_ctpop_v8i32: -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: S_ENDPGM +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: s_endpgm ; EG: BCNT_INT ; EG: BCNT_INT @@ -131,23 +131,23 @@ define void @v_ctpop_v8i32(<8 x i32> addrspace(1)* noalias %out, <8 x i32> addrs } ; FUNC-LABEL: {{^}}v_ctpop_v16i32: -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: V_BCNT_U32_B32_e32 -; SI: S_ENDPGM +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e32 +; SI: s_endpgm ; EG: BCNT_INT ; EG: BCNT_INT @@ -173,10 +173,10 @@ define void @v_ctpop_v16i32(<16 x i32> addrspace(1)* noalias %out, <16 x i32> ad } ; FUNC-LABEL: {{^}}v_ctpop_i32_add_inline_constant: -; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]], -; SI: V_BCNT_U32_B32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4 -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: buffer_load_dword [[VAL:v[0-9]+]], +; SI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4 +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm ; EG: BCNT_INT define void @v_ctpop_i32_add_inline_constant(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { @@ -188,10 +188,10 @@ define void @v_ctpop_i32_add_inline_constant(i32 addrspace(1)* noalias %out, i32 } ; FUNC-LABEL: {{^}}v_ctpop_i32_add_inline_constant_inv: -; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]], -; SI: V_BCNT_U32_B32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4 -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: buffer_load_dword [[VAL:v[0-9]+]], +; SI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4 +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm ; EG: BCNT_INT define void @v_ctpop_i32_add_inline_constant_inv(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { @@ -203,11 +203,11 @@ define void @v_ctpop_i32_add_inline_constant_inv(i32 addrspace(1)* noalias %out, } ; FUNC-LABEL: {{^}}v_ctpop_i32_add_literal: -; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]], -; SI: V_MOV_B32_e32 [[LIT:v[0-9]+]], 0x1869f -; SI: V_BCNT_U32_B32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[LIT]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: buffer_load_dword [[VAL:v[0-9]+]], +; SI: v_mov_b32_e32 [[LIT:v[0-9]+]], 0x1869f +; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[LIT]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm define void @v_ctpop_i32_add_literal(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { %val = load i32 addrspace(1)* %in, align 4 %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone @@ -217,11 +217,11 @@ define void @v_ctpop_i32_add_literal(i32 addrspace(1)* noalias %out, i32 addrspa } ; FUNC-LABEL: {{^}}v_ctpop_i32_add_var: -; SI-DAG: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]], -; SI-DAG: S_LOAD_DWORD [[VAR:s[0-9]+]], -; SI: V_BCNT_U32_B32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]], +; SI-DAG: s_load_dword [[VAR:s[0-9]+]], +; SI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm ; EG: BCNT_INT define void @v_ctpop_i32_add_var(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %const) nounwind { @@ -233,11 +233,11 @@ define void @v_ctpop_i32_add_var(i32 addrspace(1)* noalias %out, i32 addrspace(1 } ; FUNC-LABEL: {{^}}v_ctpop_i32_add_var_inv: -; SI-DAG: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]], -; SI-DAG: S_LOAD_DWORD [[VAR:s[0-9]+]], -; SI: V_BCNT_U32_B32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]], +; SI-DAG: s_load_dword [[VAR:s[0-9]+]], +; SI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm ; EG: BCNT_INT define void @v_ctpop_i32_add_var_inv(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %const) nounwind { @@ -249,11 +249,11 @@ define void @v_ctpop_i32_add_var_inv(i32 addrspace(1)* noalias %out, i32 addrspa } ; FUNC-LABEL: {{^}}v_ctpop_i32_add_vvar_inv: -; SI-DAG: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], {{0$}} -; SI-DAG: BUFFER_LOAD_DWORD [[VAR:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0 offset:0x10 -; SI: V_BCNT_U32_B32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], {{0$}} +; SI-DAG: buffer_load_dword [[VAR:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0 offset:0x10 +; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm ; EG: BCNT_INT define void @v_ctpop_i32_add_vvar_inv(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 addrspace(1)* noalias %constptr) nounwind { @@ -270,11 +270,11 @@ define void @v_ctpop_i32_add_vvar_inv(i32 addrspace(1)* noalias %out, i32 addrsp ; but there are some cases when the should be allowed. ; FUNC-LABEL: {{^}}ctpop_i32_in_br: -; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xd -; SI: S_BCNT1_I32_B32 [[SRESULT:s[0-9]+]], [[VAL]] -; SI: V_MOV_B32_e32 [[RESULT]], [[SRESULT]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xd +; SI: s_bcnt1_i32_b32 [[SRESULT:s[0-9]+]], [[VAL]] +; SI: v_mov_b32_e32 [[RESULT]], [[SRESULT]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm ; EG: BCNT_INT define void @ctpop_i32_in_br(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %ctpop_arg, i32 %cond) { entry: diff --git a/test/CodeGen/R600/ctpop64.ll b/test/CodeGen/R600/ctpop64.ll index 05f2ccc3991..2efac8f2067 100644 --- a/test/CodeGen/R600/ctpop64.ll +++ b/test/CodeGen/R600/ctpop64.ll @@ -7,11 +7,11 @@ declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>) nounwind readnone declare <16 x i64> @llvm.ctpop.v16i64(<16 x i64>) nounwind readnone ; FUNC-LABEL: {{^}}s_ctpop_i64: -; SI: S_LOAD_DWORDX2 [[SVAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI: S_BCNT1_I32_B64 [[SRESULT:s[0-9]+]], [[SVAL]] -; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] -; SI: BUFFER_STORE_DWORD [[VRESULT]], -; SI: S_ENDPGM +; SI: s_load_dwordx2 [[SVAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI: s_bcnt1_i32_b64 [[SRESULT:s[0-9]+]], [[SVAL]] +; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] +; SI: buffer_store_dword [[VRESULT]], +; SI: s_endpgm define void @s_ctpop_i64(i32 addrspace(1)* noalias %out, i64 %val) nounwind { %ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone %truncctpop = trunc i64 %ctpop to i32 @@ -20,12 +20,12 @@ define void @s_ctpop_i64(i32 addrspace(1)* noalias %out, i64 %val) nounwind { } ; FUNC-LABEL: {{^}}v_ctpop_i64: -; SI: BUFFER_LOAD_DWORDX2 v{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, -; SI: V_MOV_B32_e32 [[VZERO:v[0-9]+]], 0 -; SI: V_BCNT_U32_B32_e32 [[MIDRESULT:v[0-9]+]], v[[LOVAL]], [[VZERO]] -; SI-NEXT: V_BCNT_U32_B32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: buffer_load_dwordx2 v{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, +; SI: v_mov_b32_e32 [[VZERO:v[0-9]+]], 0 +; SI: v_bcnt_u32_b32_e32 [[MIDRESULT:v[0-9]+]], v[[LOVAL]], [[VZERO]] +; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm define void @v_ctpop_i64(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { %val = load i64 addrspace(1)* %in, align 8 %ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone @@ -35,9 +35,9 @@ define void @v_ctpop_i64(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noali } ; FUNC-LABEL: {{^}}s_ctpop_v2i64: -; SI: S_BCNT1_I32_B64 -; SI: S_BCNT1_I32_B64 -; SI: S_ENDPGM +; SI: s_bcnt1_i32_b64 +; SI: s_bcnt1_i32_b64 +; SI: s_endpgm define void @s_ctpop_v2i64(<2 x i32> addrspace(1)* noalias %out, <2 x i64> %val) nounwind { %ctpop = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %val) nounwind readnone %truncctpop = trunc <2 x i64> %ctpop to <2 x i32> @@ -46,11 +46,11 @@ define void @s_ctpop_v2i64(<2 x i32> addrspace(1)* noalias %out, <2 x i64> %val) } ; FUNC-LABEL: {{^}}s_ctpop_v4i64: -; SI: S_BCNT1_I32_B64 -; SI: S_BCNT1_I32_B64 -; SI: S_BCNT1_I32_B64 -; SI: S_BCNT1_I32_B64 -; SI: S_ENDPGM +; SI: s_bcnt1_i32_b64 +; SI: s_bcnt1_i32_b64 +; SI: s_bcnt1_i32_b64 +; SI: s_bcnt1_i32_b64 +; SI: s_endpgm define void @s_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> %val) nounwind { %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone %truncctpop = trunc <4 x i64> %ctpop to <4 x i32> @@ -59,11 +59,11 @@ define void @s_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> %val) } ; FUNC-LABEL: {{^}}v_ctpop_v2i64: -; SI: V_BCNT_U32_B32 -; SI: V_BCNT_U32_B32 -; SI: V_BCNT_U32_B32 -; SI: V_BCNT_U32_B32 -; SI: S_ENDPGM +; SI: v_bcnt_u32_b32 +; SI: v_bcnt_u32_b32 +; SI: v_bcnt_u32_b32 +; SI: v_bcnt_u32_b32 +; SI: s_endpgm define void @v_ctpop_v2i64(<2 x i32> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in) nounwind { %val = load <2 x i64> addrspace(1)* %in, align 16 %ctpop = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %val) nounwind readnone @@ -73,15 +73,15 @@ define void @v_ctpop_v2i64(<2 x i32> addrspace(1)* noalias %out, <2 x i64> addrs } ; FUNC-LABEL: {{^}}v_ctpop_v4i64: -; SI: V_BCNT_U32_B32 -; SI: V_BCNT_U32_B32 -; SI: V_BCNT_U32_B32 -; SI: V_BCNT_U32_B32 -; SI: V_BCNT_U32_B32 -; SI: V_BCNT_U32_B32 -; SI: V_BCNT_U32_B32 -; SI: V_BCNT_U32_B32 -; SI: S_ENDPGM +; SI: v_bcnt_u32_b32 +; SI: v_bcnt_u32_b32 +; SI: v_bcnt_u32_b32 +; SI: v_bcnt_u32_b32 +; SI: v_bcnt_u32_b32 +; SI: v_bcnt_u32_b32 +; SI: v_bcnt_u32_b32 +; SI: v_bcnt_u32_b32 +; SI: s_endpgm define void @v_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> addrspace(1)* noalias %in) nounwind { %val = load <4 x i64> addrspace(1)* %in, align 32 %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone @@ -94,12 +94,12 @@ define void @v_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> addrs ; but there are some cases when the should be allowed. ; FUNC-LABEL: {{^}}ctpop_i64_in_br: -; SI: S_LOAD_DWORDX2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xd -; SI: S_BCNT1_I32_B64 [[RESULT:s[0-9]+]], {{s\[}}[[LOVAL]]:[[HIVAL]]{{\]}} -; SI: V_MOV_B32_e32 v[[VLO:[0-9]+]], [[RESULT]] -; SI: V_MOV_B32_e32 v[[VHI:[0-9]+]], s[[HIVAL]] -; SI: BUFFER_STORE_DWORDX2 {{v\[}}[[VLO]]:[[VHI]]{{\]}} -; SI: S_ENDPGM +; SI: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xd +; SI: s_bcnt1_i32_b64 [[RESULT:s[0-9]+]], {{s\[}}[[LOVAL]]:[[HIVAL]]{{\]}} +; SI: v_mov_b32_e32 v[[VLO:[0-9]+]], [[RESULT]] +; SI: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[HIVAL]] +; SI: buffer_store_dwordx2 {{v\[}}[[VLO]]:[[VHI]]{{\]}} +; SI: s_endpgm define void @ctpop_i64_in_br(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %ctpop_arg, i32 %cond) { entry: %tmp0 = icmp eq i32 %cond, 0 diff --git a/test/CodeGen/R600/cttz_zero_undef.ll b/test/CodeGen/R600/cttz_zero_undef.ll index 6e96828866a..c4b1463160d 100644 --- a/test/CodeGen/R600/cttz_zero_undef.ll +++ b/test/CodeGen/R600/cttz_zero_undef.ll @@ -6,11 +6,11 @@ declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1) nounwind readnone declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1) nounwind readnone ; FUNC-LABEL: {{^}}s_cttz_zero_undef_i32: -; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], -; SI: S_FF1_I32_B32 [[SRESULT:s[0-9]+]], [[VAL]] -; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] -; SI: BUFFER_STORE_DWORD [[VRESULT]], -; SI: S_ENDPGM +; SI: s_load_dword [[VAL:s[0-9]+]], +; SI: s_ff1_i32_b32 [[SRESULT:s[0-9]+]], [[VAL]] +; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] +; SI: buffer_store_dword [[VRESULT]], +; SI: s_endpgm ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] ; EG: FFBL_INT {{\*? *}}[[RESULT]] define void @s_cttz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { @@ -20,10 +20,10 @@ define void @s_cttz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nou } ; FUNC-LABEL: {{^}}v_cttz_zero_undef_i32: -; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]], -; SI: V_FFBL_B32_e32 [[RESULT:v[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: buffer_load_dword [[VAL:v[0-9]+]], +; SI: v_ffbl_b32_e32 [[RESULT:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] ; EG: FFBL_INT {{\*? *}}[[RESULT]] define void @v_cttz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { @@ -34,11 +34,11 @@ define void @v_cttz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace } ; FUNC-LABEL: {{^}}v_cttz_zero_undef_v2i32: -; SI: BUFFER_LOAD_DWORDX2 -; SI: V_FFBL_B32_e32 -; SI: V_FFBL_B32_e32 -; SI: BUFFER_STORE_DWORDX2 -; SI: S_ENDPGM +; SI: buffer_load_dwordx2 +; SI: v_ffbl_b32_e32 +; SI: v_ffbl_b32_e32 +; SI: buffer_store_dwordx2 +; SI: s_endpgm ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} ; EG: FFBL_INT {{\*? *}}[[RESULT]] ; EG: FFBL_INT {{\*? *}}[[RESULT]] @@ -50,13 +50,13 @@ define void @v_cttz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x } ; FUNC-LABEL: {{^}}v_cttz_zero_undef_v4i32: -; SI: BUFFER_LOAD_DWORDX4 -; SI: V_FFBL_B32_e32 -; SI: V_FFBL_B32_e32 -; SI: V_FFBL_B32_e32 -; SI: V_FFBL_B32_e32 -; SI: BUFFER_STORE_DWORDX4 -; SI: S_ENDPGM +; SI: buffer_load_dwordx4 +; SI: v_ffbl_b32_e32 +; SI: v_ffbl_b32_e32 +; SI: v_ffbl_b32_e32 +; SI: v_ffbl_b32_e32 +; SI: buffer_store_dwordx4 +; SI: s_endpgm ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} ; EG: FFBL_INT {{\*? *}}[[RESULT]] ; EG: FFBL_INT {{\*? *}}[[RESULT]] diff --git a/test/CodeGen/R600/cvt_f32_ubyte.ll b/test/CodeGen/R600/cvt_f32_ubyte.ll index fa89f64d19e..0d1db1971b9 100644 --- a/test/CodeGen/R600/cvt_f32_ubyte.ll +++ b/test/CodeGen/R600/cvt_f32_ubyte.ll @@ -1,11 +1,11 @@ ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; SI-LABEL: {{^}}load_i8_to_f32: -; SI: BUFFER_LOAD_UBYTE [[LOADREG:v[0-9]+]], -; SI-NOT: BFE -; SI-NOT: LSHR -; SI: V_CVT_F32_UBYTE0_e32 [[CONV:v[0-9]+]], [[LOADREG]] -; SI: BUFFER_STORE_DWORD [[CONV]], +; SI: buffer_load_ubyte [[LOADREG:v[0-9]+]], +; SI-NOT: bfe +; SI-NOT: lshr +; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]] +; SI: buffer_store_dword [[CONV]], define void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind { %load = load i8 addrspace(1)* %in, align 1 %cvt = uitofp i8 %load to float @@ -14,13 +14,13 @@ define void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* n } ; SI-LABEL: {{^}}load_v2i8_to_v2f32: -; SI: BUFFER_LOAD_USHORT [[LOADREG:v[0-9]+]], -; SI-NOT: BFE -; SI-NOT: LSHR -; SI-NOT: AND -; SI-DAG: V_CVT_F32_UBYTE1_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]] -; SI-DAG: V_CVT_F32_UBYTE0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]] -; SI: BUFFER_STORE_DWORDX2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, +; SI: buffer_load_ushort [[LOADREG:v[0-9]+]], +; SI-NOT: bfe +; SI-NOT: lshr +; SI-NOT: and +; SI-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]] +; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]] +; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, define void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8> addrspace(1)* noalias %in) nounwind { %load = load <2 x i8> addrspace(1)* %in, align 1 %cvt = uitofp <2 x i8> %load to <2 x float> @@ -29,12 +29,12 @@ define void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8> } ; SI-LABEL: {{^}}load_v3i8_to_v3f32: -; SI-NOT: BFE -; SI-NOT: V_CVT_F32_UBYTE3_e32 -; SI-DAG: V_CVT_F32_UBYTE2_e32 -; SI-DAG: V_CVT_F32_UBYTE1_e32 -; SI-DAG: V_CVT_F32_UBYTE0_e32 -; SI: BUFFER_STORE_DWORDX2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, +; SI-NOT: bfe +; SI-NOT: v_cvt_f32_ubyte3_e32 +; SI-DAG: v_cvt_f32_ubyte2_e32 +; SI-DAG: v_cvt_f32_ubyte1_e32 +; SI-DAG: v_cvt_f32_ubyte0_e32 +; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, define void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8> addrspace(1)* noalias %in) nounwind { %load = load <3 x i8> addrspace(1)* %in, align 1 %cvt = uitofp <3 x i8> %load to <3 x float> @@ -43,18 +43,18 @@ define void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8> } ; SI-LABEL: {{^}}load_v4i8_to_v4f32: -; We can't use BUFFER_LOAD_DWORD here, because the load is byte aligned, and -; BUFFER_LOAD_DWORD requires dword alignment. -; SI: BUFFER_LOAD_USHORT -; SI: BUFFER_LOAD_USHORT -; SI: V_OR_B32_e32 [[LOADREG:v[0-9]+]] -; SI-NOT: BFE -; SI-NOT: LSHR -; SI-DAG: V_CVT_F32_UBYTE3_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]] -; SI-DAG: V_CVT_F32_UBYTE2_e32 v{{[0-9]+}}, [[LOADREG]] -; SI-DAG: V_CVT_F32_UBYTE1_e32 v{{[0-9]+}}, [[LOADREG]] -; SI-DAG: V_CVT_F32_UBYTE0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]] -; SI: BUFFER_STORE_DWORDX4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, +; We can't use buffer_load_dword here, because the load is byte aligned, and +; buffer_load_dword requires dword alignment. +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: v_or_b32_e32 [[LOADREG:v[0-9]+]] +; SI-NOT: bfe +; SI-NOT: lshr +; SI-DAG: v_cvt_f32_ubyte3_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]] +; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[LOADREG]] +; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, [[LOADREG]] +; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]] +; SI: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, define void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind { %load = load <4 x i8> addrspace(1)* %in, align 1 %cvt = uitofp <4 x i8> %load to <4 x float> @@ -62,27 +62,27 @@ define void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> ret void } -; XXX - This should really still be able to use the V_CVT_F32_UBYTE0 +; XXX - This should really still be able to use the v_cvt_f32_ubyte0 ; for each component, but computeKnownBits doesn't handle vectors very ; well. ; SI-LABEL: {{^}}load_v4i8_to_v4f32_2_uses: -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_LOAD_UBYTE -; SI: V_CVT_F32_UBYTE0_e32 -; SI: V_CVT_F32_UBYTE0_e32 -; SI: V_CVT_F32_UBYTE0_e32 -; SI: V_CVT_F32_UBYTE0_e32 +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: v_cvt_f32_ubyte0_e32 +; SI: v_cvt_f32_ubyte0_e32 +; SI: v_cvt_f32_ubyte0_e32 +; SI: v_cvt_f32_ubyte0_e32 ; XXX - replace with this when v4i8 loads aren't scalarized anymore. -; XSI: BUFFER_LOAD_DWORD -; XSI: V_CVT_F32_U32_e32 -; XSI: V_CVT_F32_U32_e32 -; XSI: V_CVT_F32_U32_e32 -; XSI: V_CVT_F32_U32_e32 -; SI: S_ENDPGM +; XSI: buffer_load_dword +; XSI: v_cvt_f32_u32_e32 +; XSI: v_cvt_f32_u32_e32 +; XSI: v_cvt_f32_u32_e32 +; XSI: v_cvt_f32_u32_e32 +; SI: s_endpgm define void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out2, <4 x i8> addrspace(1)* noalias %in) nounwind { %load = load <4 x i8> addrspace(1)* %in, align 4 %cvt = uitofp <4 x i8> %load to <4 x float> @@ -94,7 +94,7 @@ define void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, < ; Make sure this doesn't crash. ; SI-LABEL: {{^}}load_v7i8_to_v7f32: -; SI: S_ENDPGM +; SI: s_endpgm define void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> addrspace(1)* noalias %in) nounwind { %load = load <7 x i8> addrspace(1)* %in, align 1 %cvt = uitofp <7 x i8> %load to <7 x float> @@ -103,27 +103,27 @@ define void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> } ; SI-LABEL: {{^}}load_v8i8_to_v8f32: -; SI: BUFFER_LOAD_DWORDX2 v{{\[}}[[LOLOAD:[0-9]+]]:[[HILOAD:[0-9]+]]{{\]}}, -; SI-NOT: BFE -; SI-NOT: LSHR -; SI-DAG: V_CVT_F32_UBYTE3_e32 v{{[0-9]+}}, v[[LOLOAD]] -; SI-DAG: V_CVT_F32_UBYTE2_e32 v{{[0-9]+}}, v[[LOLOAD]] -; SI-DAG: V_CVT_F32_UBYTE1_e32 v{{[0-9]+}}, v[[LOLOAD]] -; SI-DAG: V_CVT_F32_UBYTE0_e32 v{{[0-9]+}}, v[[LOLOAD]] -; SI-DAG: V_CVT_F32_UBYTE3_e32 v{{[0-9]+}}, v[[HILOAD]] -; SI-DAG: V_CVT_F32_UBYTE2_e32 v{{[0-9]+}}, v[[HILOAD]] -; SI-DAG: V_CVT_F32_UBYTE1_e32 v{{[0-9]+}}, v[[HILOAD]] -; SI-DAG: V_CVT_F32_UBYTE0_e32 v{{[0-9]+}}, v[[HILOAD]] -; SI-NOT: BFE -; SI-NOT: LSHR -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD +; SI: buffer_load_dwordx2 v{{\[}}[[LOLOAD:[0-9]+]]:[[HILOAD:[0-9]+]]{{\]}}, +; SI-NOT: bfe +; SI-NOT: lshr +; SI-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[LOLOAD]] +; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[LOLOAD]] +; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[LOLOAD]] +; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[LOLOAD]] +; SI-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[HILOAD]] +; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[HILOAD]] +; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[HILOAD]] +; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[HILOAD]] +; SI-NOT: bfe +; SI-NOT: lshr +; SI: buffer_store_dword +; SI: buffer_store_dword +; SI: buffer_store_dword +; SI: buffer_store_dword +; SI: buffer_store_dword +; SI: buffer_store_dword +; SI: buffer_store_dword +; SI: buffer_store_dword define void @load_v8i8_to_v8f32(<8 x float> addrspace(1)* noalias %out, <8 x i8> addrspace(1)* noalias %in) nounwind { %load = load <8 x i8> addrspace(1)* %in, align 1 %cvt = uitofp <8 x i8> %load to <8 x float> @@ -132,10 +132,10 @@ define void @load_v8i8_to_v8f32(<8 x float> addrspace(1)* noalias %out, <8 x i8> } ; SI-LABEL: {{^}}i8_zext_inreg_i32_to_f32: -; SI: BUFFER_LOAD_DWORD [[LOADREG:v[0-9]+]], -; SI: V_ADD_I32_e32 [[ADD:v[0-9]+]], 2, [[LOADREG]] -; SI-NEXT: V_CVT_F32_UBYTE0_e32 [[CONV:v[0-9]+]], [[ADD]] -; SI: BUFFER_STORE_DWORD [[CONV]], +; SI: buffer_load_dword [[LOADREG:v[0-9]+]], +; SI: v_add_i32_e32 [[ADD:v[0-9]+]], 2, [[LOADREG]] +; SI-NEXT: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[ADD]] +; SI: buffer_store_dword [[CONV]], define void @i8_zext_inreg_i32_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { %load = load i32 addrspace(1)* %in, align 4 %add = add i32 %load, 2 diff --git a/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll b/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll index 628135ee4e5..f334062dbef 100644 --- a/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll +++ b/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll @@ -7,21 +7,21 @@ declare void @llvm.AMDGPU.barrier.local() #1 ; Function Attrs: nounwind ; CHECK-LABEL: {{^}}signed_ds_offset_addressing_loop: ; CHECK: BB0_1: -; CHECK: V_ADD_I32_e32 [[VADDR:v[0-9]+]], -; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]] -; SI-DAG: V_ADD_I32_e32 [[VADDR4:v[0-9]+]], 4, [[VADDR]] -; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR4]] -; SI-DAG: V_ADD_I32_e32 [[VADDR0x80:v[0-9]+]], 0x80, [[VADDR]] -; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR0x80]] -; SI-DAG: V_ADD_I32_e32 [[VADDR0x84:v[0-9]+]], 0x84, [[VADDR]] -; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR0x84]] -; SI-DAG: V_ADD_I32_e32 [[VADDR0x100:v[0-9]+]], 0x100, [[VADDR]] -; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR0x100]] +; CHECK: v_add_i32_e32 [[VADDR:v[0-9]+]], +; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]] +; SI-DAG: v_add_i32_e32 [[VADDR4:v[0-9]+]], 4, [[VADDR]] +; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR4]] +; SI-DAG: v_add_i32_e32 [[VADDR0x80:v[0-9]+]], 0x80, [[VADDR]] +; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x80]] +; SI-DAG: v_add_i32_e32 [[VADDR0x84:v[0-9]+]], 0x84, [[VADDR]] +; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x84]] +; SI-DAG: v_add_i32_e32 [[VADDR0x100:v[0-9]+]], 0x100, [[VADDR]] +; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x100]] -; CI-DAG: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:0 offset1:1 -; CI-DAG: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:32 offset1:33 -; CI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]] offset:256 -; CHECK: S_ENDPGM +; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:0 offset1:1 +; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:32 offset1:33 +; CI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]] offset:256 +; CHECK: s_endpgm define void @signed_ds_offset_addressing_loop(float addrspace(1)* noalias nocapture %out, float addrspace(3)* noalias nocapture readonly %lptr, i32 %n) #2 { entry: %x.i = tail call i32 @llvm.r600.read.tidig.x() #0 diff --git a/test/CodeGen/R600/ds_read2.ll b/test/CodeGen/R600/ds_read2.ll index 388d21ba08c..b431b5fe97c 100644 --- a/test/CodeGen/R600/ds_read2.ll +++ b/test/CodeGen/R600/ds_read2.ll @@ -7,11 +7,11 @@ @lds.f64 = addrspace(3) global [512 x double] zeroinitializer, align 8 ; SI-LABEL: @simple_read2_f32 -; SI: DS_READ2_B32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:0 offset1:8 -; SI: S_WAITCNT lgkmcnt(0) -; SI: V_ADD_F32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]] -; SI: BUFFER_STORE_DWORD [[RESULT]] -; SI: S_ENDPGM +; SI: ds_read2_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:0 offset1:8 +; SI: s_waitcnt lgkmcnt(0) +; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]] +; SI: buffer_store_dword [[RESULT]] +; SI: s_endpgm define void @simple_read2_f32(float addrspace(1)* %out) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i @@ -26,11 +26,11 @@ define void @simple_read2_f32(float addrspace(1)* %out) #0 { } ; SI-LABEL: @simple_read2_f32_max_offset -; SI: DS_READ2_B32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:0 offset1:255 -; SI: S_WAITCNT lgkmcnt(0) -; SI: V_ADD_F32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]] -; SI: BUFFER_STORE_DWORD [[RESULT]] -; SI: S_ENDPGM +; SI: ds_read2_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:0 offset1:255 +; SI: s_waitcnt lgkmcnt(0) +; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]] +; SI: buffer_store_dword [[RESULT]] +; SI: s_endpgm define void @simple_read2_f32_max_offset(float addrspace(1)* %out) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i @@ -45,10 +45,10 @@ define void @simple_read2_f32_max_offset(float addrspace(1)* %out) #0 { } ; SI-LABEL: @simple_read2_f32_too_far -; SI-NOT DS_READ2_B32 -; SI: DS_READ_B32 v{{[0-9]+}}, v{{[0-9]+}} -; SI: DS_READ_B32 v{{[0-9]+}}, v{{[0-9]+}} offset:1028 -; SI: S_ENDPGM +; SI-NOT ds_read2_b32 +; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} +; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:1028 +; SI: s_endpgm define void @simple_read2_f32_too_far(float addrspace(1)* %out) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i @@ -63,9 +63,9 @@ define void @simple_read2_f32_too_far(float addrspace(1)* %out) #0 { } ; SI-LABEL: @simple_read2_f32_x2 -; SI: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset0:0 offset1:8 -; SI: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27 -; SI: S_ENDPGM +; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset0:0 offset1:8 +; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27 +; SI: s_endpgm define void @simple_read2_f32_x2(float addrspace(1)* %out) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 0 @@ -94,10 +94,10 @@ define void @simple_read2_f32_x2(float addrspace(1)* %out) #0 { ; Make sure there is an instruction between the two sets of reads. ; SI-LABEL: @simple_read2_f32_x2_barrier -; SI: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset0:0 offset1:8 -; SI: S_BARRIER -; SI: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27 -; SI: S_ENDPGM +; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset0:0 offset1:8 +; SI: s_barrier +; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27 +; SI: s_endpgm define void @simple_read2_f32_x2_barrier(float addrspace(1)* %out) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 0 @@ -130,9 +130,9 @@ define void @simple_read2_f32_x2_barrier(float addrspace(1)* %out) #0 { ; element results in only folding the inner pair. ; SI-LABEL: @simple_read2_f32_x2_nonzero_base -; SI: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset0:2 offset1:8 -; SI: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27 -; SI: S_ENDPGM +; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset0:2 offset1:8 +; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27 +; SI: s_endpgm define void @simple_read2_f32_x2_nonzero_base(float addrspace(1)* %out) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 2 @@ -166,10 +166,10 @@ define void @simple_read2_f32_x2_nonzero_base(float addrspace(1)* %out) #0 { ; register. We can't safely merge this. ; SI-LABEL: @read2_ptr_is_subreg_arg_f32 -; SI-NOT: DS_READ2_B32 -; SI: DS_READ_B32 -; SI: DS_READ_B32 -; SI: S_ENDPGM +; SI-NOT: ds_read2_b32 +; SI: ds_read_b32 +; SI: ds_read_b32 +; SI: s_endpgm define void @read2_ptr_is_subreg_arg_f32(float addrspace(1)* %out, <2 x float addrspace(3)*> %lds.ptr) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %index.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0 @@ -192,10 +192,10 @@ define void @read2_ptr_is_subreg_arg_f32(float addrspace(1)* %out, <2 x float ad ; subregisters. ; SI-LABEL: @read2_ptr_is_subreg_arg_offset_f32 -; SI-NOT: DS_READ2_B32 -; SI: DS_READ_B32 -; SI: DS_READ_B32 -; SI: S_ENDPGM +; SI-NOT: ds_read2_b32 +; SI: ds_read_b32 +; SI: ds_read_b32 +; SI: s_endpgm define void @read2_ptr_is_subreg_arg_offset_f32(float addrspace(1)* %out, <2 x float addrspace(3)*> %lds.ptr) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %index.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0 @@ -217,10 +217,10 @@ define void @read2_ptr_is_subreg_arg_offset_f32(float addrspace(1)* %out, <2 x f } ; We should be able to merge in this case, but probably not worth the effort. -; SI-NOT: DS_READ2_B32 -; SI: DS_READ_B32 -; SI: DS_READ_B32 -; SI: S_ENDPGM +; SI-NOT: ds_read2_b32 +; SI: ds_read_b32 +; SI: ds_read_b32 +; SI: s_endpgm define void @read2_ptr_is_subreg_f32(float addrspace(1)* %out) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %ptr.0 = insertelement <2 x [512 x float] addrspace(3)*> undef, [512 x float] addrspace(3)* @lds, i32 0 @@ -241,10 +241,10 @@ define void @read2_ptr_is_subreg_f32(float addrspace(1)* %out) #0 { } ; SI-LABEL: @simple_read2_f32_volatile_0 -; SI-NOT DS_READ2_B32 -; SI: DS_READ_B32 v{{[0-9]+}}, v{{[0-9]+}} -; SI: DS_READ_B32 v{{[0-9]+}}, v{{[0-9]+}} offset:32 -; SI: S_ENDPGM +; SI-NOT ds_read2_b32 +; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} +; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:32 +; SI: s_endpgm define void @simple_read2_f32_volatile_0(float addrspace(1)* %out) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i @@ -259,10 +259,10 @@ define void @simple_read2_f32_volatile_0(float addrspace(1)* %out) #0 { } ; SI-LABEL: @simple_read2_f32_volatile_1 -; SI-NOT DS_READ2_B32 -; SI: DS_READ_B32 v{{[0-9]+}}, v{{[0-9]+}} -; SI: DS_READ_B32 v{{[0-9]+}}, v{{[0-9]+}} offset:32 -; SI: S_ENDPGM +; SI-NOT ds_read2_b32 +; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} +; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:32 +; SI: s_endpgm define void @simple_read2_f32_volatile_1(float addrspace(1)* %out) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i @@ -280,8 +280,8 @@ define void @simple_read2_f32_volatile_1(float addrspace(1)* %out) #0 { ; XXX: This isn't really testing anything useful now. I think CI ; allows unaligned LDS accesses, which would be a problem here. ; SI-LABEL: @unaligned_read2_f32 -; SI-NOT: DS_READ2_B32 -; SI: S_ENDPGM +; SI-NOT: ds_read2_b32 +; SI: s_endpgm define void @unaligned_read2_f32(float addrspace(1)* %out, float addrspace(3)* %lds) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %arrayidx0 = getelementptr inbounds float addrspace(3)* %lds, i32 %x.i @@ -296,8 +296,8 @@ define void @unaligned_read2_f32(float addrspace(1)* %out, float addrspace(3)* % } ; SI-LABEL: @misaligned_2_simple_read2_f32 -; SI-NOT: DS_READ2_B32 -; SI: S_ENDPGM +; SI-NOT: ds_read2_b32 +; SI: s_endpgm define void @misaligned_2_simple_read2_f32(float addrspace(1)* %out, float addrspace(3)* %lds) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %arrayidx0 = getelementptr inbounds float addrspace(3)* %lds, i32 %x.i @@ -312,11 +312,11 @@ define void @misaligned_2_simple_read2_f32(float addrspace(1)* %out, float addrs } ; SI-LABEL: @simple_read2_f64 -; SI: V_LSHLREV_B32_e32 [[VPTR:v[0-9]+]], 3, {{v[0-9]+}} -; SI: DS_READ2_B64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, [[VPTR]] offset0:0 offset1:8 -; SI: V_ADD_F64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}} -; SI: BUFFER_STORE_DWORDX2 [[RESULT]] -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, {{v[0-9]+}} +; SI: ds_read2_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, [[VPTR]] offset0:0 offset1:8 +; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}} +; SI: buffer_store_dwordx2 [[RESULT]] +; SI: s_endpgm define void @simple_read2_f64(double addrspace(1)* %out) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %arrayidx0 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i @@ -331,8 +331,8 @@ define void @simple_read2_f64(double addrspace(1)* %out) #0 { } ; SI-LABEL: @simple_read2_f64_max_offset -; SI: DS_READ2_B64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:0 offset1:255 -; SI: S_ENDPGM +; SI: ds_read2_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:0 offset1:255 +; SI: s_endpgm define void @simple_read2_f64_max_offset(double addrspace(1)* %out) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %arrayidx0 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i @@ -347,10 +347,10 @@ define void @simple_read2_f64_max_offset(double addrspace(1)* %out) #0 { } ; SI-LABEL: @simple_read2_f64_too_far -; SI-NOT DS_READ2_B64 -; SI: DS_READ_B64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} -; SI: DS_READ_B64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:2056 -; SI: S_ENDPGM +; SI-NOT ds_read2_b64 +; SI: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} +; SI: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:2056 +; SI: s_endpgm define void @simple_read2_f64_too_far(double addrspace(1)* %out) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %arrayidx0 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i @@ -366,9 +366,9 @@ define void @simple_read2_f64_too_far(double addrspace(1)* %out) #0 { ; Alignment only 4 ; SI-LABEL: @misaligned_read2_f64 -; SI: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:0 offset1:1 -; SI: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:14 offset1:15 -; SI: S_ENDPGM +; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:0 offset1:1 +; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:14 offset1:15 +; SI: s_endpgm define void @misaligned_read2_f64(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %x.i @@ -385,8 +385,8 @@ define void @misaligned_read2_f64(double addrspace(1)* %out, double addrspace(3) @foo = addrspace(3) global [4 x i32] zeroinitializer, align 4 ; SI-LABEL: @load_constant_adjacent_offsets -; SI: V_MOV_B32_e32 [[ZERO:v[0-9]+]], 0{{$}} -; SI: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset0:0 offset1:1 +; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}} +; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset0:0 offset1:1 define void @load_constant_adjacent_offsets(i32 addrspace(1)* %out) { %val0 = load i32 addrspace(3)* getelementptr inbounds ([4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4 %val1 = load i32 addrspace(3)* getelementptr inbounds ([4 x i32] addrspace(3)* @foo, i32 0, i32 1), align 4 @@ -396,8 +396,8 @@ define void @load_constant_adjacent_offsets(i32 addrspace(1)* %out) { } ; SI-LABEL: @load_constant_disjoint_offsets -; SI: V_MOV_B32_e32 [[ZERO:v[0-9]+]], 0{{$}} -; SI: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset0:0 offset1:2 +; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}} +; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset0:0 offset1:2 define void @load_constant_disjoint_offsets(i32 addrspace(1)* %out) { %val0 = load i32 addrspace(3)* getelementptr inbounds ([4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4 %val1 = load i32 addrspace(3)* getelementptr inbounds ([4 x i32] addrspace(3)* @foo, i32 0, i32 2), align 4 @@ -409,9 +409,9 @@ define void @load_constant_disjoint_offsets(i32 addrspace(1)* %out) { @bar = addrspace(3) global [4 x i64] zeroinitializer, align 4 ; SI-LABEL: @load_misaligned64_constant_offsets -; SI: V_MOV_B32_e32 [[ZERO:v[0-9]+]], 0{{$}} -; SI: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset0:0 offset1:1 -; SI: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset0:2 offset1:3 +; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}} +; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset0:0 offset1:1 +; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset0:2 offset1:3 define void @load_misaligned64_constant_offsets(i64 addrspace(1)* %out) { %val0 = load i64 addrspace(3)* getelementptr inbounds ([4 x i64] addrspace(3)* @bar, i32 0, i32 0), align 4 %val1 = load i64 addrspace(3)* getelementptr inbounds ([4 x i64] addrspace(3)* @bar, i32 0, i32 1), align 4 @@ -423,11 +423,11 @@ define void @load_misaligned64_constant_offsets(i64 addrspace(1)* %out) { @bar.large = addrspace(3) global [4096 x i64] zeroinitializer, align 4 ; SI-LABEL: @load_misaligned64_constant_large_offsets -; SI-DAG: V_MOV_B32_e32 [[BASE0:v[0-9]+]], 0x7ff8{{$}} -; SI-DAG: V_MOV_B32_e32 [[BASE1:v[0-9]+]], 0x4000 -; SI-DAG: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[BASE0]] offset0:0 offset1:1 -; SI-DAG: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[BASE1]] offset0:0 offset1:1 -; SI: S_ENDPGM +; SI-DAG: v_mov_b32_e32 [[BASE0:v[0-9]+]], 0x7ff8{{$}} +; SI-DAG: v_mov_b32_e32 [[BASE1:v[0-9]+]], 0x4000 +; SI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASE0]] offset0:0 offset1:1 +; SI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASE1]] offset0:0 offset1:1 +; SI: s_endpgm define void @load_misaligned64_constant_large_offsets(i64 addrspace(1)* %out) { %val0 = load i64 addrspace(3)* getelementptr inbounds ([4096 x i64] addrspace(3)* @bar.large, i32 0, i32 2048), align 4 %val1 = load i64 addrspace(3)* getelementptr inbounds ([4096 x i64] addrspace(3)* @bar.large, i32 0, i32 4095), align 4 diff --git a/test/CodeGen/R600/ds_read2st64.ll b/test/CodeGen/R600/ds_read2st64.ll index f30dc946b0c..cbb8da63935 100644 --- a/test/CodeGen/R600/ds_read2st64.ll +++ b/test/CodeGen/R600/ds_read2st64.ll @@ -5,11 +5,11 @@ ; SI-LABEL: @simple_read2st64_f32_0_1 -; SI: DS_READ2ST64_B32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:0 offset1:1 -; SI: S_WAITCNT lgkmcnt(0) -; SI: V_ADD_F32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]] -; SI: BUFFER_STORE_DWORD [[RESULT]] -; SI: S_ENDPGM +; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:0 offset1:1 +; SI: s_waitcnt lgkmcnt(0) +; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]] +; SI: buffer_store_dword [[RESULT]] +; SI: s_endpgm define void @simple_read2st64_f32_0_1(float addrspace(1)* %out) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i @@ -24,11 +24,11 @@ define void @simple_read2st64_f32_0_1(float addrspace(1)* %out) #0 { } ; SI-LABEL: @simple_read2st64_f32_1_2 -; SI: DS_READ2ST64_B32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:2 -; SI: S_WAITCNT lgkmcnt(0) -; SI: V_ADD_F32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]] -; SI: BUFFER_STORE_DWORD [[RESULT]] -; SI: S_ENDPGM +; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:2 +; SI: s_waitcnt lgkmcnt(0) +; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]] +; SI: buffer_store_dword [[RESULT]] +; SI: s_endpgm define void @simple_read2st64_f32_1_2(float addrspace(1)* %out, float addrspace(3)* %lds) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %add.x.0 = add nsw i32 %x.i, 64 @@ -44,11 +44,11 @@ define void @simple_read2st64_f32_1_2(float addrspace(1)* %out, float addrspace( } ; SI-LABEL: @simple_read2st64_f32_max_offset -; SI: DS_READ2ST64_B32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:255 -; SI: S_WAITCNT lgkmcnt(0) -; SI: V_ADD_F32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]] -; SI: BUFFER_STORE_DWORD [[RESULT]] -; SI: S_ENDPGM +; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:255 +; SI: s_waitcnt lgkmcnt(0) +; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]] +; SI: buffer_store_dword [[RESULT]] +; SI: s_endpgm define void @simple_read2st64_f32_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %add.x.0 = add nsw i32 %x.i, 64 @@ -64,11 +64,11 @@ define void @simple_read2st64_f32_max_offset(float addrspace(1)* %out, float add } ; SI-LABEL: @simple_read2st64_f32_over_max_offset -; SI-NOT: DS_READ2ST64_B32 -; SI: DS_READ_B32 {{v[0-9]+}}, {{v[0-9]+}} offset:256 -; SI: V_ADD_I32_e32 [[BIGADD:v[0-9]+]], 0x10000, {{v[0-9]+}} -; SI: DS_READ_B32 {{v[0-9]+}}, [[BIGADD]] -; SI: S_ENDPGM +; SI-NOT: ds_read2st64_b32 +; SI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:256 +; SI: v_add_i32_e32 [[BIGADD:v[0-9]+]], 0x10000, {{v[0-9]+}} +; SI: ds_read_b32 {{v[0-9]+}}, [[BIGADD]] +; SI: s_endpgm define void @simple_read2st64_f32_over_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %add.x.0 = add nsw i32 %x.i, 64 @@ -84,8 +84,8 @@ define void @simple_read2st64_f32_over_max_offset(float addrspace(1)* %out, floa } ; SI-LABEL: @odd_invalid_read2st64_f32_0 -; SI-NOT: DS_READ2ST64_B32 -; SI: S_ENDPGM +; SI-NOT: ds_read2st64_b32 +; SI: s_endpgm define void @odd_invalid_read2st64_f32_0(float addrspace(1)* %out) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i @@ -100,8 +100,8 @@ define void @odd_invalid_read2st64_f32_0(float addrspace(1)* %out) #0 { } ; SI-LABEL: @odd_invalid_read2st64_f32_1 -; SI-NOT: DS_READ2ST64_B32 -; SI: S_ENDPGM +; SI-NOT: ds_read2st64_b32 +; SI: s_endpgm define void @odd_invalid_read2st64_f32_1(float addrspace(1)* %out) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %add.x.0 = add nsw i32 %x.i, 64 @@ -117,11 +117,11 @@ define void @odd_invalid_read2st64_f32_1(float addrspace(1)* %out) #0 { } ; SI-LABEL: @simple_read2st64_f64_0_1 -; SI: DS_READ2ST64_B64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:0 offset1:1 -; SI: S_WAITCNT lgkmcnt(0) -; SI: V_ADD_F64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}} -; SI: BUFFER_STORE_DWORDX2 [[RESULT]] -; SI: S_ENDPGM +; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:0 offset1:1 +; SI: s_waitcnt lgkmcnt(0) +; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}} +; SI: buffer_store_dwordx2 [[RESULT]] +; SI: s_endpgm define void @simple_read2st64_f64_0_1(double addrspace(1)* %out) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %arrayidx0 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i @@ -136,11 +136,11 @@ define void @simple_read2st64_f64_0_1(double addrspace(1)* %out) #0 { } ; SI-LABEL: @simple_read2st64_f64_1_2 -; SI: DS_READ2ST64_B64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:2 -; SI: S_WAITCNT lgkmcnt(0) -; SI: V_ADD_F64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}} -; SI: BUFFER_STORE_DWORDX2 [[RESULT]] -; SI: S_ENDPGM +; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:2 +; SI: s_waitcnt lgkmcnt(0) +; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}} +; SI: buffer_store_dwordx2 [[RESULT]] +; SI: s_endpgm define void @simple_read2st64_f64_1_2(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %add.x.0 = add nsw i32 %x.i, 64 @@ -158,9 +158,9 @@ define void @simple_read2st64_f64_1_2(double addrspace(1)* %out, double addrspac ; Alignment only ; SI-LABEL: @misaligned_read2st64_f64 -; SI: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:0 offset1:1 -; SI: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:128 offset1:129 -; SI: S_ENDPGM +; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:0 offset1:1 +; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:128 offset1:129 +; SI: s_endpgm define void @misaligned_read2st64_f64(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %x.i @@ -176,11 +176,11 @@ define void @misaligned_read2st64_f64(double addrspace(1)* %out, double addrspac ; The maximum is not the usual 0xff because 0xff * 8 * 64 > 0xffff ; SI-LABEL: @simple_read2st64_f64_max_offset -; SI: DS_READ2ST64_B64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:4 offset1:127 -; SI: S_WAITCNT lgkmcnt(0) -; SI: V_ADD_F64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}} -; SI: BUFFER_STORE_DWORDX2 [[RESULT]] -; SI: S_ENDPGM +; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:4 offset1:127 +; SI: s_waitcnt lgkmcnt(0) +; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}} +; SI: buffer_store_dwordx2 [[RESULT]] +; SI: s_endpgm define void @simple_read2st64_f64_max_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %add.x.0 = add nsw i32 %x.i, 256 @@ -196,11 +196,11 @@ define void @simple_read2st64_f64_max_offset(double addrspace(1)* %out, double a } ; SI-LABEL: @simple_read2st64_f64_over_max_offset -; SI-NOT: DS_READ2ST64_B64 -; SI: DS_READ_B64 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset:512 -; SI: V_ADD_I32_e32 [[BIGADD:v[0-9]+]], 0x10000, {{v[0-9]+}} -; SI: DS_READ_B64 {{v\[[0-9]+:[0-9]+\]}}, [[BIGADD]] -; SI: S_ENDPGM +; SI-NOT: ds_read2st64_b64 +; SI: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset:512 +; SI: v_add_i32_e32 [[BIGADD:v[0-9]+]], 0x10000, {{v[0-9]+}} +; SI: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, [[BIGADD]] +; SI: s_endpgm define void @simple_read2st64_f64_over_max_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %add.x.0 = add nsw i32 %x.i, 64 @@ -216,8 +216,8 @@ define void @simple_read2st64_f64_over_max_offset(double addrspace(1)* %out, dou } ; SI-LABEL: @invalid_read2st64_f64_odd_offset -; SI-NOT: DS_READ2ST64_B64 -; SI: S_ENDPGM +; SI-NOT: ds_read2st64_b64 +; SI: s_endpgm define void @invalid_read2st64_f64_odd_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %add.x.0 = add nsw i32 %x.i, 64 @@ -236,9 +236,9 @@ define void @invalid_read2st64_f64_odd_offset(double addrspace(1)* %out, double ; stride in elements, not bytes, is a multiple of 64. ; SI-LABEL: @byte_size_only_divisible_64_read2_f64 -; SI-NOT: DS_READ2ST_B64 -; SI: DS_READ2_B64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:0 offset1:8 -; SI: S_ENDPGM +; SI-NOT: ds_read2st_b64 +; SI: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:0 offset1:8 +; SI: s_endpgm define void @byte_size_only_divisible_64_read2_f64(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %x.i diff --git a/test/CodeGen/R600/ds_write2.ll b/test/CodeGen/R600/ds_write2.ll index 99876f9ce07..678435e2f4d 100644 --- a/test/CodeGen/R600/ds_write2.ll +++ b/test/CodeGen/R600/ds_write2.ll @@ -5,10 +5,10 @@ ; SI-LABEL: @simple_write2_one_val_f32 -; SI-DAG: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]] -; SI-DAG: V_LSHLREV_B32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} -; SI: DS_WRITE2_B32 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:8 [M0] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]] +; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} +; SI: ds_write2_b32 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:8 [M0] +; SI: s_endpgm define void @simple_write2_one_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in.gep = getelementptr float addrspace(1)* %in, i32 %x.i @@ -22,11 +22,11 @@ define void @simple_write2_one_val_f32(float addrspace(1)* %C, float addrspace(1 } ; SI-LABEL: @simple_write2_two_val_f32 -; SI-DAG: BUFFER_LOAD_DWORD [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; SI-DAG: BUFFER_LOAD_DWORD [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 -; SI-DAG: V_LSHLREV_B32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} -; SI: DS_WRITE2_B32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:8 [M0] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 +; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} +; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:8 [M0] +; SI: s_endpgm define void @simple_write2_two_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in.gep.0 = getelementptr float addrspace(1)* %in, i32 %x.i @@ -42,10 +42,10 @@ define void @simple_write2_two_val_f32(float addrspace(1)* %C, float addrspace(1 } ; SI-LABEL: @simple_write2_two_val_f32_volatile_0 -; SI-NOT: DS_WRITE2_B32 -; SI: DS_WRITE_B32 {{v[0-9]+}}, {{v[0-9]+}} -; SI: DS_WRITE_B32 {{v[0-9]+}}, {{v[0-9]+}} offset:32 -; SI: S_ENDPGM +; SI-NOT: ds_write2_b32 +; SI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} +; SI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:32 +; SI: s_endpgm define void @simple_write2_two_val_f32_volatile_0(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in0.gep = getelementptr float addrspace(1)* %in0, i32 %x.i @@ -61,10 +61,10 @@ define void @simple_write2_two_val_f32_volatile_0(float addrspace(1)* %C, float } ; SI-LABEL: @simple_write2_two_val_f32_volatile_1 -; SI-NOT: DS_WRITE2_B32 -; SI: DS_WRITE_B32 {{v[0-9]+}}, {{v[0-9]+}} -; SI: DS_WRITE_B32 {{v[0-9]+}}, {{v[0-9]+}} offset:32 -; SI: S_ENDPGM +; SI-NOT: ds_write2_b32 +; SI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} +; SI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:32 +; SI: s_endpgm define void @simple_write2_two_val_f32_volatile_1(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in0.gep = getelementptr float addrspace(1)* %in0, i32 %x.i @@ -81,11 +81,11 @@ define void @simple_write2_two_val_f32_volatile_1(float addrspace(1)* %C, float ; 2 data subregisters from different super registers. ; SI-LABEL: @simple_write2_two_val_subreg2_mixed_f32 -; SI: BUFFER_LOAD_DWORDX2 v{{\[}}[[VAL0:[0-9]+]]:{{[0-9]+\]}} -; SI: BUFFER_LOAD_DWORDX2 v{{\[[0-9]+}}:[[VAL1:[0-9]+]]{{\]}} -; SI: V_LSHLREV_B32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} -; SI: DS_WRITE2_B32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8 [M0] -; SI: S_ENDPGM +; SI: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:{{[0-9]+\]}} +; SI: buffer_load_dwordx2 v{{\[[0-9]+}}:[[VAL1:[0-9]+]]{{\]}} +; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} +; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8 [M0] +; SI: s_endpgm define void @simple_write2_two_val_subreg2_mixed_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in.gep.0 = getelementptr <2 x float> addrspace(1)* %in, i32 %x.i @@ -103,10 +103,10 @@ define void @simple_write2_two_val_subreg2_mixed_f32(float addrspace(1)* %C, <2 } ; SI-LABEL: @simple_write2_two_val_subreg2_f32 -; SI-DAG: BUFFER_LOAD_DWORDX2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}} -; SI-DAG: V_LSHLREV_B32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} -; SI: DS_WRITE2_B32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8 [M0] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}} +; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} +; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8 [M0] +; SI: s_endpgm define void @simple_write2_two_val_subreg2_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in.gep = getelementptr <2 x float> addrspace(1)* %in, i32 %x.i @@ -122,10 +122,10 @@ define void @simple_write2_two_val_subreg2_f32(float addrspace(1)* %C, <2 x floa } ; SI-LABEL: @simple_write2_two_val_subreg4_f32 -; SI-DAG: BUFFER_LOAD_DWORDX4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}} -; SI-DAG: V_LSHLREV_B32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} -; SI: DS_WRITE2_B32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8 [M0] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}} +; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} +; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8 [M0] +; SI: s_endpgm define void @simple_write2_two_val_subreg4_f32(float addrspace(1)* %C, <4 x float> addrspace(1)* %in) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in.gep = getelementptr <4 x float> addrspace(1)* %in, i32 %x.i @@ -141,11 +141,11 @@ define void @simple_write2_two_val_subreg4_f32(float addrspace(1)* %C, <4 x floa } ; SI-LABEL: @simple_write2_two_val_max_offset_f32 -; SI-DAG: BUFFER_LOAD_DWORD [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; SI-DAG: BUFFER_LOAD_DWORD [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 -; SI-DAG: V_LSHLREV_B32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} -; SI: DS_WRITE2_B32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:255 [M0] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 +; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} +; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:255 [M0] +; SI: s_endpgm define void @simple_write2_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in.gep.0 = getelementptr float addrspace(1)* %in, i32 %x.i @@ -161,9 +161,9 @@ define void @simple_write2_two_val_max_offset_f32(float addrspace(1)* %C, float } ; SI-LABEL: @simple_write2_two_val_too_far_f32 -; SI: DS_WRITE_B32 v{{[0-9]+}}, v{{[0-9]+}} -; SI: DS_WRITE_B32 v{{[0-9]+}}, v{{[0-9]+}} offset:1028 -; SI: S_ENDPGM +; SI: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} +; SI: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:1028 +; SI: s_endpgm define void @simple_write2_two_val_too_far_f32(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in0.gep = getelementptr float addrspace(1)* %in0, i32 %x.i @@ -179,9 +179,9 @@ define void @simple_write2_two_val_too_far_f32(float addrspace(1)* %C, float add } ; SI-LABEL: @simple_write2_two_val_f32_x2 -; SI: DS_WRITE2_B32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL1:v[0-9]+]] offset0:0 offset1:8 -; SI-NEXT: DS_WRITE2_B32 [[BASEADDR]], [[VAL0]], [[VAL1]] offset0:11 offset1:27 -; SI: S_ENDPGM +; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL1:v[0-9]+]] offset0:0 offset1:8 +; SI-NEXT: ds_write2_b32 [[BASEADDR]], [[VAL0]], [[VAL1]] offset0:11 offset1:27 +; SI: s_endpgm define void @simple_write2_two_val_f32_x2(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %in0.gep = getelementptr float addrspace(1)* %in0, i32 %tid.x @@ -209,9 +209,9 @@ define void @simple_write2_two_val_f32_x2(float addrspace(1)* %C, float addrspac } ; SI-LABEL: @simple_write2_two_val_f32_x2_nonzero_base -; SI: DS_WRITE2_B32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL1:v[0-9]+]] offset0:3 offset1:8 -; SI-NEXT: DS_WRITE2_B32 [[BASEADDR]], [[VAL0]], [[VAL1]] offset0:11 offset1:27 -; SI: S_ENDPGM +; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL1:v[0-9]+]] offset0:3 offset1:8 +; SI-NEXT: ds_write2_b32 [[BASEADDR]], [[VAL0]], [[VAL1]] offset0:11 offset1:27 +; SI: s_endpgm define void @simple_write2_two_val_f32_x2_nonzero_base(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %in0.gep = getelementptr float addrspace(1)* %in0, i32 %tid.x @@ -239,10 +239,10 @@ define void @simple_write2_two_val_f32_x2_nonzero_base(float addrspace(1)* %C, f } ; SI-LABEL: @write2_ptr_subreg_arg_two_val_f32 -; SI-NOT: DS_WRITE2_B32 -; SI: DS_WRITE_B32 -; SI: DS_WRITE_B32 -; SI: S_ENDPGM +; SI-NOT: ds_write2_b32 +; SI: ds_write_b32 +; SI: ds_write_b32 +; SI: s_endpgm define void @write2_ptr_subreg_arg_two_val_f32(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1, <2 x float addrspace(3)*> %lds.ptr) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in0.gep = getelementptr float addrspace(1)* %in0, i32 %x.i @@ -266,10 +266,10 @@ define void @write2_ptr_subreg_arg_two_val_f32(float addrspace(1)* %C, float add } ; SI-LABEL: @simple_write2_one_val_f64 -; SI: BUFFER_LOAD_DWORDX2 [[VAL:v\[[0-9]+:[0-9]+\]]], -; SI: V_LSHLREV_B32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}} -; SI: DS_WRITE2_B64 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:8 [M0] -; SI: S_ENDPGM +; SI: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], +; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}} +; SI: ds_write2_b64 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:8 [M0] +; SI: s_endpgm define void @simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace(1)* %in) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in.gep = getelementptr double addrspace(1)* %in, i32 %x.i @@ -283,11 +283,11 @@ define void @simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace } ; SI-LABEL: @misaligned_simple_write2_one_val_f64 -; SI-DAG: BUFFER_LOAD_DWORDX2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}} -; SI-DAG: V_LSHLREV_B32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}} -; SI: DS_WRITE2_B32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:1 [M0] -; SI: DS_WRITE2_B32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:14 offset1:15 [M0] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}} +; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}} +; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:1 [M0] +; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:14 offset1:15 [M0] +; SI: s_endpgm define void @misaligned_simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in.gep = getelementptr double addrspace(1)* %in, i32 %x.i @@ -301,11 +301,11 @@ define void @misaligned_simple_write2_one_val_f64(double addrspace(1)* %C, doubl } ; SI-LABEL: @simple_write2_two_val_f64 -; SI-DAG: BUFFER_LOAD_DWORDX2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; SI-DAG: BUFFER_LOAD_DWORDX2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x8 -; SI-DAG: V_LSHLREV_B32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}} -; SI: DS_WRITE2_B64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:8 [M0] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; SI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x8 +; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}} +; SI: ds_write2_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:8 [M0] +; SI: s_endpgm define void @simple_write2_two_val_f64(double addrspace(1)* %C, double addrspace(1)* %in) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in.gep.0 = getelementptr double addrspace(1)* %in, i32 %x.i @@ -323,8 +323,8 @@ define void @simple_write2_two_val_f64(double addrspace(1)* %C, double addrspace @foo = addrspace(3) global [4 x i32] zeroinitializer, align 4 ; SI-LABEL: @store_constant_adjacent_offsets -; SI: V_MOV_B32_e32 [[ZERO:v[0-9]+]], 0{{$}} -; SI: DS_WRITE2_B32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset0:0 offset1:1 +; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}} +; SI: ds_write2_b32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset0:0 offset1:1 define void @store_constant_adjacent_offsets() { store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4 store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32] addrspace(3)* @foo, i32 0, i32 1), align 4 @@ -332,9 +332,9 @@ define void @store_constant_adjacent_offsets() { } ; SI-LABEL: @store_constant_disjoint_offsets -; SI-DAG: V_MOV_B32_e32 [[VAL:v[0-9]+]], 0x7b{{$}} -; SI-DAG: V_MOV_B32_e32 [[ZERO:v[0-9]+]], 0{{$}} -; SI: DS_WRITE2_B32 [[ZERO]], [[VAL]], [[VAL]] offset0:0 offset1:2 +; SI-DAG: v_mov_b32_e32 [[VAL:v[0-9]+]], 0x7b{{$}} +; SI-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}} +; SI: ds_write2_b32 [[ZERO]], [[VAL]], [[VAL]] offset0:0 offset1:2 define void @store_constant_disjoint_offsets() { store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4 store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32] addrspace(3)* @foo, i32 0, i32 2), align 4 @@ -344,9 +344,9 @@ define void @store_constant_disjoint_offsets() { @bar = addrspace(3) global [4 x i64] zeroinitializer, align 4 ; SI-LABEL: @store_misaligned64_constant_offsets -; SI: V_MOV_B32_e32 [[ZERO:v[0-9]+]], 0{{$}} -; SI: DS_WRITE2_B32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset0:0 offset1:1 -; SI: DS_WRITE2_B32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3 +; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}} +; SI: ds_write2_b32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset0:0 offset1:1 +; SI: ds_write2_b32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3 define void @store_misaligned64_constant_offsets() { store i64 123, i64 addrspace(3)* getelementptr inbounds ([4 x i64] addrspace(3)* @bar, i32 0, i32 0), align 4 store i64 123, i64 addrspace(3)* getelementptr inbounds ([4 x i64] addrspace(3)* @bar, i32 0, i32 1), align 4 @@ -356,11 +356,11 @@ define void @store_misaligned64_constant_offsets() { @bar.large = addrspace(3) global [4096 x i64] zeroinitializer, align 4 ; SI-LABEL: @store_misaligned64_constant_large_offsets -; SI-DAG: V_MOV_B32_e32 [[BASE0:v[0-9]+]], 0x7ff8{{$}} -; SI-DAG: V_MOV_B32_e32 [[BASE1:v[0-9]+]], 0x4000{{$}} -; SI-DAG: DS_WRITE2_B32 [[BASE0]], v{{[0-9]+}}, v{{[0-9]+}} offset0:0 offset1:1 -; SI-DAG: DS_WRITE2_B32 [[BASE1]], v{{[0-9]+}}, v{{[0-9]+}} offset0:0 offset1:1 -; SI: S_ENDPGM +; SI-DAG: v_mov_b32_e32 [[BASE0:v[0-9]+]], 0x7ff8{{$}} +; SI-DAG: v_mov_b32_e32 [[BASE1:v[0-9]+]], 0x4000{{$}} +; SI-DAG: ds_write2_b32 [[BASE0]], v{{[0-9]+}}, v{{[0-9]+}} offset0:0 offset1:1 +; SI-DAG: ds_write2_b32 [[BASE1]], v{{[0-9]+}}, v{{[0-9]+}} offset0:0 offset1:1 +; SI: s_endpgm define void @store_misaligned64_constant_large_offsets() { store i64 123, i64 addrspace(3)* getelementptr inbounds ([4096 x i64] addrspace(3)* @bar.large, i32 0, i32 2048), align 4 store i64 123, i64 addrspace(3)* getelementptr inbounds ([4096 x i64] addrspace(3)* @bar.large, i32 0, i32 4095), align 4 diff --git a/test/CodeGen/R600/ds_write2st64.ll b/test/CodeGen/R600/ds_write2st64.ll index 80b5c4b1ed5..a2dc09aec29 100644 --- a/test/CodeGen/R600/ds_write2st64.ll +++ b/test/CodeGen/R600/ds_write2st64.ll @@ -5,10 +5,10 @@ ; SI-LABEL: @simple_write2st64_one_val_f32_0_1 -; SI-DAG: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]] -; SI-DAG: V_LSHLREV_B32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} -; SI: DS_WRITE2ST64_B32 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:1 [M0] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]] +; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} +; SI: ds_write2st64_b32 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:1 [M0] +; SI: s_endpgm define void @simple_write2st64_one_val_f32_0_1(float addrspace(1)* %C, float addrspace(1)* %in) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in.gep = getelementptr float addrspace(1)* %in, i32 %x.i @@ -22,11 +22,11 @@ define void @simple_write2st64_one_val_f32_0_1(float addrspace(1)* %C, float add } ; SI-LABEL: @simple_write2st64_two_val_f32_2_5 -; SI-DAG: BUFFER_LOAD_DWORD [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; SI-DAG: BUFFER_LOAD_DWORD [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 -; SI-DAG: V_LSHLREV_B32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} -; SI: DS_WRITE2ST64_B32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5 [M0] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 +; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} +; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5 [M0] +; SI: s_endpgm define void @simple_write2st64_two_val_f32_2_5(float addrspace(1)* %C, float addrspace(1)* %in) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in.gep.0 = getelementptr float addrspace(1)* %in, i32 %x.i @@ -43,11 +43,11 @@ define void @simple_write2st64_two_val_f32_2_5(float addrspace(1)* %C, float add } ; SI-LABEL: @simple_write2st64_two_val_max_offset_f32 -; SI-DAG: BUFFER_LOAD_DWORD [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; SI-DAG: BUFFER_LOAD_DWORD [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 -; SI-DAG: V_LSHLREV_B32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} -; SI: DS_WRITE2ST64_B32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:255 [M0] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 +; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} +; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:255 [M0] +; SI: s_endpgm define void @simple_write2st64_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in, float addrspace(3)* %lds) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in.gep.0 = getelementptr float addrspace(1)* %in, i32 %x.i @@ -63,11 +63,11 @@ define void @simple_write2st64_two_val_max_offset_f32(float addrspace(1)* %C, fl } ; SI-LABEL: @simple_write2st64_two_val_max_offset_f64 -; SI-DAG: BUFFER_LOAD_DWORDX2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; SI-DAG: BUFFER_LOAD_DWORDX2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x8 -; SI-DAG: V_ADD_I32_e32 [[VPTR:v[0-9]+]], -; SI: DS_WRITE2ST64_B64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127 [M0] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; SI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x8 +; SI-DAG: v_add_i32_e32 [[VPTR:v[0-9]+]], +; SI: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127 [M0] +; SI: s_endpgm define void @simple_write2st64_two_val_max_offset_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in.gep.0 = getelementptr double addrspace(1)* %in, i32 %x.i @@ -84,9 +84,9 @@ define void @simple_write2st64_two_val_max_offset_f64(double addrspace(1)* %C, d } ; SI-LABEL: @byte_size_only_divisible_64_write2st64_f64 -; SI-NOT: DS_WRITE2ST64_B64 -; SI: DS_WRITE2_B64 {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:0 offset1:8 -; SI: S_ENDPGM +; SI-NOT: ds_write2st64_b64 +; SI: ds_write2_b64 {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:0 offset1:8 +; SI: s_endpgm define void @byte_size_only_divisible_64_write2st64_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 { %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 %in.gep = getelementptr double addrspace(1)* %in, i32 %x.i diff --git a/test/CodeGen/R600/extload.ll b/test/CodeGen/R600/extload.ll index c2c9e17dbda..5bda8f8fc7b 100644 --- a/test/CodeGen/R600/extload.ll +++ b/test/CodeGen/R600/extload.ll @@ -54,9 +54,9 @@ define void @anyext_load_lds_i16(i16 addrspace(3)* nocapture noalias %out, i16 a } ; FUNC-LABEL: {{^}}sextload_global_i8_to_i64: -; SI: BUFFER_LOAD_SBYTE [[LOAD:v[0-9]+]], -; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 31, [[LOAD]] -; SI: BUFFER_STORE_DWORDX2 +; SI: buffer_load_sbyte [[LOAD:v[0-9]+]], +; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[LOAD]] +; SI: buffer_store_dwordx2 define void @sextload_global_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind { %a = load i8 addrspace(1)* %in, align 8 %ext = sext i8 %a to i64 @@ -65,9 +65,9 @@ define void @sextload_global_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* } ; FUNC-LABEL: {{^}}sextload_global_i16_to_i64: -; SI: BUFFER_LOAD_SSHORT [[LOAD:v[0-9]+]], -; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 31, [[LOAD]] -; SI: BUFFER_STORE_DWORDX2 +; SI: buffer_load_sshort [[LOAD:v[0-9]+]], +; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[LOAD]] +; SI: buffer_store_dwordx2 define void @sextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind { %a = load i16 addrspace(1)* %in, align 8 %ext = sext i16 %a to i64 @@ -76,9 +76,9 @@ define void @sextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1) } ; FUNC-LABEL: {{^}}sextload_global_i32_to_i64: -; SI: BUFFER_LOAD_DWORD [[LOAD:v[0-9]+]], -; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 31, [[LOAD]] -; SI: BUFFER_STORE_DWORDX2 +; SI: buffer_load_dword [[LOAD:v[0-9]+]], +; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[LOAD]] +; SI: buffer_store_dwordx2 define void @sextload_global_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %a = load i32 addrspace(1)* %in, align 8 %ext = sext i32 %a to i64 @@ -87,10 +87,10 @@ define void @sextload_global_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1) } ; FUNC-LABEL: {{^}}zextload_global_i8_to_i64: -; SI-DAG: S_MOV_B32 [[ZERO:s[0-9]+]], 0{{$}} -; SI-DAG: BUFFER_LOAD_UBYTE [[LOAD:v[0-9]+]], -; SI: V_MOV_B32_e32 {{v[0-9]+}}, [[ZERO]] -; SI: BUFFER_STORE_DWORDX2 +; SI-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0{{$}} +; SI-DAG: buffer_load_ubyte [[LOAD:v[0-9]+]], +; SI: v_mov_b32_e32 {{v[0-9]+}}, [[ZERO]] +; SI: buffer_store_dwordx2 define void @zextload_global_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind { %a = load i8 addrspace(1)* %in, align 8 %ext = zext i8 %a to i64 @@ -99,10 +99,10 @@ define void @zextload_global_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* } ; FUNC-LABEL: {{^}}zextload_global_i16_to_i64: -; SI-DAG: S_MOV_B32 [[ZERO:s[0-9]+]], 0{{$}} -; SI-DAG: BUFFER_LOAD_USHORT [[LOAD:v[0-9]+]], -; SI: V_MOV_B32_e32 {{v[0-9]+}}, [[ZERO]] -; SI: BUFFER_STORE_DWORDX2 +; SI-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0{{$}} +; SI-DAG: buffer_load_ushort [[LOAD:v[0-9]+]], +; SI: v_mov_b32_e32 {{v[0-9]+}}, [[ZERO]] +; SI: buffer_store_dwordx2 define void @zextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind { %a = load i16 addrspace(1)* %in, align 8 %ext = zext i16 %a to i64 @@ -111,10 +111,10 @@ define void @zextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1) } ; FUNC-LABEL: {{^}}zextload_global_i32_to_i64: -; SI-DAG: S_MOV_B32 [[ZERO:s[0-9]+]], 0{{$}} -; SI-DAG: BUFFER_LOAD_DWORD [[LOAD:v[0-9]+]], -; SI: V_MOV_B32_e32 {{v[0-9]+}}, [[ZERO]] -; SI: BUFFER_STORE_DWORDX2 +; SI-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0{{$}} +; SI-DAG: buffer_load_dword [[LOAD:v[0-9]+]], +; SI: v_mov_b32_e32 {{v[0-9]+}}, [[ZERO]] +; SI: buffer_store_dwordx2 define void @zextload_global_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %a = load i32 addrspace(1)* %in, align 8 %ext = zext i32 %a to i64 diff --git a/test/CodeGen/R600/extract_vector_elt_i16.ll b/test/CodeGen/R600/extract_vector_elt_i16.ll index fcdd1bd5c0c..efdc1c8c738 100644 --- a/test/CodeGen/R600/extract_vector_elt_i16.ll +++ b/test/CodeGen/R600/extract_vector_elt_i16.ll @@ -1,10 +1,10 @@ ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}extract_vector_elt_v2i16: -; SI: BUFFER_LOAD_USHORT -; SI: BUFFER_LOAD_USHORT -; SI: BUFFER_STORE_SHORT -; SI: BUFFER_STORE_SHORT +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_store_short +; SI: buffer_store_short define void @extract_vector_elt_v2i16(i16 addrspace(1)* %out, <2 x i16> %foo) nounwind { %p0 = extractelement <2 x i16> %foo, i32 0 %p1 = extractelement <2 x i16> %foo, i32 1 @@ -15,10 +15,10 @@ define void @extract_vector_elt_v2i16(i16 addrspace(1)* %out, <2 x i16> %foo) no } ; FUNC-LABEL: {{^}}extract_vector_elt_v4i16: -; SI: BUFFER_LOAD_USHORT -; SI: BUFFER_LOAD_USHORT -; SI: BUFFER_STORE_SHORT -; SI: BUFFER_STORE_SHORT +; SI: buffer_load_ushort +; SI: buffer_load_ushort +; SI: buffer_store_short +; SI: buffer_store_short define void @extract_vector_elt_v4i16(i16 addrspace(1)* %out, <4 x i16> %foo) nounwind { %p0 = extractelement <4 x i16> %foo, i32 0 %p1 = extractelement <4 x i16> %foo, i32 2 diff --git a/test/CodeGen/R600/fabs.f64.ll b/test/CodeGen/R600/fabs.f64.ll index 72941b3a466..d2ba3206999 100644 --- a/test/CodeGen/R600/fabs.f64.ll +++ b/test/CodeGen/R600/fabs.f64.ll @@ -8,8 +8,8 @@ declare <2 x double> @llvm.fabs.v2f64(<2 x double>) readnone declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone ; FUNC-LABEL: {{^}}v_fabs_f64: -; SI: V_AND_B32 -; SI: S_ENDPGM +; SI: v_and_b32 +; SI: s_endpgm define void @v_fabs_f64(double addrspace(1)* %out, double addrspace(1)* %in) { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %tidext = sext i32 %tid to i64 @@ -21,9 +21,9 @@ define void @v_fabs_f64(double addrspace(1)* %out, double addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}fabs_f64: -; SI: V_AND_B32 -; SI-NOT: V_AND_B32 -; SI: S_ENDPGM +; SI: v_and_b32 +; SI-NOT: v_and_b32 +; SI: s_endpgm define void @fabs_f64(double addrspace(1)* %out, double %in) { %fabs = call double @llvm.fabs.f64(double %in) store double %fabs, double addrspace(1)* %out @@ -31,9 +31,9 @@ define void @fabs_f64(double addrspace(1)* %out, double %in) { } ; FUNC-LABEL: {{^}}fabs_v2f64: -; SI: V_AND_B32 -; SI: V_AND_B32 -; SI: S_ENDPGM +; SI: v_and_b32 +; SI: v_and_b32 +; SI: s_endpgm define void @fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) { %fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in) store <2 x double> %fabs, <2 x double> addrspace(1)* %out @@ -41,11 +41,11 @@ define void @fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) { } ; FUNC-LABEL: {{^}}fabs_v4f64: -; SI: V_AND_B32 -; SI: V_AND_B32 -; SI: V_AND_B32 -; SI: V_AND_B32 -; SI: S_ENDPGM +; SI: v_and_b32 +; SI: v_and_b32 +; SI: v_and_b32 +; SI: v_and_b32 +; SI: s_endpgm define void @fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) { %fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in) store <4 x double> %fabs, <4 x double> addrspace(1)* %out @@ -53,10 +53,10 @@ define void @fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) { } ; SI-LABEL: {{^}}fabs_fold_f64: -; SI: S_LOAD_DWORDX2 [[ABS_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb -; SI-NOT: AND -; SI: V_MUL_F64 {{v\[[0-9]+:[0-9]+\]}}, |[[ABS_VALUE]]|, {{v\[[0-9]+:[0-9]+\]}} -; SI: S_ENDPGM +; SI: s_load_dwordx2 [[ABS_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb +; SI-NOT: and +; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, |[[ABS_VALUE]]|, {{v\[[0-9]+:[0-9]+\]}} +; SI: s_endpgm define void @fabs_fold_f64(double addrspace(1)* %out, double %in0, double %in1) { %fabs = call double @llvm.fabs.f64(double %in0) %fmul = fmul double %fabs, %in1 @@ -65,10 +65,10 @@ define void @fabs_fold_f64(double addrspace(1)* %out, double %in0, double %in1) } ; SI-LABEL: {{^}}fabs_fn_fold_f64: -; SI: S_LOAD_DWORDX2 [[ABS_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb -; SI-NOT: AND -; SI: V_MUL_F64 {{v\[[0-9]+:[0-9]+\]}}, |[[ABS_VALUE]]|, {{v\[[0-9]+:[0-9]+\]}} -; SI: S_ENDPGM +; SI: s_load_dwordx2 [[ABS_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb +; SI-NOT: and +; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, |[[ABS_VALUE]]|, {{v\[[0-9]+:[0-9]+\]}} +; SI: s_endpgm define void @fabs_fn_fold_f64(double addrspace(1)* %out, double %in0, double %in1) { %fabs = call double @fabs(double %in0) %fmul = fmul double %fabs, %in1 @@ -77,8 +77,8 @@ define void @fabs_fn_fold_f64(double addrspace(1)* %out, double %in0, double %in } ; FUNC-LABEL: {{^}}fabs_free_f64: -; SI: V_AND_B32 -; SI: S_ENDPGM +; SI: v_and_b32 +; SI: s_endpgm define void @fabs_free_f64(double addrspace(1)* %out, i64 %in) { %bc= bitcast i64 %in to double %fabs = call double @llvm.fabs.f64(double %bc) @@ -87,8 +87,8 @@ define void @fabs_free_f64(double addrspace(1)* %out, i64 %in) { } ; FUNC-LABEL: {{^}}fabs_fn_free_f64: -; SI: V_AND_B32 -; SI: S_ENDPGM +; SI: v_and_b32 +; SI: s_endpgm define void @fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) { %bc= bitcast i64 %in to double %fabs = call double @fabs(double %bc) diff --git a/test/CodeGen/R600/fabs.ll b/test/CodeGen/R600/fabs.ll index b5bb92b2392..06cc97fb292 100644 --- a/test/CodeGen/R600/fabs.ll +++ b/test/CodeGen/R600/fabs.ll @@ -10,7 +10,7 @@ ; R600-NOT: AND ; R600: |PV.{{[XYZW]}}| -; SI: V_AND_B32 +; SI: v_and_b32 define void @fabs_fn_free(float addrspace(1)* %out, i32 %in) { %bc= bitcast i32 %in to float @@ -23,7 +23,7 @@ define void @fabs_fn_free(float addrspace(1)* %out, i32 %in) { ; R600-NOT: AND ; R600: |PV.{{[XYZW]}}| -; SI: V_AND_B32 +; SI: v_and_b32 define void @fabs_free(float addrspace(1)* %out, i32 %in) { %bc= bitcast i32 %in to float @@ -35,7 +35,7 @@ define void @fabs_free(float addrspace(1)* %out, i32 %in) { ; FUNC-LABEL: {{^}}fabs_f32: ; R600: |{{(PV|T[0-9])\.[XYZW]}}| -; SI: V_AND_B32 +; SI: v_and_b32 define void @fabs_f32(float addrspace(1)* %out, float %in) { %fabs = call float @llvm.fabs.f32(float %in) store float %fabs, float addrspace(1)* %out @@ -46,8 +46,8 @@ define void @fabs_f32(float addrspace(1)* %out, float %in) { ; R600: |{{(PV|T[0-9])\.[XYZW]}}| ; R600: |{{(PV|T[0-9])\.[XYZW]}}| -; SI: V_AND_B32 -; SI: V_AND_B32 +; SI: v_and_b32 +; SI: v_and_b32 define void @fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in) store <2 x float> %fabs, <2 x float> addrspace(1)* %out @@ -60,10 +60,10 @@ define void @fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { ; R600: |{{(PV|T[0-9])\.[XYZW]}}| ; R600: |{{(PV|T[0-9])\.[XYZW]}}| -; SI: V_AND_B32 -; SI: V_AND_B32 -; SI: V_AND_B32 -; SI: V_AND_B32 +; SI: v_and_b32 +; SI: v_and_b32 +; SI: v_and_b32 +; SI: v_and_b32 define void @fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in) store <4 x float> %fabs, <4 x float> addrspace(1)* %out @@ -71,9 +71,9 @@ define void @fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { } ; SI-LABEL: {{^}}fabs_fn_fold: -; SI: S_LOAD_DWORD [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb -; SI-NOT: AND -; SI: V_MUL_F32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}} +; SI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb +; SI-NOT: and +; SI: v_mul_f32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}} define void @fabs_fn_fold(float addrspace(1)* %out, float %in0, float %in1) { %fabs = call float @fabs(float %in0) %fmul = fmul float %fabs, %in1 @@ -82,9 +82,9 @@ define void @fabs_fn_fold(float addrspace(1)* %out, float %in0, float %in1) { } ; SI-LABEL: {{^}}fabs_fold: -; SI: S_LOAD_DWORD [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb -; SI-NOT: AND -; SI: V_MUL_F32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}} +; SI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb +; SI-NOT: and +; SI: v_mul_f32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}} define void @fabs_fold(float addrspace(1)* %out, float %in0, float %in1) { %fabs = call float @llvm.fabs.f32(float %in0) %fmul = fmul float %fabs, %in1 diff --git a/test/CodeGen/R600/fadd.ll b/test/CodeGen/R600/fadd.ll index 08f78909d02..774dd0b8baa 100644 --- a/test/CodeGen/R600/fadd.ll +++ b/test/CodeGen/R600/fadd.ll @@ -3,7 +3,7 @@ ; FUNC-LABEL: {{^}}fadd_f32: ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W -; SI: V_ADD_F32 +; SI: v_add_f32 define void @fadd_f32(float addrspace(1)* %out, float %a, float %b) { %add = fadd float %a, %b store float %add, float addrspace(1)* %out, align 4 @@ -13,8 +13,8 @@ define void @fadd_f32(float addrspace(1)* %out, float %a, float %b) { ; FUNC-LABEL: {{^}}fadd_v2f32: ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y -; SI: V_ADD_F32 -; SI: V_ADD_F32 +; SI: v_add_f32 +; SI: v_add_f32 define void @fadd_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { %add = fadd <2 x float> %a, %b store <2 x float> %add, <2 x float> addrspace(1)* %out, align 8 @@ -26,10 +26,10 @@ define void @fadd_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x flo ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; SI: V_ADD_F32 -; SI: V_ADD_F32 -; SI: V_ADD_F32 -; SI: V_ADD_F32 +; SI: v_add_f32 +; SI: v_add_f32 +; SI: v_add_f32 +; SI: v_add_f32 define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 %a = load <4 x float> addrspace(1)* %in, align 16 @@ -48,14 +48,14 @@ define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1) ; R600: ADD ; R600: ADD ; R600: ADD -; SI: V_ADD_F32 -; SI: V_ADD_F32 -; SI: V_ADD_F32 -; SI: V_ADD_F32 -; SI: V_ADD_F32 -; SI: V_ADD_F32 -; SI: V_ADD_F32 -; SI: V_ADD_F32 +; SI: v_add_f32 +; SI: v_add_f32 +; SI: v_add_f32 +; SI: v_add_f32 +; SI: v_add_f32 +; SI: v_add_f32 +; SI: v_add_f32 +; SI: v_add_f32 define void @fadd_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) { %add = fadd <8 x float> %a, %b store <8 x float> %add, <8 x float> addrspace(1)* %out, align 32 diff --git a/test/CodeGen/R600/fadd64.ll b/test/CodeGen/R600/fadd64.ll index 108264c4d55..3ca8500e9f8 100644 --- a/test/CodeGen/R600/fadd64.ll +++ b/test/CodeGen/R600/fadd64.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; CHECK: {{^}}fadd_f64: -; CHECK: V_ADD_F64 {{v[[0-9]+:[0-9]+]}}, {{v[[0-9]+:[0-9]+]}}, {{v[[0-9]+:[0-9]+]}} +; CHECK: v_add_f64 {{v[[0-9]+:[0-9]+]}}, {{v[[0-9]+:[0-9]+]}}, {{v[[0-9]+:[0-9]+]}} define void @fadd_f64(double addrspace(1)* %out, double addrspace(1)* %in1, double addrspace(1)* %in2) { diff --git a/test/CodeGen/R600/fceil.ll b/test/CodeGen/R600/fceil.ll index ef89eedf5cd..56dc796bab5 100644 --- a/test/CodeGen/R600/fceil.ll +++ b/test/CodeGen/R600/fceil.ll @@ -9,7 +9,7 @@ declare <8 x float> @llvm.ceil.v8f32(<8 x float>) nounwind readnone declare <16 x float> @llvm.ceil.v16f32(<16 x float>) nounwind readnone ; FUNC-LABEL: {{^}}fceil_f32: -; SI: V_CEIL_F32_e32 +; SI: v_ceil_f32_e32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] ; EG: CEIL {{\*? *}}[[RESULT]] define void @fceil_f32(float addrspace(1)* %out, float %x) { @@ -19,8 +19,8 @@ define void @fceil_f32(float addrspace(1)* %out, float %x) { } ; FUNC-LABEL: {{^}}fceil_v2f32: -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} ; EG: CEIL {{\*? *}}[[RESULT]] ; EG: CEIL {{\*? *}}[[RESULT]] @@ -31,9 +31,9 @@ define void @fceil_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %x) { } ; FUNC-LABEL: {{^}}fceil_v3f32: -; FIXME-SI: V_CEIL_F32_e32 -; FIXME-SI: V_CEIL_F32_e32 -; FIXME-SI: V_CEIL_F32_e32 +; FIXME-SI: v_ceil_f32_e32 +; FIXME-SI: v_ceil_f32_e32 +; FIXME-SI: v_ceil_f32_e32 ; FIXME-EG: v3 is treated as v2 and v1, hence 2 stores ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}} ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}} @@ -47,10 +47,10 @@ define void @fceil_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %x) { } ; FUNC-LABEL: {{^}}fceil_v4f32: -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} ; EG: CEIL {{\*? *}}[[RESULT]] ; EG: CEIL {{\*? *}}[[RESULT]] @@ -63,14 +63,14 @@ define void @fceil_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %x) { } ; FUNC-LABEL: {{^}}fceil_v8f32: -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}} ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}} ; EG-DAG: CEIL {{\*? *}}[[RESULT1]] @@ -88,22 +88,22 @@ define void @fceil_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %x) { } ; FUNC-LABEL: {{^}}fceil_v16f32: -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}} ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}} ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT3:T[0-9]+]]{{\.[XYZW]}} diff --git a/test/CodeGen/R600/fceil64.ll b/test/CodeGen/R600/fceil64.ll index ec565a91bda..029f41dc7ed 100644 --- a/test/CodeGen/R600/fceil64.ll +++ b/test/CodeGen/R600/fceil64.ll @@ -9,25 +9,25 @@ declare <8 x double> @llvm.ceil.v8f64(<8 x double>) nounwind readnone declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone ; FUNC-LABEL: {{^}}fceil_f64: -; CI: V_CEIL_F64_e32 -; SI: S_BFE_U32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014 -; SI: S_ADD_I32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01 -; SI: S_LSHR_B64 -; SI: S_NOT_B64 -; SI: S_AND_B64 -; SI-DAG: S_AND_B32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 -; SI-DAG: CMP_LT_I32 -; SI: CNDMASK_B32 -; SI: CNDMASK_B32 -; SI: CMP_GT_I32 -; SI: CNDMASK_B32 -; SI: CNDMASK_B32 -; SI: CMP_GT_F64 -; SI: CNDMASK_B32 -; SI: CMP_NE_I32 -; SI: CNDMASK_B32 -; SI: CNDMASK_B32 -; SI: V_ADD_F64 +; CI: v_ceil_f64_e32 +; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014 +; SI: s_add_i32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01 +; SI: s_lshr_b64 +; SI: s_not_b64 +; SI: s_and_b64 +; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 +; SI-DAG: cmp_lt_i32 +; SI: cndmask_b32 +; SI: cndmask_b32 +; SI: cmp_gt_i32 +; SI: cndmask_b32 +; SI: cndmask_b32 +; SI: cmp_gt_f64 +; SI: cndmask_b32 +; SI: cmp_ne_i32 +; SI: cndmask_b32 +; SI: cndmask_b32 +; SI: v_add_f64 define void @fceil_f64(double addrspace(1)* %out, double %x) { %y = call double @llvm.ceil.f64(double %x) nounwind readnone store double %y, double addrspace(1)* %out @@ -35,8 +35,8 @@ define void @fceil_f64(double addrspace(1)* %out, double %x) { } ; FUNC-LABEL: {{^}}fceil_v2f64: -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 define void @fceil_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) { %y = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x) nounwind readnone store <2 x double> %y, <2 x double> addrspace(1)* %out @@ -44,9 +44,9 @@ define void @fceil_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) { } ; FIXME-FUNC-LABEL: {{^}}fceil_v3f64: -; FIXME-CI: V_CEIL_F64_e32 -; FIXME-CI: V_CEIL_F64_e32 -; FIXME-CI: V_CEIL_F64_e32 +; FIXME-CI: v_ceil_f64_e32 +; FIXME-CI: v_ceil_f64_e32 +; FIXME-CI: v_ceil_f64_e32 ; define void @fceil_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) { ; %y = call <3 x double> @llvm.ceil.v3f64(<3 x double> %x) nounwind readnone ; store <3 x double> %y, <3 x double> addrspace(1)* %out @@ -54,10 +54,10 @@ define void @fceil_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) { ; } ; FUNC-LABEL: {{^}}fceil_v4f64: -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 define void @fceil_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) { %y = call <4 x double> @llvm.ceil.v4f64(<4 x double> %x) nounwind readnone store <4 x double> %y, <4 x double> addrspace(1)* %out @@ -65,14 +65,14 @@ define void @fceil_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) { } ; FUNC-LABEL: {{^}}fceil_v8f64: -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 define void @fceil_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) { %y = call <8 x double> @llvm.ceil.v8f64(<8 x double> %x) nounwind readnone store <8 x double> %y, <8 x double> addrspace(1)* %out @@ -80,22 +80,22 @@ define void @fceil_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) { } ; FUNC-LABEL: {{^}}fceil_v16f64: -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 -; CI: V_CEIL_F64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 +; CI: v_ceil_f64_e32 define void @fceil_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %x) { %y = call <16 x double> @llvm.ceil.v16f64(<16 x double> %x) nounwind readnone store <16 x double> %y, <16 x double> addrspace(1)* %out diff --git a/test/CodeGen/R600/fcmp64.ll b/test/CodeGen/R600/fcmp64.ll index dcb474087e0..3cf4a3b6889 100644 --- a/test/CodeGen/R600/fcmp64.ll +++ b/test/CodeGen/R600/fcmp64.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; CHECK: {{^}}flt_f64: -; CHECK: V_CMP_LT_F64_e64 {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} +; CHECK: v_cmp_lt_f64_e64 {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} define void @flt_f64(double addrspace(1)* %out, double addrspace(1)* %in1, double addrspace(1)* %in2) { @@ -14,7 +14,7 @@ define void @flt_f64(double addrspace(1)* %out, double addrspace(1)* %in1, } ; CHECK: {{^}}fle_f64: -; CHECK: V_CMP_LE_F64_e64 {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} +; CHECK: v_cmp_le_f64_e64 {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} define void @fle_f64(double addrspace(1)* %out, double addrspace(1)* %in1, double addrspace(1)* %in2) { @@ -27,7 +27,7 @@ define void @fle_f64(double addrspace(1)* %out, double addrspace(1)* %in1, } ; CHECK: {{^}}fgt_f64: -; CHECK: V_CMP_GT_F64_e64 {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} +; CHECK: v_cmp_gt_f64_e64 {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} define void @fgt_f64(double addrspace(1)* %out, double addrspace(1)* %in1, double addrspace(1)* %in2) { @@ -40,7 +40,7 @@ define void @fgt_f64(double addrspace(1)* %out, double addrspace(1)* %in1, } ; CHECK: {{^}}fge_f64: -; CHECK: V_CMP_GE_F64_e64 {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} +; CHECK: v_cmp_ge_f64_e64 {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} define void @fge_f64(double addrspace(1)* %out, double addrspace(1)* %in1, double addrspace(1)* %in2) { @@ -53,7 +53,7 @@ define void @fge_f64(double addrspace(1)* %out, double addrspace(1)* %in1, } ; CHECK: {{^}}fne_f64: -; CHECK: V_CMP_NEQ_F64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} +; CHECK: v_cmp_neq_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} define void @fne_f64(double addrspace(1)* %out, double addrspace(1)* %in1, double addrspace(1)* %in2) { @@ -66,7 +66,7 @@ define void @fne_f64(double addrspace(1)* %out, double addrspace(1)* %in1, } ; CHECK: {{^}}feq_f64: -; CHECK: V_CMP_EQ_F64_e64 {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} +; CHECK: v_cmp_eq_f64_e64 {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} define void @feq_f64(double addrspace(1)* %out, double addrspace(1)* %in1, double addrspace(1)* %in2) { diff --git a/test/CodeGen/R600/fconst64.ll b/test/CodeGen/R600/fconst64.ll index 0e23d492ab6..097c89f4a7c 100644 --- a/test/CodeGen/R600/fconst64.ll +++ b/test/CodeGen/R600/fconst64.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; CHECK: {{^}}fconst_f64: -; CHECK-DAG: S_MOV_B32 {{s[0-9]+}}, 0x40140000 -; CHECK-DAG: S_MOV_B32 {{s[0-9]+}}, 0 +; CHECK-DAG: s_mov_b32 {{s[0-9]+}}, 0x40140000 +; CHECK-DAG: s_mov_b32 {{s[0-9]+}}, 0 define void @fconst_f64(double addrspace(1)* %out, double addrspace(1)* %in) { %r1 = load double addrspace(1)* %in diff --git a/test/CodeGen/R600/fcopysign.f32.ll b/test/CodeGen/R600/fcopysign.f32.ll index 8c48272026f..897830eb70f 100644 --- a/test/CodeGen/R600/fcopysign.f32.ll +++ b/test/CodeGen/R600/fcopysign.f32.ll @@ -8,14 +8,14 @@ declare <4 x float> @llvm.copysign.v4f32(<4 x float>, <4 x float>) nounwind read ; Try to identify arg based on higher address. ; FUNC-LABEL: {{^}}test_copysign_f32: -; SI: S_LOAD_DWORD [[SMAG:s[0-9]+]], {{.*}} 0xb -; SI: S_LOAD_DWORD [[SSIGN:s[0-9]+]], {{.*}} 0xc -; SI-DAG: V_MOV_B32_e32 [[VSIGN:v[0-9]+]], [[SSIGN]] -; SI-DAG: V_MOV_B32_e32 [[VMAG:v[0-9]+]], [[SMAG]] -; SI-DAG: S_MOV_B32 [[SCONST:s[0-9]+]], 0x7fffffff -; SI: V_BFI_B32 [[RESULT:v[0-9]+]], [[SCONST]], [[VMAG]], [[VSIGN]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: s_load_dword [[SMAG:s[0-9]+]], {{.*}} 0xb +; SI: s_load_dword [[SSIGN:s[0-9]+]], {{.*}} 0xc +; SI-DAG: v_mov_b32_e32 [[VSIGN:v[0-9]+]], [[SSIGN]] +; SI-DAG: v_mov_b32_e32 [[VMAG:v[0-9]+]], [[SMAG]] +; SI-DAG: s_mov_b32 [[SCONST:s[0-9]+]], 0x7fffffff +; SI: v_bfi_b32 [[RESULT:v[0-9]+]], [[SCONST]], [[VMAG]], [[VSIGN]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm ; EG: BFI_INT define void @test_copysign_f32(float addrspace(1)* %out, float %mag, float %sign) nounwind { @@ -25,7 +25,7 @@ define void @test_copysign_f32(float addrspace(1)* %out, float %mag, float %sign } ; FUNC-LABEL: {{^}}test_copysign_v2f32: -; SI: S_ENDPGM +; SI: s_endpgm ; EG: BFI_INT ; EG: BFI_INT @@ -36,7 +36,7 @@ define void @test_copysign_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %ma } ; FUNC-LABEL: {{^}}test_copysign_v4f32: -; SI: S_ENDPGM +; SI: s_endpgm ; EG: BFI_INT ; EG: BFI_INT diff --git a/test/CodeGen/R600/fcopysign.f64.ll b/test/CodeGen/R600/fcopysign.f64.ll index c0150bc4101..90f0ce34650 100644 --- a/test/CodeGen/R600/fcopysign.f64.ll +++ b/test/CodeGen/R600/fcopysign.f64.ll @@ -5,15 +5,15 @@ declare <2 x double> @llvm.copysign.v2f64(<2 x double>, <2 x double>) nounwind r declare <4 x double> @llvm.copysign.v4f64(<4 x double>, <4 x double>) nounwind readnone ; FUNC-LABEL: {{^}}test_copysign_f64: -; SI-DAG: S_LOAD_DWORDX2 s{{\[}}[[SMAG_LO:[0-9]+]]:[[SMAG_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: S_LOAD_DWORDX2 s{{\[}}[[SSIGN_LO:[0-9]+]]:[[SSIGN_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: V_MOV_B32_e32 v[[VSIGN_HI:[0-9]+]], s[[SSIGN_HI]] -; SI-DAG: V_MOV_B32_e32 v[[VMAG_HI:[0-9]+]], s[[SMAG_HI]] -; SI-DAG: S_MOV_B32 [[SCONST:s[0-9]+]], 0x7fffffff -; SI: V_BFI_B32 v[[VRESULT_HI:[0-9]+]], [[SCONST]], v[[VMAG_HI]], v[[VSIGN_HI]] -; SI: V_MOV_B32_e32 v[[VMAG_LO:[0-9]+]], s[[SMAG_LO]] -; SI: BUFFER_STORE_DWORDX2 v{{\[}}[[VMAG_LO]]:[[VRESULT_HI]]{{\]}} -; SI: S_ENDPGM +; SI-DAG: s_load_dwordx2 s{{\[}}[[SMAG_LO:[0-9]+]]:[[SMAG_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dwordx2 s{{\[}}[[SSIGN_LO:[0-9]+]]:[[SSIGN_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: v_mov_b32_e32 v[[VSIGN_HI:[0-9]+]], s[[SSIGN_HI]] +; SI-DAG: v_mov_b32_e32 v[[VMAG_HI:[0-9]+]], s[[SMAG_HI]] +; SI-DAG: s_mov_b32 [[SCONST:s[0-9]+]], 0x7fffffff +; SI: v_bfi_b32 v[[VRESULT_HI:[0-9]+]], [[SCONST]], v[[VMAG_HI]], v[[VSIGN_HI]] +; SI: v_mov_b32_e32 v[[VMAG_LO:[0-9]+]], s[[SMAG_LO]] +; SI: buffer_store_dwordx2 v{{\[}}[[VMAG_LO]]:[[VRESULT_HI]]{{\]}} +; SI: s_endpgm define void @test_copysign_f64(double addrspace(1)* %out, double %mag, double %sign) nounwind { %result = call double @llvm.copysign.f64(double %mag, double %sign) store double %result, double addrspace(1)* %out, align 8 @@ -21,7 +21,7 @@ define void @test_copysign_f64(double addrspace(1)* %out, double %mag, double %s } ; FUNC-LABEL: {{^}}test_copysign_v2f64: -; SI: S_ENDPGM +; SI: s_endpgm define void @test_copysign_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %mag, <2 x double> %sign) nounwind { %result = call <2 x double> @llvm.copysign.v2f64(<2 x double> %mag, <2 x double> %sign) store <2 x double> %result, <2 x double> addrspace(1)* %out, align 8 @@ -29,7 +29,7 @@ define void @test_copysign_v2f64(<2 x double> addrspace(1)* %out, <2 x double> % } ; FUNC-LABEL: {{^}}test_copysign_v4f64: -; SI: S_ENDPGM +; SI: s_endpgm define void @test_copysign_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %mag, <4 x double> %sign) nounwind { %result = call <4 x double> @llvm.copysign.v4f64(<4 x double> %mag, <4 x double> %sign) store <4 x double> %result, <4 x double> addrspace(1)* %out, align 8 diff --git a/test/CodeGen/R600/fdiv.ll b/test/CodeGen/R600/fdiv.ll index d00217799f1..5321fdbea1d 100644 --- a/test/CodeGen/R600/fdiv.ll +++ b/test/CodeGen/R600/fdiv.ll @@ -11,8 +11,8 @@ ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS -; SI-DAG: V_RCP_F32 -; SI-DAG: V_MUL_F32 +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 define void @fdiv_f32(float addrspace(1)* %out, float %a, float %b) { entry: %0 = fdiv float %a, %b @@ -28,10 +28,10 @@ entry: ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS -; SI-DAG: V_RCP_F32 -; SI-DAG: V_MUL_F32 -; SI-DAG: V_RCP_F32 -; SI-DAG: V_MUL_F32 +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 define void @fdiv_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { entry: %0 = fdiv <2 x float> %a, %b @@ -49,14 +49,14 @@ entry: ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS -; SI-DAG: V_RCP_F32 -; SI-DAG: V_MUL_F32 -; SI-DAG: V_RCP_F32 -; SI-DAG: V_MUL_F32 -; SI-DAG: V_RCP_F32 -; SI-DAG: V_MUL_F32 -; SI-DAG: V_RCP_F32 -; SI-DAG: V_MUL_F32 +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 define void @fdiv_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 %a = load <4 x float> addrspace(1) * %in diff --git a/test/CodeGen/R600/fdiv64.ll b/test/CodeGen/R600/fdiv64.ll index 312870bbdff..d424898b81c 100644 --- a/test/CodeGen/R600/fdiv64.ll +++ b/test/CodeGen/R600/fdiv64.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; CHECK: {{^}}fdiv_f64: -; CHECK: V_RCP_F64_e32 {{v\[[0-9]+:[0-9]+\]}} -; CHECK: V_MUL_F64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} +; CHECK: v_rcp_f64_e32 {{v\[[0-9]+:[0-9]+\]}} +; CHECK: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} define void @fdiv_f64(double addrspace(1)* %out, double addrspace(1)* %in1, double addrspace(1)* %in2) { diff --git a/test/CodeGen/R600/ffloor.ll b/test/CodeGen/R600/ffloor.ll index 4436e820883..166f7055fb1 100644 --- a/test/CodeGen/R600/ffloor.ll +++ b/test/CodeGen/R600/ffloor.ll @@ -9,26 +9,26 @@ declare <8 x double> @llvm.floor.v8f64(<8 x double>) nounwind readnone declare <16 x double> @llvm.floor.v16f64(<16 x double>) nounwind readnone ; FUNC-LABEL: {{^}}ffloor_f64: -; CI: V_FLOOR_F64_e32 +; CI: v_floor_f64_e32 -; SI: S_BFE_U32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014 -; SI: S_ADD_I32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01 -; SI: S_LSHR_B64 -; SI: S_NOT_B64 -; SI: S_AND_B64 -; SI-DAG: S_AND_B32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 -; SI-DAG: CMP_LT_I32 -; SI: CNDMASK_B32 -; SI: CNDMASK_B32 -; SI: CMP_GT_I32 -; SI: CNDMASK_B32 -; SI: CNDMASK_B32 -; SI: CMP_LT_F64 -; SI: CNDMASK_B32 -; SI: CMP_NE_I32 -; SI: CNDMASK_B32 -; SI: CNDMASK_B32 -; SI: V_ADD_F64 +; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014 +; SI: s_add_i32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01 +; SI: s_lshr_b64 +; SI: s_not_b64 +; SI: s_and_b64 +; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 +; SI-DAG: cmp_lt_i32 +; SI: cndmask_b32 +; SI: cndmask_b32 +; SI: cmp_gt_i32 +; SI: cndmask_b32 +; SI: cndmask_b32 +; SI: cmp_lt_f64 +; SI: cndmask_b32 +; SI: cmp_ne_i32 +; SI: cndmask_b32 +; SI: cndmask_b32 +; SI: v_add_f64 define void @ffloor_f64(double addrspace(1)* %out, double %x) { %y = call double @llvm.floor.f64(double %x) nounwind readnone store double %y, double addrspace(1)* %out @@ -36,8 +36,8 @@ define void @ffloor_f64(double addrspace(1)* %out, double %x) { } ; FUNC-LABEL: {{^}}ffloor_v2f64: -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 define void @ffloor_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) { %y = call <2 x double> @llvm.floor.v2f64(<2 x double> %x) nounwind readnone store <2 x double> %y, <2 x double> addrspace(1)* %out @@ -45,9 +45,9 @@ define void @ffloor_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) { } ; FIXME-FUNC-LABEL: {{^}}ffloor_v3f64: -; FIXME-CI: V_FLOOR_F64_e32 -; FIXME-CI: V_FLOOR_F64_e32 -; FIXME-CI: V_FLOOR_F64_e32 +; FIXME-CI: v_floor_f64_e32 +; FIXME-CI: v_floor_f64_e32 +; FIXME-CI: v_floor_f64_e32 ; define void @ffloor_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) { ; %y = call <3 x double> @llvm.floor.v3f64(<3 x double> %x) nounwind readnone ; store <3 x double> %y, <3 x double> addrspace(1)* %out @@ -55,10 +55,10 @@ define void @ffloor_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) { ; } ; FUNC-LABEL: {{^}}ffloor_v4f64: -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 define void @ffloor_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) { %y = call <4 x double> @llvm.floor.v4f64(<4 x double> %x) nounwind readnone store <4 x double> %y, <4 x double> addrspace(1)* %out @@ -66,14 +66,14 @@ define void @ffloor_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) { } ; FUNC-LABEL: {{^}}ffloor_v8f64: -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 define void @ffloor_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) { %y = call <8 x double> @llvm.floor.v8f64(<8 x double> %x) nounwind readnone store <8 x double> %y, <8 x double> addrspace(1)* %out @@ -81,22 +81,22 @@ define void @ffloor_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) { } ; FUNC-LABEL: {{^}}ffloor_v16f64: -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 -; CI: V_FLOOR_F64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 define void @ffloor_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %x) { %y = call <16 x double> @llvm.floor.v16f64(<16 x double> %x) nounwind readnone store <16 x double> %y, <16 x double> addrspace(1)* %out diff --git a/test/CodeGen/R600/flat-address-space.ll b/test/CodeGen/R600/flat-address-space.ll index ff9bd7312f7..c147bd128d9 100644 --- a/test/CodeGen/R600/flat-address-space.ll +++ b/test/CodeGen/R600/flat-address-space.ll @@ -6,8 +6,8 @@ ; CHECK-LABEL: {{^}}branch_use_flat_i32: -; CHECK: FLAT_STORE_DWORD {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, [M0, FLAT_SCRATCH] -; CHECK: S_ENDPGM +; CHECK: flat_store_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, [M0, FLAT_SCRATCH] +; CHECK: s_endpgm define void @branch_use_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %gptr, i32 addrspace(3)* %lptr, i32 %x, i32 %c) #0 { entry: %cmp = icmp ne i32 %c, 0 @@ -35,10 +35,10 @@ end: ; remove generic pointers. ; CHECK-LABEL: {{^}}store_flat_i32: -; CHECK: V_MOV_B32_e32 v[[DATA:[0-9]+]], {{s[0-9]+}} -; CHECK: V_MOV_B32_e32 v[[LO_VREG:[0-9]+]], {{s[0-9]+}} -; CHECK: V_MOV_B32_e32 v[[HI_VREG:[0-9]+]], {{s[0-9]+}} -; CHECK: FLAT_STORE_DWORD v[[DATA]], v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} +; CHECK: v_mov_b32_e32 v[[DATA:[0-9]+]], {{s[0-9]+}} +; CHECK: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], {{s[0-9]+}} +; CHECK: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], {{s[0-9]+}} +; CHECK: flat_store_dword v[[DATA]], v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} define void @store_flat_i32(i32 addrspace(1)* %gptr, i32 %x) #0 { %fptr = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)* store i32 %x, i32 addrspace(4)* %fptr, align 4 @@ -46,7 +46,7 @@ define void @store_flat_i32(i32 addrspace(1)* %gptr, i32 %x) #0 { } ; CHECK-LABEL: {{^}}store_flat_i64: -; CHECK: FLAT_STORE_DWORDX2 +; CHECK: flat_store_dwordx2 define void @store_flat_i64(i64 addrspace(1)* %gptr, i64 %x) #0 { %fptr = addrspacecast i64 addrspace(1)* %gptr to i64 addrspace(4)* store i64 %x, i64 addrspace(4)* %fptr, align 8 @@ -54,7 +54,7 @@ define void @store_flat_i64(i64 addrspace(1)* %gptr, i64 %x) #0 { } ; CHECK-LABEL: {{^}}store_flat_v4i32: -; CHECK: FLAT_STORE_DWORDX4 +; CHECK: flat_store_dwordx4 define void @store_flat_v4i32(<4 x i32> addrspace(1)* %gptr, <4 x i32> %x) #0 { %fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32> addrspace(4)* store <4 x i32> %x, <4 x i32> addrspace(4)* %fptr, align 16 @@ -62,7 +62,7 @@ define void @store_flat_v4i32(<4 x i32> addrspace(1)* %gptr, <4 x i32> %x) #0 { } ; CHECK-LABEL: {{^}}store_flat_trunc_i16: -; CHECK: FLAT_STORE_SHORT +; CHECK: flat_store_short define void @store_flat_trunc_i16(i16 addrspace(1)* %gptr, i32 %x) #0 { %fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)* %y = trunc i32 %x to i16 @@ -71,7 +71,7 @@ define void @store_flat_trunc_i16(i16 addrspace(1)* %gptr, i32 %x) #0 { } ; CHECK-LABEL: {{^}}store_flat_trunc_i8: -; CHECK: FLAT_STORE_BYTE +; CHECK: flat_store_byte define void @store_flat_trunc_i8(i8 addrspace(1)* %gptr, i32 %x) #0 { %fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)* %y = trunc i32 %x to i8 @@ -82,7 +82,7 @@ define void @store_flat_trunc_i8(i8 addrspace(1)* %gptr, i32 %x) #0 { ; CHECK-LABEL @load_flat_i32: -; CHECK: FLAT_LOAD_DWORD +; CHECK: flat_load_dword define void @load_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %gptr) #0 { %fptr = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)* %fload = load i32 addrspace(4)* %fptr, align 4 @@ -91,7 +91,7 @@ define void @load_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noa } ; CHECK-LABEL @load_flat_i64: -; CHECK: FLAT_LOAD_DWORDX2 +; CHECK: flat_load_dwordx2 define void @load_flat_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %gptr) #0 { %fptr = addrspacecast i64 addrspace(1)* %gptr to i64 addrspace(4)* %fload = load i64 addrspace(4)* %fptr, align 4 @@ -100,7 +100,7 @@ define void @load_flat_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noa } ; CHECK-LABEL @load_flat_v4i32: -; CHECK: FLAT_LOAD_DWORDX4 +; CHECK: flat_load_dwordx4 define void @load_flat_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %gptr) #0 { %fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32> addrspace(4)* %fload = load <4 x i32> addrspace(4)* %fptr, align 4 @@ -109,7 +109,7 @@ define void @load_flat_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> add } ; CHECK-LABEL @sextload_flat_i8: -; CHECK: FLAT_LOAD_SBYTE +; CHECK: flat_load_sbyte define void @sextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 { %fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)* %fload = load i8 addrspace(4)* %fptr, align 4 @@ -119,7 +119,7 @@ define void @sextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* n } ; CHECK-LABEL @zextload_flat_i8: -; CHECK: FLAT_LOAD_UBYTE +; CHECK: flat_load_ubyte define void @zextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 { %fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)* %fload = load i8 addrspace(4)* %fptr, align 4 @@ -129,7 +129,7 @@ define void @zextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* n } ; CHECK-LABEL @sextload_flat_i16: -; CHECK: FLAT_LOAD_SSHORT +; CHECK: flat_load_sshort define void @sextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 { %fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)* %fload = load i16 addrspace(4)* %fptr, align 4 @@ -139,7 +139,7 @@ define void @sextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* } ; CHECK-LABEL @zextload_flat_i16: -; CHECK: FLAT_LOAD_USHORT +; CHECK: flat_load_ushort define void @zextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 { %fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)* %fload = load i16 addrspace(4)* %fptr, align 4 @@ -155,12 +155,12 @@ define void @zextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* ; Check for prologue initializing special SGPRs pointing to scratch. ; CHECK-LABEL: {{^}}store_flat_scratch: -; CHECK: S_MOVK_I32 flat_scratch_lo, 0 -; CHECK-NO-PROMOTE: S_MOVK_I32 flat_scratch_hi, 40 -; CHECK-PROMOTE: S_MOVK_I32 flat_scratch_hi, 0 -; CHECK: FLAT_STORE_DWORD -; CHECK: S_BARRIER -; CHECK: FLAT_LOAD_DWORD +; CHECK: s_movk_i32 flat_scratch_lo, 0 +; CHECK-NO-PROMOTE: s_movk_i32 flat_scratch_hi, 40 +; CHECK-PROMOTE: s_movk_i32 flat_scratch_hi, 0 +; CHECK: flat_store_dword +; CHECK: s_barrier +; CHECK: flat_load_dword define void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 { %alloca = alloca i32, i32 9, align 4 %x = call i32 @llvm.r600.read.tidig.x() #3 diff --git a/test/CodeGen/R600/fma.f64.ll b/test/CodeGen/R600/fma.f64.ll index e4fb441bbfc..4b0ab76ff72 100644 --- a/test/CodeGen/R600/fma.f64.ll +++ b/test/CodeGen/R600/fma.f64.ll @@ -6,7 +6,7 @@ declare <4 x double> @llvm.fma.v4f64(<4 x double>, <4 x double>, <4 x double>) n ; FUNC-LABEL: {{^}}fma_f64: -; SI: V_FMA_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} +; SI: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} define void @fma_f64(double addrspace(1)* %out, double addrspace(1)* %in1, double addrspace(1)* %in2, double addrspace(1)* %in3) { %r0 = load double addrspace(1)* %in1 @@ -18,8 +18,8 @@ define void @fma_f64(double addrspace(1)* %out, double addrspace(1)* %in1, } ; FUNC-LABEL: {{^}}fma_v2f64: -; SI: V_FMA_F64 -; SI: V_FMA_F64 +; SI: v_fma_f64 +; SI: v_fma_f64 define void @fma_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1, <2 x double> addrspace(1)* %in2, <2 x double> addrspace(1)* %in3) { %r0 = load <2 x double> addrspace(1)* %in1 @@ -31,10 +31,10 @@ define void @fma_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1 } ; FUNC-LABEL: {{^}}fma_v4f64: -; SI: V_FMA_F64 -; SI: V_FMA_F64 -; SI: V_FMA_F64 -; SI: V_FMA_F64 +; SI: v_fma_f64 +; SI: v_fma_f64 +; SI: v_fma_f64 +; SI: v_fma_f64 define void @fma_v4f64(<4 x double> addrspace(1)* %out, <4 x double> addrspace(1)* %in1, <4 x double> addrspace(1)* %in2, <4 x double> addrspace(1)* %in3) { %r0 = load <4 x double> addrspace(1)* %in1 diff --git a/test/CodeGen/R600/fma.ll b/test/CodeGen/R600/fma.ll index 0f8190304e4..d715c99a7dc 100644 --- a/test/CodeGen/R600/fma.ll +++ b/test/CodeGen/R600/fma.ll @@ -6,7 +6,7 @@ declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounw declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone ; FUNC-LABEL: {{^}}fma_f32: -; SI: V_FMA_F32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}} ; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}}, ; EG: FMA {{\*? *}}[[RES]] @@ -21,8 +21,8 @@ define void @fma_f32(float addrspace(1)* %out, float addrspace(1)* %in1, } ; FUNC-LABEL: {{^}}fma_v2f32: -; SI: V_FMA_F32 -; SI: V_FMA_F32 +; SI: v_fma_f32 +; SI: v_fma_f32 ; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]]].[[CHLO:[XYZW]]][[CHHI:[XYZW]]], {{T[0-9]\.[XYZW]}}, ; EG-DAG: FMA {{\*? *}}[[RES]].[[CHLO]] @@ -38,10 +38,10 @@ define void @fma_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* } ; FUNC-LABEL: {{^}}fma_v4f32: -; SI: V_FMA_F32 -; SI: V_FMA_F32 -; SI: V_FMA_F32 -; SI: V_FMA_F32 +; SI: v_fma_f32 +; SI: v_fma_f32 +; SI: v_fma_f32 +; SI: v_fma_f32 ; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]]].{{[XYZW][XYZW][XYZW][XYZW]}}, {{T[0-9]\.[XYZW]}}, ; EG-DAG: FMA {{\*? *}}[[RES]].X diff --git a/test/CodeGen/R600/fmaxnum.f64.ll b/test/CodeGen/R600/fmaxnum.f64.ll index af762e108ee..51cbf4dee7c 100644 --- a/test/CodeGen/R600/fmaxnum.f64.ll +++ b/test/CodeGen/R600/fmaxnum.f64.ll @@ -7,7 +7,7 @@ declare <8 x double> @llvm.maxnum.v8f64(<8 x double>, <8 x double>) #0 declare <16 x double> @llvm.maxnum.v16f64(<16 x double>, <16 x double>) #0 ; FUNC-LABEL: @test_fmax_f64 -; SI: V_MAX_F64 +; SI: v_max_f64 define void @test_fmax_f64(double addrspace(1)* %out, double %a, double %b) nounwind { %val = call double @llvm.maxnum.f64(double %a, double %b) #0 store double %val, double addrspace(1)* %out, align 8 @@ -15,8 +15,8 @@ define void @test_fmax_f64(double addrspace(1)* %out, double %a, double %b) noun } ; FUNC-LABEL: @test_fmax_v2f64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 +; SI: v_max_f64 +; SI: v_max_f64 define void @test_fmax_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b) nounwind { %val = call <2 x double> @llvm.maxnum.v2f64(<2 x double> %a, <2 x double> %b) #0 store <2 x double> %val, <2 x double> addrspace(1)* %out, align 16 @@ -24,10 +24,10 @@ define void @test_fmax_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, < } ; FUNC-LABEL: @test_fmax_v4f64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 define void @test_fmax_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b) nounwind { %val = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %a, <4 x double> %b) #0 store <4 x double> %val, <4 x double> addrspace(1)* %out, align 32 @@ -35,14 +35,14 @@ define void @test_fmax_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, < } ; FUNC-LABEL: @test_fmax_v8f64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 define void @test_fmax_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b) nounwind { %val = call <8 x double> @llvm.maxnum.v8f64(<8 x double> %a, <8 x double> %b) #0 store <8 x double> %val, <8 x double> addrspace(1)* %out, align 64 @@ -50,22 +50,22 @@ define void @test_fmax_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, < } ; FUNC-LABEL: @test_fmax_v16f64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 -; SI: V_MAX_F64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 +; SI: v_max_f64 define void @test_fmax_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %a, <16 x double> %b) nounwind { %val = call <16 x double> @llvm.maxnum.v16f64(<16 x double> %a, <16 x double> %b) #0 store <16 x double> %val, <16 x double> addrspace(1)* %out, align 128 diff --git a/test/CodeGen/R600/fmaxnum.ll b/test/CodeGen/R600/fmaxnum.ll index 227537df716..01d30b0b070 100644 --- a/test/CodeGen/R600/fmaxnum.ll +++ b/test/CodeGen/R600/fmaxnum.ll @@ -9,7 +9,7 @@ declare <16 x float> @llvm.maxnum.v16f32(<16 x float>, <16 x float>) #0 declare double @llvm.maxnum.f64(double, double) ; FUNC-LABEL: @test_fmax_f32 -; SI: V_MAX_F32_e32 +; SI: v_max_f32_e32 define void @test_fmax_f32(float addrspace(1)* %out, float %a, float %b) nounwind { %val = call float @llvm.maxnum.f32(float %a, float %b) #0 store float %val, float addrspace(1)* %out, align 4 @@ -17,8 +17,8 @@ define void @test_fmax_f32(float addrspace(1)* %out, float %a, float %b) nounwin } ; FUNC-LABEL: @test_fmax_v2f32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 define void @test_fmax_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) nounwind { %val = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b) #0 store <2 x float> %val, <2 x float> addrspace(1)* %out, align 8 @@ -26,10 +26,10 @@ define void @test_fmax_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 } ; FUNC-LABEL: @test_fmax_v4f32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 define void @test_fmax_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) nounwind { %val = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b) #0 store <4 x float> %val, <4 x float> addrspace(1)* %out, align 16 @@ -37,14 +37,14 @@ define void @test_fmax_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 } ; FUNC-LABEL: @test_fmax_v8f32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 define void @test_fmax_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) nounwind { %val = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %a, <8 x float> %b) #0 store <8 x float> %val, <8 x float> addrspace(1)* %out, align 32 @@ -52,22 +52,22 @@ define void @test_fmax_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 } ; FUNC-LABEL: @test_fmax_v16f32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 -; SI: V_MAX_F32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 +; SI: v_max_f32_e32 define void @test_fmax_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) nounwind { %val = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %a, <16 x float> %b) #0 store <16 x float> %val, <16 x float> addrspace(1)* %out, align 64 @@ -75,9 +75,9 @@ define void @test_fmax_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, } ; FUNC-LABEL: @constant_fold_fmax_f32 -; SI-NOT: V_MAX_F32_e32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 2.0 -; SI: BUFFER_STORE_DWORD [[REG]] +; SI-NOT: v_max_f32_e32 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0 +; SI: buffer_store_dword [[REG]] define void @constant_fold_fmax_f32(float addrspace(1)* %out) nounwind { %val = call float @llvm.maxnum.f32(float 1.0, float 2.0) #0 store float %val, float addrspace(1)* %out, align 4 @@ -85,9 +85,9 @@ define void @constant_fold_fmax_f32(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: @constant_fold_fmax_f32_nan_nan -; SI-NOT: V_MAX_F32_e32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x7fc00000 -; SI: BUFFER_STORE_DWORD [[REG]] +; SI-NOT: v_max_f32_e32 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000 +; SI: buffer_store_dword [[REG]] define void @constant_fold_fmax_f32_nan_nan(float addrspace(1)* %out) nounwind { %val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000) #0 store float %val, float addrspace(1)* %out, align 4 @@ -95,9 +95,9 @@ define void @constant_fold_fmax_f32_nan_nan(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: @constant_fold_fmax_f32_val_nan -; SI-NOT: V_MAX_F32_e32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 1.0 -; SI: BUFFER_STORE_DWORD [[REG]] +; SI-NOT: v_max_f32_e32 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 +; SI: buffer_store_dword [[REG]] define void @constant_fold_fmax_f32_val_nan(float addrspace(1)* %out) nounwind { %val = call float @llvm.maxnum.f32(float 1.0, float 0x7FF8000000000000) #0 store float %val, float addrspace(1)* %out, align 4 @@ -105,9 +105,9 @@ define void @constant_fold_fmax_f32_val_nan(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: @constant_fold_fmax_f32_nan_val -; SI-NOT: V_MAX_F32_e32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 1.0 -; SI: BUFFER_STORE_DWORD [[REG]] +; SI-NOT: v_max_f32_e32 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 +; SI: buffer_store_dword [[REG]] define void @constant_fold_fmax_f32_nan_val(float addrspace(1)* %out) nounwind { %val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 1.0) #0 store float %val, float addrspace(1)* %out, align 4 @@ -115,9 +115,9 @@ define void @constant_fold_fmax_f32_nan_val(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: @constant_fold_fmax_f32_p0_p0 -; SI-NOT: V_MAX_F32_e32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[REG]] +; SI-NOT: v_max_f32_e32 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0 +; SI: buffer_store_dword [[REG]] define void @constant_fold_fmax_f32_p0_p0(float addrspace(1)* %out) nounwind { %val = call float @llvm.maxnum.f32(float 0.0, float 0.0) #0 store float %val, float addrspace(1)* %out, align 4 @@ -125,9 +125,9 @@ define void @constant_fold_fmax_f32_p0_p0(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: @constant_fold_fmax_f32_p0_n0 -; SI-NOT: V_MAX_F32_e32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[REG]] +; SI-NOT: v_max_f32_e32 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0 +; SI: buffer_store_dword [[REG]] define void @constant_fold_fmax_f32_p0_n0(float addrspace(1)* %out) nounwind { %val = call float @llvm.maxnum.f32(float 0.0, float -0.0) #0 store float %val, float addrspace(1)* %out, align 4 @@ -135,9 +135,9 @@ define void @constant_fold_fmax_f32_p0_n0(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: @constant_fold_fmax_f32_n0_p0 -; SI-NOT: V_MAX_F32_e32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x80000000 -; SI: BUFFER_STORE_DWORD [[REG]] +; SI-NOT: v_max_f32_e32 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000 +; SI: buffer_store_dword [[REG]] define void @constant_fold_fmax_f32_n0_p0(float addrspace(1)* %out) nounwind { %val = call float @llvm.maxnum.f32(float -0.0, float 0.0) #0 store float %val, float addrspace(1)* %out, align 4 @@ -145,9 +145,9 @@ define void @constant_fold_fmax_f32_n0_p0(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: @constant_fold_fmax_f32_n0_n0 -; SI-NOT: V_MAX_F32_e32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x80000000 -; SI: BUFFER_STORE_DWORD [[REG]] +; SI-NOT: v_max_f32_e32 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000 +; SI: buffer_store_dword [[REG]] define void @constant_fold_fmax_f32_n0_n0(float addrspace(1)* %out) nounwind { %val = call float @llvm.maxnum.f32(float -0.0, float -0.0) #0 store float %val, float addrspace(1)* %out, align 4 @@ -155,7 +155,7 @@ define void @constant_fold_fmax_f32_n0_n0(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: @fmax_var_immediate_f32 -; SI: V_MAX_F32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}} +; SI: v_max_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}} define void @fmax_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind { %val = call float @llvm.maxnum.f32(float %a, float 2.0) #0 store float %val, float addrspace(1)* %out, align 4 @@ -163,7 +163,7 @@ define void @fmax_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind } ; FUNC-LABEL: @fmax_immediate_var_f32 -; SI: V_MAX_F32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}} +; SI: v_max_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}} define void @fmax_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind { %val = call float @llvm.maxnum.f32(float 2.0, float %a) #0 store float %val, float addrspace(1)* %out, align 4 @@ -171,8 +171,8 @@ define void @fmax_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind } ; FUNC-LABEL: @fmax_var_literal_f32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x42c60000 -; SI: V_MAX_F32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000 +; SI: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] define void @fmax_var_literal_f32(float addrspace(1)* %out, float %a) nounwind { %val = call float @llvm.maxnum.f32(float %a, float 99.0) #0 store float %val, float addrspace(1)* %out, align 4 @@ -180,8 +180,8 @@ define void @fmax_var_literal_f32(float addrspace(1)* %out, float %a) nounwind { } ; FUNC-LABEL: @fmax_literal_var_f32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x42c60000 -; SI: V_MAX_F32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000 +; SI: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] define void @fmax_literal_var_f32(float addrspace(1)* %out, float %a) nounwind { %val = call float @llvm.maxnum.f32(float 99.0, float %a) #0 store float %val, float addrspace(1)* %out, align 4 diff --git a/test/CodeGen/R600/fminnum.f64.ll b/test/CodeGen/R600/fminnum.f64.ll index 5feef60f90d..11b0c20105d 100644 --- a/test/CodeGen/R600/fminnum.f64.ll +++ b/test/CodeGen/R600/fminnum.f64.ll @@ -7,7 +7,7 @@ declare <8 x double> @llvm.minnum.v8f64(<8 x double>, <8 x double>) #0 declare <16 x double> @llvm.minnum.v16f64(<16 x double>, <16 x double>) #0 ; FUNC-LABEL: @test_fmin_f64 -; SI: V_MIN_F64 +; SI: v_min_f64 define void @test_fmin_f64(double addrspace(1)* %out, double %a, double %b) nounwind { %val = call double @llvm.minnum.f64(double %a, double %b) #0 store double %val, double addrspace(1)* %out, align 8 @@ -15,8 +15,8 @@ define void @test_fmin_f64(double addrspace(1)* %out, double %a, double %b) noun } ; FUNC-LABEL: @test_fmin_v2f64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 +; SI: v_min_f64 +; SI: v_min_f64 define void @test_fmin_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b) nounwind { %val = call <2 x double> @llvm.minnum.v2f64(<2 x double> %a, <2 x double> %b) #0 store <2 x double> %val, <2 x double> addrspace(1)* %out, align 16 @@ -24,10 +24,10 @@ define void @test_fmin_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, < } ; FUNC-LABEL: @test_fmin_v4f64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 define void @test_fmin_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b) nounwind { %val = call <4 x double> @llvm.minnum.v4f64(<4 x double> %a, <4 x double> %b) #0 store <4 x double> %val, <4 x double> addrspace(1)* %out, align 32 @@ -35,14 +35,14 @@ define void @test_fmin_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, < } ; FUNC-LABEL: @test_fmin_v8f64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 define void @test_fmin_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b) nounwind { %val = call <8 x double> @llvm.minnum.v8f64(<8 x double> %a, <8 x double> %b) #0 store <8 x double> %val, <8 x double> addrspace(1)* %out, align 64 @@ -50,22 +50,22 @@ define void @test_fmin_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, < } ; FUNC-LABEL: @test_fmin_v16f64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 -; SI: V_MIN_F64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 +; SI: v_min_f64 define void @test_fmin_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %a, <16 x double> %b) nounwind { %val = call <16 x double> @llvm.minnum.v16f64(<16 x double> %a, <16 x double> %b) #0 store <16 x double> %val, <16 x double> addrspace(1)* %out, align 128 diff --git a/test/CodeGen/R600/fminnum.ll b/test/CodeGen/R600/fminnum.ll index b2853f921fc..65adab6c5cb 100644 --- a/test/CodeGen/R600/fminnum.ll +++ b/test/CodeGen/R600/fminnum.ll @@ -7,7 +7,7 @@ declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>) #0 declare <16 x float> @llvm.minnum.v16f32(<16 x float>, <16 x float>) #0 ; FUNC-LABEL: @test_fmin_f32 -; SI: V_MIN_F32_e32 +; SI: v_min_f32_e32 define void @test_fmin_f32(float addrspace(1)* %out, float %a, float %b) nounwind { %val = call float @llvm.minnum.f32(float %a, float %b) #0 store float %val, float addrspace(1)* %out, align 4 @@ -15,8 +15,8 @@ define void @test_fmin_f32(float addrspace(1)* %out, float %a, float %b) nounwin } ; FUNC-LABEL: @test_fmin_v2f32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 define void @test_fmin_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) nounwind { %val = call <2 x float> @llvm.minnum.v2f32(<2 x float> %a, <2 x float> %b) #0 store <2 x float> %val, <2 x float> addrspace(1)* %out, align 8 @@ -24,10 +24,10 @@ define void @test_fmin_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 } ; FUNC-LABEL: @test_fmin_v4f32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 define void @test_fmin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) nounwind { %val = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b) #0 store <4 x float> %val, <4 x float> addrspace(1)* %out, align 16 @@ -35,14 +35,14 @@ define void @test_fmin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 } ; FUNC-LABEL: @test_fmin_v8f32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 define void @test_fmin_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) nounwind { %val = call <8 x float> @llvm.minnum.v8f32(<8 x float> %a, <8 x float> %b) #0 store <8 x float> %val, <8 x float> addrspace(1)* %out, align 32 @@ -50,22 +50,22 @@ define void @test_fmin_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 } ; FUNC-LABEL: @test_fmin_v16f32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 -; SI: V_MIN_F32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 +; SI: v_min_f32_e32 define void @test_fmin_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) nounwind { %val = call <16 x float> @llvm.minnum.v16f32(<16 x float> %a, <16 x float> %b) #0 store <16 x float> %val, <16 x float> addrspace(1)* %out, align 64 @@ -73,9 +73,9 @@ define void @test_fmin_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, } ; FUNC-LABEL: @constant_fold_fmin_f32 -; SI-NOT: V_MIN_F32_e32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 1.0 -; SI: BUFFER_STORE_DWORD [[REG]] +; SI-NOT: v_min_f32_e32 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 +; SI: buffer_store_dword [[REG]] define void @constant_fold_fmin_f32(float addrspace(1)* %out) nounwind { %val = call float @llvm.minnum.f32(float 1.0, float 2.0) #0 store float %val, float addrspace(1)* %out, align 4 @@ -83,9 +83,9 @@ define void @constant_fold_fmin_f32(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: @constant_fold_fmin_f32_nan_nan -; SI-NOT: V_MIN_F32_e32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x7fc00000 -; SI: BUFFER_STORE_DWORD [[REG]] +; SI-NOT: v_min_f32_e32 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000 +; SI: buffer_store_dword [[REG]] define void @constant_fold_fmin_f32_nan_nan(float addrspace(1)* %out) nounwind { %val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000) #0 store float %val, float addrspace(1)* %out, align 4 @@ -93,9 +93,9 @@ define void @constant_fold_fmin_f32_nan_nan(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: @constant_fold_fmin_f32_val_nan -; SI-NOT: V_MIN_F32_e32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 1.0 -; SI: BUFFER_STORE_DWORD [[REG]] +; SI-NOT: v_min_f32_e32 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 +; SI: buffer_store_dword [[REG]] define void @constant_fold_fmin_f32_val_nan(float addrspace(1)* %out) nounwind { %val = call float @llvm.minnum.f32(float 1.0, float 0x7FF8000000000000) #0 store float %val, float addrspace(1)* %out, align 4 @@ -103,9 +103,9 @@ define void @constant_fold_fmin_f32_val_nan(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: @constant_fold_fmin_f32_nan_val -; SI-NOT: V_MIN_F32_e32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 1.0 -; SI: BUFFER_STORE_DWORD [[REG]] +; SI-NOT: v_min_f32_e32 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 +; SI: buffer_store_dword [[REG]] define void @constant_fold_fmin_f32_nan_val(float addrspace(1)* %out) nounwind { %val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 1.0) #0 store float %val, float addrspace(1)* %out, align 4 @@ -113,9 +113,9 @@ define void @constant_fold_fmin_f32_nan_val(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: @constant_fold_fmin_f32_p0_p0 -; SI-NOT: V_MIN_F32_e32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[REG]] +; SI-NOT: v_min_f32_e32 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0 +; SI: buffer_store_dword [[REG]] define void @constant_fold_fmin_f32_p0_p0(float addrspace(1)* %out) nounwind { %val = call float @llvm.minnum.f32(float 0.0, float 0.0) #0 store float %val, float addrspace(1)* %out, align 4 @@ -123,9 +123,9 @@ define void @constant_fold_fmin_f32_p0_p0(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: @constant_fold_fmin_f32_p0_n0 -; SI-NOT: V_MIN_F32_e32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[REG]] +; SI-NOT: v_min_f32_e32 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0 +; SI: buffer_store_dword [[REG]] define void @constant_fold_fmin_f32_p0_n0(float addrspace(1)* %out) nounwind { %val = call float @llvm.minnum.f32(float 0.0, float -0.0) #0 store float %val, float addrspace(1)* %out, align 4 @@ -133,9 +133,9 @@ define void @constant_fold_fmin_f32_p0_n0(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: @constant_fold_fmin_f32_n0_p0 -; SI-NOT: V_MIN_F32_e32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x80000000 -; SI: BUFFER_STORE_DWORD [[REG]] +; SI-NOT: v_min_f32_e32 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000 +; SI: buffer_store_dword [[REG]] define void @constant_fold_fmin_f32_n0_p0(float addrspace(1)* %out) nounwind { %val = call float @llvm.minnum.f32(float -0.0, float 0.0) #0 store float %val, float addrspace(1)* %out, align 4 @@ -143,9 +143,9 @@ define void @constant_fold_fmin_f32_n0_p0(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: @constant_fold_fmin_f32_n0_n0 -; SI-NOT: V_MIN_F32_e32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x80000000 -; SI: BUFFER_STORE_DWORD [[REG]] +; SI-NOT: v_min_f32_e32 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000 +; SI: buffer_store_dword [[REG]] define void @constant_fold_fmin_f32_n0_n0(float addrspace(1)* %out) nounwind { %val = call float @llvm.minnum.f32(float -0.0, float -0.0) #0 store float %val, float addrspace(1)* %out, align 4 @@ -153,7 +153,7 @@ define void @constant_fold_fmin_f32_n0_n0(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: @fmin_var_immediate_f32 -; SI: V_MIN_F32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}} +; SI: v_min_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}} define void @fmin_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind { %val = call float @llvm.minnum.f32(float %a, float 2.0) #0 store float %val, float addrspace(1)* %out, align 4 @@ -161,7 +161,7 @@ define void @fmin_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind } ; FUNC-LABEL: @fmin_immediate_var_f32 -; SI: V_MIN_F32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}} +; SI: v_min_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}} define void @fmin_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind { %val = call float @llvm.minnum.f32(float 2.0, float %a) #0 store float %val, float addrspace(1)* %out, align 4 @@ -169,8 +169,8 @@ define void @fmin_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind } ; FUNC-LABEL: @fmin_var_literal_f32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x42c60000 -; SI: V_MIN_F32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000 +; SI: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] define void @fmin_var_literal_f32(float addrspace(1)* %out, float %a) nounwind { %val = call float @llvm.minnum.f32(float %a, float 99.0) #0 store float %val, float addrspace(1)* %out, align 4 @@ -178,8 +178,8 @@ define void @fmin_var_literal_f32(float addrspace(1)* %out, float %a) nounwind { } ; FUNC-LABEL: @fmin_literal_var_f32 -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x42c60000 -; SI: V_MIN_F32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000 +; SI: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] define void @fmin_literal_var_f32(float addrspace(1)* %out, float %a) nounwind { %val = call float @llvm.minnum.f32(float 99.0, float %a) #0 store float %val, float addrspace(1)* %out, align 4 diff --git a/test/CodeGen/R600/fmul.ll b/test/CodeGen/R600/fmul.ll index 814ed59340a..eabb2712353 100644 --- a/test/CodeGen/R600/fmul.ll +++ b/test/CodeGen/R600/fmul.ll @@ -5,7 +5,7 @@ ; FUNC-LABEL: {{^}}fmul_f32: ; R600: MUL_IEEE {{\** *}}{{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W -; SI: V_MUL_F32 +; SI: v_mul_f32 define void @fmul_f32(float addrspace(1)* %out, float %a, float %b) { entry: %0 = fmul float %a, %b @@ -21,8 +21,8 @@ declare void @llvm.AMDGPU.store.output(float, i32) ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}} ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}} -; SI: V_MUL_F32 -; SI: V_MUL_F32 +; SI: v_mul_f32 +; SI: v_mul_f32 define void @fmul_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { entry: %0 = fmul <2 x float> %a, %b @@ -36,10 +36,10 @@ entry: ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; SI: V_MUL_F32 -; SI: V_MUL_F32 -; SI: V_MUL_F32 -; SI: V_MUL_F32 +; SI: v_mul_f32 +; SI: v_mul_f32 +; SI: v_mul_f32 +; SI: v_mul_f32 define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 %a = load <4 x float> addrspace(1) * %in @@ -50,9 +50,9 @@ define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1) } ; FUNC-LABEL: {{^}}test_mul_2_k: -; SI: V_MUL_F32 -; SI-NOT: V_MUL_F32 -; SI: S_ENDPGM +; SI: v_mul_f32 +; SI-NOT: v_mul_f32 +; SI: s_endpgm define void @test_mul_2_k(float addrspace(1)* %out, float %x) #0 { %y = fmul float %x, 2.0 %z = fmul float %y, 3.0 @@ -61,10 +61,10 @@ define void @test_mul_2_k(float addrspace(1)* %out, float %x) #0 { } ; FUNC-LABEL: {{^}}test_mul_2_k_inv: -; SI: V_MUL_F32 -; SI-NOT: V_MUL_F32 -; SI-NOT: V_MAD_F32 -; SI: S_ENDPGM +; SI: v_mul_f32 +; SI-NOT: v_mul_f32 +; SI-NOT: v_mad_f32 +; SI: s_endpgm define void @test_mul_2_k_inv(float addrspace(1)* %out, float %x) #0 { %y = fmul float %x, 3.0 %z = fmul float %y, 2.0 diff --git a/test/CodeGen/R600/fmul64.ll b/test/CodeGen/R600/fmul64.ll index c35f5f3b408..0a5f7071dd7 100644 --- a/test/CodeGen/R600/fmul64.ll +++ b/test/CodeGen/R600/fmul64.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=r600 -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s ; FUNC-LABEL: {{^}}fmul_f64: -; SI: V_MUL_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} +; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} define void @fmul_f64(double addrspace(1)* %out, double addrspace(1)* %in1, double addrspace(1)* %in2) { %r0 = load double addrspace(1)* %in1 @@ -12,8 +12,8 @@ define void @fmul_f64(double addrspace(1)* %out, double addrspace(1)* %in1, } ; FUNC-LABEL: {{^}}fmul_v2f64: -; SI: V_MUL_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} -; SI: V_MUL_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} +; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} +; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} define void @fmul_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1, <2 x double> addrspace(1)* %in2) { %r0 = load <2 x double> addrspace(1)* %in1 @@ -24,10 +24,10 @@ define void @fmul_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace( } ; FUNC-LABEL: {{^}}fmul_v4f64: -; SI: V_MUL_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} -; SI: V_MUL_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} -; SI: V_MUL_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} -; SI: V_MUL_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} +; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} +; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} +; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} +; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} define void @fmul_v4f64(<4 x double> addrspace(1)* %out, <4 x double> addrspace(1)* %in1, <4 x double> addrspace(1)* %in2) { %r0 = load <4 x double> addrspace(1)* %in1 diff --git a/test/CodeGen/R600/fmuladd.ll b/test/CodeGen/R600/fmuladd.ll index c2360e6ec98..becc3e441ca 100644 --- a/test/CodeGen/R600/fmuladd.ll +++ b/test/CodeGen/R600/fmuladd.ll @@ -6,7 +6,7 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone declare float @llvm.fabs.f32(float) nounwind readnone ; CHECK-LABEL: {{^}}fmuladd_f32: -; CHECK: V_MAD_F32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}} +; CHECK: v_mad_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}} define void @fmuladd_f32(float addrspace(1)* %out, float addrspace(1)* %in1, float addrspace(1)* %in2, float addrspace(1)* %in3) { @@ -19,7 +19,7 @@ define void @fmuladd_f32(float addrspace(1)* %out, float addrspace(1)* %in1, } ; CHECK-LABEL: {{^}}fmuladd_f64: -; CHECK: V_FMA_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} +; CHECK: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} define void @fmuladd_f64(double addrspace(1)* %out, double addrspace(1)* %in1, double addrspace(1)* %in2, double addrspace(1)* %in3) { @@ -32,10 +32,10 @@ define void @fmuladd_f64(double addrspace(1)* %out, double addrspace(1)* %in1, } ; CHECK-LABEL: {{^}}fmuladd_2.0_a_b_f32 -; CHECK-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; CHECK-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 -; CHECK: V_MAD_F32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]] -; CHECK: BUFFER_STORE_DWORD [[RESULT]] +; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 +; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]] +; CHECK: buffer_store_dword [[RESULT]] define void @fmuladd_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid @@ -51,10 +51,10 @@ define void @fmuladd_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* % } ; CHECK-LABEL: {{^}}fmuladd_a_2.0_b_f32 -; CHECK-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; CHECK-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 -; CHECK: V_MAD_F32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]] -; CHECK: BUFFER_STORE_DWORD [[RESULT]] +; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 +; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]] +; CHECK: buffer_store_dword [[RESULT]] define void @fmuladd_a_2.0_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid @@ -70,10 +70,10 @@ define void @fmuladd_a_2.0_b_f32(float addrspace(1)* %out, float addrspace(1)* % } ; CHECK-LABEL: {{^}}fadd_a_a_b_f32: -; CHECK-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; CHECK-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 -; CHECK: V_MAD_F32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]] -; CHECK: BUFFER_STORE_DWORD [[RESULT]] +; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 +; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]] +; CHECK: buffer_store_dword [[RESULT]] define void @fadd_a_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in1, float addrspace(1)* %in2) { @@ -92,10 +92,10 @@ define void @fadd_a_a_b_f32(float addrspace(1)* %out, } ; CHECK-LABEL: {{^}}fadd_b_a_a_f32: -; CHECK-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; CHECK-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 -; CHECK: V_MAD_F32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]] -; CHECK: BUFFER_STORE_DWORD [[RESULT]] +; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 +; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]] +; CHECK: buffer_store_dword [[RESULT]] define void @fadd_b_a_a_f32(float addrspace(1)* %out, float addrspace(1)* %in1, float addrspace(1)* %in2) { @@ -114,10 +114,10 @@ define void @fadd_b_a_a_f32(float addrspace(1)* %out, } ; CHECK-LABEL: {{^}}fmuladd_neg_2.0_a_b_f32 -; CHECK-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; CHECK-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 -; CHECK: V_MAD_F32 [[RESULT:v[0-9]+]], [[R1]], -2.0, [[R2]] -; CHECK: BUFFER_STORE_DWORD [[RESULT]] +; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 +; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], [[R1]], -2.0, [[R2]] +; CHECK: buffer_store_dword [[RESULT]] define void @fmuladd_neg_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid @@ -134,10 +134,10 @@ define void @fmuladd_neg_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1 ; CHECK-LABEL: {{^}}fmuladd_neg_2.0_neg_a_b_f32 -; CHECK-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; CHECK-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 -; CHECK: V_MAD_F32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]] -; CHECK: BUFFER_STORE_DWORD [[RESULT]] +; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 +; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]] +; CHECK: buffer_store_dword [[RESULT]] define void @fmuladd_neg_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid @@ -156,10 +156,10 @@ define void @fmuladd_neg_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspa ; CHECK-LABEL: {{^}}fmuladd_2.0_neg_a_b_f32 -; CHECK-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; CHECK-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 -; CHECK: V_MAD_F32 [[RESULT:v[0-9]+]], [[R1]], -2.0, [[R2]] -; CHECK: BUFFER_STORE_DWORD [[RESULT]] +; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 +; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], [[R1]], -2.0, [[R2]] +; CHECK: buffer_store_dword [[RESULT]] define void @fmuladd_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid @@ -178,10 +178,10 @@ define void @fmuladd_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1 ; CHECK-LABEL: {{^}}fmuladd_2.0_a_neg_b_f32 -; CHECK-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; CHECK-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 -; CHECK: V_MAD_F32 [[RESULT:v[0-9]+]], 2.0, [[R1]], -[[R2]] -; CHECK: BUFFER_STORE_DWORD [[RESULT]] +; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 +; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], -[[R2]] +; CHECK: buffer_store_dword [[RESULT]] define void @fmuladd_2.0_a_neg_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid diff --git a/test/CodeGen/R600/fneg-fabs.f64.ll b/test/CodeGen/R600/fneg-fabs.f64.ll index 53d032c1b47..555f4cc5698 100644 --- a/test/CodeGen/R600/fneg-fabs.f64.ll +++ b/test/CodeGen/R600/fneg-fabs.f64.ll @@ -4,9 +4,9 @@ ; into 2 modifiers, although theoretically that should work. ; FUNC-LABEL: {{^}}fneg_fabs_fadd_f64: -; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x7fffffff -; SI: V_AND_B32_e32 v[[FABS:[0-9]+]], {{s[0-9]+}}, [[IMMREG]] -; SI: V_ADD_F64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, -v{{\[[0-9]+}}:[[FABS]]{{\]}} +; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x7fffffff +; SI: v_and_b32_e32 v[[FABS:[0-9]+]], {{s[0-9]+}}, [[IMMREG]] +; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, -v{{\[[0-9]+}}:[[FABS]]{{\]}} define void @fneg_fabs_fadd_f64(double addrspace(1)* %out, double %x, double %y) { %fabs = call double @llvm.fabs.f64(double %x) %fsub = fsub double -0.000000e+00, %fabs @@ -26,7 +26,7 @@ define void @v_fneg_fabs_fadd_f64(double addrspace(1)* %out, double addrspace(1) } ; FUNC-LABEL: {{^}}fneg_fabs_fmul_f64: -; SI: V_MUL_F64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|{{v\[[0-9]+:[0-9]+\]}}| +; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|{{v\[[0-9]+:[0-9]+\]}}| define void @fneg_fabs_fmul_f64(double addrspace(1)* %out, double %x, double %y) { %fabs = call double @llvm.fabs.f64(double %x) %fsub = fsub double -0.000000e+00, %fabs @@ -45,8 +45,8 @@ define void @fneg_fabs_free_f64(double addrspace(1)* %out, i64 %in) { } ; FUNC-LABEL: {{^}}fneg_fabs_fn_free_f64: -; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000 -; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 +; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] define void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) { %bc = bitcast i64 %in to double %fabs = call double @fabs(double %bc) @@ -56,12 +56,12 @@ define void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) { } ; FUNC-LABEL: {{^}}fneg_fabs_f64: -; SI: S_LOAD_DWORDX2 -; SI: S_LOAD_DWORDX2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}} -; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000 -; SI-DAG: V_OR_B32_e32 v[[HI_V:[0-9]+]], s[[HI_X]], [[IMMREG]] -; SI-DAG: V_MOV_B32_e32 v[[LO_V:[0-9]+]], s[[LO_X]] -; SI: BUFFER_STORE_DWORDX2 v{{\[}}[[LO_V]]:[[HI_V]]{{\]}} +; SI: s_load_dwordx2 +; SI: s_load_dwordx2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}} +; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 +; SI-DAG: v_or_b32_e32 v[[HI_V:[0-9]+]], s[[HI_X]], [[IMMREG]] +; SI-DAG: v_mov_b32_e32 v[[LO_V:[0-9]+]], s[[LO_X]] +; SI: buffer_store_dwordx2 v{{\[}}[[LO_V]]:[[HI_V]]{{\]}} define void @fneg_fabs_f64(double addrspace(1)* %out, double %in) { %fabs = call double @llvm.fabs.f64(double %in) %fsub = fsub double -0.000000e+00, %fabs @@ -70,10 +70,10 @@ define void @fneg_fabs_f64(double addrspace(1)* %out, double %in) { } ; FUNC-LABEL: {{^}}fneg_fabs_v2f64: -; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000 +; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 ; SI-NOT: 0x80000000 -; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] -; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] define void @fneg_fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) { %fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in) %fsub = fsub <2 x double> , %fabs @@ -82,12 +82,12 @@ define void @fneg_fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) } ; FUNC-LABEL: {{^}}fneg_fabs_v4f64: -; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000 +; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 ; SI-NOT: 0x80000000 -; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] -; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] -; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] -; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] define void @fneg_fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) { %fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in) %fsub = fsub <4 x double> , %fabs diff --git a/test/CodeGen/R600/fneg-fabs.ll b/test/CodeGen/R600/fneg-fabs.ll index bedc659ff9c..3cc832f15b4 100644 --- a/test/CodeGen/R600/fneg-fabs.ll +++ b/test/CodeGen/R600/fneg-fabs.ll @@ -2,8 +2,8 @@ ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}fneg_fabs_fadd_f32: -; SI-NOT: AND -; SI: V_SUB_F32_e64 {{v[0-9]+}}, {{s[0-9]+}}, |{{v[0-9]+}}| +; SI-NOT: and +; SI: v_sub_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, |{{v[0-9]+}}| define void @fneg_fabs_fadd_f32(float addrspace(1)* %out, float %x, float %y) { %fabs = call float @llvm.fabs.f32(float %x) %fsub = fsub float -0.000000e+00, %fabs @@ -13,9 +13,9 @@ define void @fneg_fabs_fadd_f32(float addrspace(1)* %out, float %x, float %y) { } ; FUNC-LABEL: {{^}}fneg_fabs_fmul_f32: -; SI-NOT: AND -; SI: V_MUL_F32_e64 {{v[0-9]+}}, {{s[0-9]+}}, -|{{v[0-9]+}}| -; SI-NOT: AND +; SI-NOT: and +; SI: v_mul_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, -|{{v[0-9]+}}| +; SI-NOT: and define void @fneg_fabs_fmul_f32(float addrspace(1)* %out, float %x, float %y) { %fabs = call float @llvm.fabs.f32(float %x) %fsub = fsub float -0.000000e+00, %fabs @@ -33,8 +33,8 @@ define void @fneg_fabs_fmul_f32(float addrspace(1)* %out, float %x, float %y) { ; R600: |PV.{{[XYZW]}}| ; R600: -PV -; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000 -; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 +; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] define void @fneg_fabs_free_f32(float addrspace(1)* %out, i32 %in) { %bc = bitcast i32 %in to float %fabs = call float @llvm.fabs.f32(float %bc) @@ -48,8 +48,8 @@ define void @fneg_fabs_free_f32(float addrspace(1)* %out, i32 %in) { ; R600: |PV.{{[XYZW]}}| ; R600: -PV -; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000 -; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 +; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] define void @fneg_fabs_fn_free_f32(float addrspace(1)* %out, i32 %in) { %bc = bitcast i32 %in to float %fabs = call float @fabs(float %bc) @@ -59,8 +59,8 @@ define void @fneg_fabs_fn_free_f32(float addrspace(1)* %out, i32 %in) { } ; FUNC-LABEL: {{^}}fneg_fabs_f32: -; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000 -; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 +; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] define void @fneg_fabs_f32(float addrspace(1)* %out, float %in) { %fabs = call float @llvm.fabs.f32(float %in) %fsub = fsub float -0.000000e+00, %fabs @@ -69,7 +69,7 @@ define void @fneg_fabs_f32(float addrspace(1)* %out, float %in) { } ; FUNC-LABEL: {{^}}v_fneg_fabs_f32: -; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}} define void @v_fneg_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) { %val = load float addrspace(1)* %in, align 4 %fabs = call float @llvm.fabs.f32(float %val) @@ -85,10 +85,10 @@ define void @v_fneg_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) ; R600: -PV ; FIXME: SGPR should be used directly for first src operand. -; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000 +; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 ; SI-NOT: 0x80000000 -; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]] -; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]] +; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]] +; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]] define void @fneg_fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in) %fsub = fsub <2 x float> , %fabs @@ -98,12 +98,12 @@ define void @fneg_fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { ; FIXME: SGPR should be used directly for first src operand. ; FUNC-LABEL: {{^}}fneg_fabs_v4f32: -; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000 +; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 ; SI-NOT: 0x80000000 -; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]] -; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]] -; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]] -; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]] +; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]] +; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]] +; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]] +; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]] define void @fneg_fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in) %fsub = fsub <4 x float> , %fabs diff --git a/test/CodeGen/R600/fneg.f64.ll b/test/CodeGen/R600/fneg.f64.ll index 68a1c0f2320..7aa08a9856f 100644 --- a/test/CodeGen/R600/fneg.f64.ll +++ b/test/CodeGen/R600/fneg.f64.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}fneg_f64: -; SI: V_XOR_B32 +; SI: v_xor_b32 define void @fneg_f64(double addrspace(1)* %out, double %in) { %fneg = fsub double -0.000000e+00, %in store double %fneg, double addrspace(1)* %out @@ -9,8 +9,8 @@ define void @fneg_f64(double addrspace(1)* %out, double %in) { } ; FUNC-LABEL: {{^}}fneg_v2f64: -; SI: V_XOR_B32 -; SI: V_XOR_B32 +; SI: v_xor_b32 +; SI: v_xor_b32 define void @fneg_v2f64(<2 x double> addrspace(1)* nocapture %out, <2 x double> %in) { %fneg = fsub <2 x double> , %in store <2 x double> %fneg, <2 x double> addrspace(1)* %out @@ -23,10 +23,10 @@ define void @fneg_v2f64(<2 x double> addrspace(1)* nocapture %out, <2 x double> ; R600: -PV ; R600: -PV -; SI: V_XOR_B32 -; SI: V_XOR_B32 -; SI: V_XOR_B32 -; SI: V_XOR_B32 +; SI: v_xor_b32 +; SI: v_xor_b32 +; SI: v_xor_b32 +; SI: v_xor_b32 define void @fneg_v4f64(<4 x double> addrspace(1)* nocapture %out, <4 x double> %in) { %fneg = fsub <4 x double> , %in store <4 x double> %fneg, <4 x double> addrspace(1)* %out @@ -39,7 +39,7 @@ define void @fneg_v4f64(<4 x double> addrspace(1)* nocapture %out, <4 x double> ; FUNC-LABEL: {{^}}fneg_free_f64: ; FIXME: Unnecessary copy to VGPRs -; SI: V_ADD_F64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, -{{v\[[0-9]+:[0-9]+\]$}} +; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, -{{v\[[0-9]+:[0-9]+\]$}} define void @fneg_free_f64(double addrspace(1)* %out, i64 %in) { %bc = bitcast i64 %in to double %fsub = fsub double 0.0, %bc @@ -48,9 +48,9 @@ define void @fneg_free_f64(double addrspace(1)* %out, i64 %in) { } ; SI-LABEL: {{^}}fneg_fold_f64: -; SI: S_LOAD_DWORDX2 [[NEG_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb -; SI-NOT: XOR -; SI: V_MUL_F64 {{v\[[0-9]+:[0-9]+\]}}, -[[NEG_VALUE]], [[NEG_VALUE]] +; SI: s_load_dwordx2 [[NEG_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb +; SI-NOT: xor +; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, -[[NEG_VALUE]], [[NEG_VALUE]] define void @fneg_fold_f64(double addrspace(1)* %out, double %in) { %fsub = fsub double -0.0, %in %fmul = fmul double %fsub, %in diff --git a/test/CodeGen/R600/fneg.ll b/test/CodeGen/R600/fneg.ll index 638983ab8f2..c20cf2466d4 100644 --- a/test/CodeGen/R600/fneg.ll +++ b/test/CodeGen/R600/fneg.ll @@ -4,7 +4,7 @@ ; FUNC-LABEL: {{^}}fneg_f32: ; R600: -PV -; SI: V_XOR_B32 +; SI: v_xor_b32 define void @fneg_f32(float addrspace(1)* %out, float %in) { %fneg = fsub float -0.000000e+00, %in store float %fneg, float addrspace(1)* %out @@ -15,8 +15,8 @@ define void @fneg_f32(float addrspace(1)* %out, float %in) { ; R600: -PV ; R600: -PV -; SI: V_XOR_B32 -; SI: V_XOR_B32 +; SI: v_xor_b32 +; SI: v_xor_b32 define void @fneg_v2f32(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) { %fneg = fsub <2 x float> , %in store <2 x float> %fneg, <2 x float> addrspace(1)* %out @@ -29,10 +29,10 @@ define void @fneg_v2f32(<2 x float> addrspace(1)* nocapture %out, <2 x float> %i ; R600: -PV ; R600: -PV -; SI: V_XOR_B32 -; SI: V_XOR_B32 -; SI: V_XOR_B32 -; SI: V_XOR_B32 +; SI: v_xor_b32 +; SI: v_xor_b32 +; SI: v_xor_b32 +; SI: v_xor_b32 define void @fneg_v4f32(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) { %fneg = fsub <4 x float> , %in store <4 x float> %fneg, <4 x float> addrspace(1)* %out @@ -47,8 +47,8 @@ define void @fneg_v4f32(<4 x float> addrspace(1)* nocapture %out, <4 x float> %i ; R600-NOT: XOR ; R600: -KC0[2].Z -; XXX: We could use V_ADD_F32_e64 with the negate bit here instead. -; SI: V_SUB_F32_e64 v{{[0-9]}}, 0.0, s{{[0-9]+$}} +; XXX: We could use v_add_f32_e64 with the negate bit here instead. +; SI: v_sub_f32_e64 v{{[0-9]}}, 0.0, s{{[0-9]+$}} define void @fneg_free_f32(float addrspace(1)* %out, i32 %in) { %bc = bitcast i32 %in to float %fsub = fsub float 0.0, %bc @@ -57,9 +57,9 @@ define void @fneg_free_f32(float addrspace(1)* %out, i32 %in) { } ; FUNC-LABEL: {{^}}fneg_fold_f32: -; SI: S_LOAD_DWORD [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb -; SI-NOT: XOR -; SI: V_MUL_F32_e64 v{{[0-9]+}}, -[[NEG_VALUE]], [[NEG_VALUE]] +; SI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb +; SI-NOT: xor +; SI: v_mul_f32_e64 v{{[0-9]+}}, -[[NEG_VALUE]], [[NEG_VALUE]] define void @fneg_fold_f32(float addrspace(1)* %out, float %in) { %fsub = fsub float -0.0, %in %fmul = fmul float %fsub, %in diff --git a/test/CodeGen/R600/fp16_to_fp.ll b/test/CodeGen/R600/fp16_to_fp.ll index 79fff1e1aa9..ec3e0519dcc 100644 --- a/test/CodeGen/R600/fp16_to_fp.ll +++ b/test/CodeGen/R600/fp16_to_fp.ll @@ -4,9 +4,9 @@ declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone declare double @llvm.convert.from.fp16.f64(i16) nounwind readnone ; SI-LABEL: {{^}}test_convert_fp16_to_fp32: -; SI: BUFFER_LOAD_USHORT [[VAL:v[0-9]+]] -; SI: V_CVT_F32_F16_e32 [[RESULT:v[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI: buffer_load_ushort [[VAL:v[0-9]+]] +; SI: v_cvt_f32_f16_e32 [[RESULT:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[RESULT]] define void @test_convert_fp16_to_fp32(float addrspace(1)* noalias %out, i16 addrspace(1)* noalias %in) nounwind { %val = load i16 addrspace(1)* %in, align 2 %cvt = call float @llvm.convert.from.fp16.f32(i16 %val) nounwind readnone @@ -16,10 +16,10 @@ define void @test_convert_fp16_to_fp32(float addrspace(1)* noalias %out, i16 add ; SI-LABEL: {{^}}test_convert_fp16_to_fp64: -; SI: BUFFER_LOAD_USHORT [[VAL:v[0-9]+]] -; SI: V_CVT_F32_F16_e32 [[RESULT32:v[0-9]+]], [[VAL]] -; SI: V_CVT_F64_F32_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[RESULT32]] -; SI: BUFFER_STORE_DWORDX2 [[RESULT]] +; SI: buffer_load_ushort [[VAL:v[0-9]+]] +; SI: v_cvt_f32_f16_e32 [[RESULT32:v[0-9]+]], [[VAL]] +; SI: v_cvt_f64_f32_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[RESULT32]] +; SI: buffer_store_dwordx2 [[RESULT]] define void @test_convert_fp16_to_fp64(double addrspace(1)* noalias %out, i16 addrspace(1)* noalias %in) nounwind { %val = load i16 addrspace(1)* %in, align 2 %cvt = call double @llvm.convert.from.fp16.f64(i16 %val) nounwind readnone diff --git a/test/CodeGen/R600/fp32_to_fp16.ll b/test/CodeGen/R600/fp32_to_fp16.ll index 802cca88877..e86ee62647b 100644 --- a/test/CodeGen/R600/fp32_to_fp16.ll +++ b/test/CodeGen/R600/fp32_to_fp16.ll @@ -3,9 +3,9 @@ declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone ; SI-LABEL: {{^}}test_convert_fp32_to_fp16: -; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]] -; SI: V_CVT_F16_F32_e32 [[RESULT:v[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_SHORT [[RESULT]] +; SI: buffer_load_dword [[VAL:v[0-9]+]] +; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[VAL]] +; SI: buffer_store_short [[RESULT]] define void @test_convert_fp32_to_fp16(i16 addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind { %val = load float addrspace(1)* %in, align 4 %cvt = call i16 @llvm.convert.to.fp16.f32(float %val) nounwind readnone diff --git a/test/CodeGen/R600/fp_to_sint.f64.ll b/test/CodeGen/R600/fp_to_sint.f64.ll index 5543808c381..09edb40bc95 100644 --- a/test/CodeGen/R600/fp_to_sint.f64.ll +++ b/test/CodeGen/R600/fp_to_sint.f64.ll @@ -4,7 +4,7 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone ; FUNC-LABEL: @fp_to_sint_f64_i32 -; SI: V_CVT_I32_F64_e32 +; SI: v_cvt_i32_f64_e32 define void @fp_to_sint_f64_i32(i32 addrspace(1)* %out, double %in) { %result = fptosi double %in to i32 store i32 %result, i32 addrspace(1)* %out @@ -12,8 +12,8 @@ define void @fp_to_sint_f64_i32(i32 addrspace(1)* %out, double %in) { } ; FUNC-LABEL: @fp_to_sint_v2f64_v2i32 -; SI: V_CVT_I32_F64_e32 -; SI: V_CVT_I32_F64_e32 +; SI: v_cvt_i32_f64_e32 +; SI: v_cvt_i32_f64_e32 define void @fp_to_sint_v2f64_v2i32(<2 x i32> addrspace(1)* %out, <2 x double> %in) { %result = fptosi <2 x double> %in to <2 x i32> store <2 x i32> %result, <2 x i32> addrspace(1)* %out @@ -21,10 +21,10 @@ define void @fp_to_sint_v2f64_v2i32(<2 x i32> addrspace(1)* %out, <2 x double> % } ; FUNC-LABEL: @fp_to_sint_v4f64_v4i32 -; SI: V_CVT_I32_F64_e32 -; SI: V_CVT_I32_F64_e32 -; SI: V_CVT_I32_F64_e32 -; SI: V_CVT_I32_F64_e32 +; SI: v_cvt_i32_f64_e32 +; SI: v_cvt_i32_f64_e32 +; SI: v_cvt_i32_f64_e32 +; SI: v_cvt_i32_f64_e32 define void @fp_to_sint_v4f64_v4i32(<4 x i32> addrspace(1)* %out, <4 x double> %in) { %result = fptosi <4 x double> %in to <4 x i32> store <4 x i32> %result, <4 x i32> addrspace(1)* %out @@ -32,20 +32,20 @@ define void @fp_to_sint_v4f64_v4i32(<4 x i32> addrspace(1)* %out, <4 x double> % } ; FUNC-LABEL: @fp_to_sint_i64_f64 -; CI-DAG: BUFFER_LOAD_DWORDX2 [[VAL:v\[[0-9]+:[0-9]+\]]] -; CI-DAG: V_TRUNC_F64_e32 [[TRUNC:v\[[0-9]+:[0-9]+\]]], [[VAL]] -; CI-DAG: S_MOV_B32 s[[K0_LO:[0-9]+]], 0{{$}} -; CI-DAG: S_MOV_B32 s[[K0_HI:[0-9]+]], 0x3df00000 +; CI-DAG: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] +; CI-DAG: v_trunc_f64_e32 [[TRUNC:v\[[0-9]+:[0-9]+\]]], [[VAL]] +; CI-DAG: s_mov_b32 s[[K0_LO:[0-9]+]], 0{{$}} +; CI-DAG: s_mov_b32 s[[K0_HI:[0-9]+]], 0x3df00000 -; CI-DAG: V_MUL_F64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[VAL]], s{{\[}}[[K0_LO]]:[[K0_HI]]{{\]}} -; CI-DAG: V_FLOOR_F64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[MUL]] +; CI-DAG: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[VAL]], s{{\[}}[[K0_LO]]:[[K0_HI]]{{\]}} +; CI-DAG: v_floor_f64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[MUL]] -; CI-DAG: S_MOV_B32 s[[K1_HI:[0-9]+]], 0xc1f00000 +; CI-DAG: s_mov_b32 s[[K1_HI:[0-9]+]], 0xc1f00000 -; CI-DAG: V_FMA_F64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]{{\]}}, [[TRUNC]] -; CI-DAG: V_CVT_U32_F64_e32 v[[LO:[0-9]+]], [[FMA]] -; CI-DAG: V_CVT_I32_F64_e32 v[[HI:[0-9]+]], [[FLOOR]] -; CI: BUFFER_STORE_DWORDX2 v{{\[}}[[LO]]:[[HI]]{{\]}} +; CI-DAG: v_fma_f64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]{{\]}}, [[TRUNC]] +; CI-DAG: v_cvt_u32_f64_e32 v[[LO:[0-9]+]], [[FMA]] +; CI-DAG: v_cvt_i32_f64_e32 v[[HI:[0-9]+]], [[FLOOR]] +; CI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} define void @fp_to_sint_i64_f64(i64 addrspace(1)* %out, double addrspace(1)* %in) { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep = getelementptr double addrspace(1)* %in, i32 %tid diff --git a/test/CodeGen/R600/fp_to_sint.ll b/test/CodeGen/R600/fp_to_sint.ll index f71b8515ef0..c583ec3429b 100644 --- a/test/CodeGen/R600/fp_to_sint.ll +++ b/test/CodeGen/R600/fp_to_sint.ll @@ -3,8 +3,8 @@ ; FUNC-LABEL: {{^}}fp_to_sint_i32: ; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} -; SI: V_CVT_I32_F32_e32 -; SI: S_ENDPGM +; SI: v_cvt_i32_f32_e32 +; SI: s_endpgm define void @fp_to_sint_i32 (i32 addrspace(1)* %out, float %in) { %conv = fptosi float %in to i32 store i32 %conv, i32 addrspace(1)* %out @@ -14,8 +14,8 @@ define void @fp_to_sint_i32 (i32 addrspace(1)* %out, float %in) { ; FUNC-LABEL: {{^}}fp_to_sint_v2i32: ; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} -; SI: V_CVT_I32_F32_e32 -; SI: V_CVT_I32_F32_e32 +; SI: v_cvt_i32_f32_e32 +; SI: v_cvt_i32_f32_e32 define void @fp_to_sint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) { %result = fptosi <2 x float> %in to <2 x i32> store <2 x i32> %result, <2 x i32> addrspace(1)* %out @@ -27,10 +27,10 @@ define void @fp_to_sint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) { ; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW]}} ; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} -; SI: V_CVT_I32_F32_e32 -; SI: V_CVT_I32_F32_e32 -; SI: V_CVT_I32_F32_e32 -; SI: V_CVT_I32_F32_e32 +; SI: v_cvt_i32_f32_e32 +; SI: v_cvt_i32_f32_e32 +; SI: v_cvt_i32_f32_e32 +; SI: v_cvt_i32_f32_e32 define void @fp_to_sint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %value = load <4 x float> addrspace(1) * %in %result = fptosi <4 x float> %value to <4 x i32> @@ -63,7 +63,7 @@ define void @fp_to_sint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspac ; EG-DAG: CNDE_INT ; Check that the compiler doesn't crash with a "cannot select" error -; SI: S_ENDPGM +; SI: s_endpgm define void @fp_to_sint_i64 (i64 addrspace(1)* %out, float %in) { entry: %0 = fptosi float %in to i64 @@ -115,7 +115,7 @@ entry: ; EG-DAG: CNDE_INT ; EG-DAG: CNDE_INT -; SI: S_ENDPGM +; SI: s_endpgm define void @fp_to_sint_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) { %conv = fptosi <2 x float> %x to <2 x i64> store <2 x i64> %conv, <2 x i64> addrspace(1)* %out @@ -208,7 +208,7 @@ define void @fp_to_sint_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) { ; EG-DAG: CNDE_INT ; EG-DAG: CNDE_INT -; SI: S_ENDPGM +; SI: s_endpgm define void @fp_to_sint_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) { %conv = fptosi <4 x float> %x to <4 x i64> store <4 x i64> %conv, <4 x i64> addrspace(1)* %out diff --git a/test/CodeGen/R600/fp_to_uint.f64.ll b/test/CodeGen/R600/fp_to_uint.f64.ll index 2fcb0e34afb..25859bb7fbf 100644 --- a/test/CodeGen/R600/fp_to_uint.f64.ll +++ b/test/CodeGen/R600/fp_to_uint.f64.ll @@ -4,7 +4,7 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone ; SI-LABEL: {{^}}fp_to_uint_i32_f64: -; SI: V_CVT_U32_F64_e32 +; SI: v_cvt_u32_f64_e32 define void @fp_to_uint_i32_f64(i32 addrspace(1)* %out, double %in) { %cast = fptoui double %in to i32 store i32 %cast, i32 addrspace(1)* %out, align 4 @@ -12,8 +12,8 @@ define void @fp_to_uint_i32_f64(i32 addrspace(1)* %out, double %in) { } ; SI-LABEL: @fp_to_uint_v2i32_v2f64 -; SI: V_CVT_U32_F64_e32 -; SI: V_CVT_U32_F64_e32 +; SI: v_cvt_u32_f64_e32 +; SI: v_cvt_u32_f64_e32 define void @fp_to_uint_v2i32_v2f64(<2 x i32> addrspace(1)* %out, <2 x double> %in) { %cast = fptoui <2 x double> %in to <2 x i32> store <2 x i32> %cast, <2 x i32> addrspace(1)* %out, align 8 @@ -21,10 +21,10 @@ define void @fp_to_uint_v2i32_v2f64(<2 x i32> addrspace(1)* %out, <2 x double> % } ; SI-LABEL: @fp_to_uint_v4i32_v4f64 -; SI: V_CVT_U32_F64_e32 -; SI: V_CVT_U32_F64_e32 -; SI: V_CVT_U32_F64_e32 -; SI: V_CVT_U32_F64_e32 +; SI: v_cvt_u32_f64_e32 +; SI: v_cvt_u32_f64_e32 +; SI: v_cvt_u32_f64_e32 +; SI: v_cvt_u32_f64_e32 define void @fp_to_uint_v4i32_v4f64(<4 x i32> addrspace(1)* %out, <4 x double> %in) { %cast = fptoui <4 x double> %in to <4 x i32> store <4 x i32> %cast, <4 x i32> addrspace(1)* %out, align 8 @@ -32,20 +32,20 @@ define void @fp_to_uint_v4i32_v4f64(<4 x i32> addrspace(1)* %out, <4 x double> % } ; FUNC-LABEL: @fp_to_uint_i64_f64 -; CI-DAG: BUFFER_LOAD_DWORDX2 [[VAL:v\[[0-9]+:[0-9]+\]]] -; CI-DAG: V_TRUNC_F64_e32 [[TRUNC:v\[[0-9]+:[0-9]+\]]], [[VAL]] -; CI-DAG: S_MOV_B32 s[[K0_LO:[0-9]+]], 0{{$}} -; CI-DAG: S_MOV_B32 s[[K0_HI:[0-9]+]], 0x3df00000 +; CI-DAG: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] +; CI-DAG: v_trunc_f64_e32 [[TRUNC:v\[[0-9]+:[0-9]+\]]], [[VAL]] +; CI-DAG: s_mov_b32 s[[K0_LO:[0-9]+]], 0{{$}} +; CI-DAG: s_mov_b32 s[[K0_HI:[0-9]+]], 0x3df00000 -; CI-DAG: V_MUL_F64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[VAL]], s{{\[}}[[K0_LO]]:[[K0_HI]]{{\]}} -; CI-DAG: V_FLOOR_F64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[MUL]] +; CI-DAG: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[VAL]], s{{\[}}[[K0_LO]]:[[K0_HI]]{{\]}} +; CI-DAG: v_floor_f64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[MUL]] -; CI-DAG: S_MOV_B32 s[[K1_HI:[0-9]+]], 0xc1f00000 +; CI-DAG: s_mov_b32 s[[K1_HI:[0-9]+]], 0xc1f00000 -; CI-DAG: V_FMA_F64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]{{\]}}, [[TRUNC]] -; CI-DAG: V_CVT_U32_F64_e32 v[[LO:[0-9]+]], [[FMA]] -; CI-DAG: V_CVT_U32_F64_e32 v[[HI:[0-9]+]], [[FLOOR]] -; CI: BUFFER_STORE_DWORDX2 v{{\[}}[[LO]]:[[HI]]{{\]}} +; CI-DAG: v_fma_f64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]{{\]}}, [[TRUNC]] +; CI-DAG: v_cvt_u32_f64_e32 v[[LO:[0-9]+]], [[FMA]] +; CI-DAG: v_cvt_u32_f64_e32 v[[HI:[0-9]+]], [[FLOOR]] +; CI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} define void @fp_to_uint_i64_f64(i64 addrspace(1)* %out, double addrspace(1)* %in) { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep = getelementptr double addrspace(1)* %in, i32 %tid diff --git a/test/CodeGen/R600/fp_to_uint.ll b/test/CodeGen/R600/fp_to_uint.ll index e92c2c651a3..91bf4b74974 100644 --- a/test/CodeGen/R600/fp_to_uint.ll +++ b/test/CodeGen/R600/fp_to_uint.ll @@ -3,8 +3,8 @@ ; FUNC-LABEL: {{^}}fp_to_uint_i32: ; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} -; SI: V_CVT_U32_F32_e32 -; SI: S_ENDPGM +; SI: v_cvt_u32_f32_e32 +; SI: s_endpgm define void @fp_to_uint_i32 (i32 addrspace(1)* %out, float %in) { %conv = fptoui float %in to i32 store i32 %conv, i32 addrspace(1)* %out @@ -14,8 +14,8 @@ define void @fp_to_uint_i32 (i32 addrspace(1)* %out, float %in) { ; FUNC-LABEL: {{^}}fp_to_uint_v2i32: ; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; SI: V_CVT_U32_F32_e32 -; SI: V_CVT_U32_F32_e32 +; SI: v_cvt_u32_f32_e32 +; SI: v_cvt_u32_f32_e32 define void @fp_to_uint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) { %result = fptoui <2 x float> %in to <2 x i32> @@ -28,10 +28,10 @@ define void @fp_to_uint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) { ; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} -; SI: V_CVT_U32_F32_e32 -; SI: V_CVT_U32_F32_e32 -; SI: V_CVT_U32_F32_e32 -; SI: V_CVT_U32_F32_e32 +; SI: v_cvt_u32_f32_e32 +; SI: v_cvt_u32_f32_e32 +; SI: v_cvt_u32_f32_e32 +; SI: v_cvt_u32_f32_e32 define void @fp_to_uint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %value = load <4 x float> addrspace(1) * %in @@ -63,7 +63,7 @@ define void @fp_to_uint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspac ; EG-DAG: CNDE_INT ; EG-DAG: CNDE_INT -; SI: S_ENDPGM +; SI: s_endpgm define void @fp_to_uint_i64(i64 addrspace(1)* %out, float %x) { %conv = fptoui float %x to i64 store i64 %conv, i64 addrspace(1)* %out @@ -114,7 +114,7 @@ define void @fp_to_uint_i64(i64 addrspace(1)* %out, float %x) { ; EG-DAG: CNDE_INT ; EG-DAG: CNDE_INT -; SI: S_ENDPGM +; SI: s_endpgm define void @fp_to_uint_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) { %conv = fptoui <2 x float> %x to <2 x i64> store <2 x i64> %conv, <2 x i64> addrspace(1)* %out @@ -207,7 +207,7 @@ define void @fp_to_uint_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) { ; EG-DAG: CNDE_INT ; EG-DAG: CNDE_INT -; SI: S_ENDPGM +; SI: s_endpgm define void @fp_to_uint_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) { %conv = fptoui <4 x float> %x to <4 x i64> store <4 x i64> %conv, <4 x i64> addrspace(1)* %out diff --git a/test/CodeGen/R600/fpext.ll b/test/CodeGen/R600/fpext.ll index 4bad8e913b9..418395ff8e7 100644 --- a/test/CodeGen/R600/fpext.ll +++ b/test/CodeGen/R600/fpext.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=CHECK ; CHECK: {{^}}fpext: -; CHECK: V_CVT_F64_F32_e32 +; CHECK: v_cvt_f64_f32_e32 define void @fpext(double addrspace(1)* %out, float %in) { %result = fpext float %in to double store double %result, double addrspace(1)* %out diff --git a/test/CodeGen/R600/fptrunc.ll b/test/CodeGen/R600/fptrunc.ll index 05452d1e86e..8ac8d3bf48d 100644 --- a/test/CodeGen/R600/fptrunc.ll +++ b/test/CodeGen/R600/fptrunc.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=CHECK ; CHECK: {{^}}fptrunc: -; CHECK: V_CVT_F32_F64_e32 +; CHECK: v_cvt_f32_f64_e32 define void @fptrunc(float addrspace(1)* %out, double %in) { %result = fptrunc double %in to float store float %result, float addrspace(1)* %out diff --git a/test/CodeGen/R600/frem.ll b/test/CodeGen/R600/frem.ll index a520e0a83ea..c846a77e3b2 100644 --- a/test/CodeGen/R600/frem.ll +++ b/test/CodeGen/R600/frem.ll @@ -1,16 +1,16 @@ ; RUN: llc -march=r600 -mcpu=SI -enable-misched < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}frem_f32: -; SI-DAG: BUFFER_LOAD_DWORD [[X:v[0-9]+]], {{.*$}} -; SI-DAG: BUFFER_LOAD_DWORD [[Y:v[0-9]+]], {{.*}} offset:0x10 -; SI-DAG: V_CMP -; SI-DAG: V_MUL_F32 -; SI: V_RCP_F32_e32 -; SI: V_MUL_F32_e32 -; SI: V_MUL_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_MAD_F32 -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{.*$}} +; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{.*}} offset:0x10 +; SI-DAG: v_cmp +; SI-DAG: v_mul_f32 +; SI: v_rcp_f32_e32 +; SI: v_mul_f32_e32 +; SI: v_mul_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_mad_f32 +; SI: s_endpgm define void @frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1, float addrspace(1)* %in2) #0 { %gep2 = getelementptr float addrspace(1)* %in2, i32 4 @@ -22,14 +22,14 @@ define void @frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1, } ; FUNC-LABEL: {{^}}unsafe_frem_f32: -; SI: BUFFER_LOAD_DWORD [[Y:v[0-9]+]], {{.*}} offset:0x10 -; SI: BUFFER_LOAD_DWORD [[X:v[0-9]+]], {{.*}} -; SI: V_RCP_F32_e32 [[INVY:v[0-9]+]], [[Y]] -; SI: V_MUL_F32_e32 [[DIV:v[0-9]+]], [[INVY]], [[X]] -; SI: V_TRUNC_F32_e32 [[TRUNC:v[0-9]+]], [[DIV]] -; SI: V_MAD_F32 [[RESULT:v[0-9]+]], -[[TRUNC]], [[Y]], [[X]] -; SI: BUFFER_STORE_DWORD [[RESULT]] -; SI: S_ENDPGM +; SI: buffer_load_dword [[Y:v[0-9]+]], {{.*}} offset:0x10 +; SI: buffer_load_dword [[X:v[0-9]+]], {{.*}} +; SI: v_rcp_f32_e32 [[INVY:v[0-9]+]], [[Y]] +; SI: v_mul_f32_e32 [[DIV:v[0-9]+]], [[INVY]], [[X]] +; SI: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[DIV]] +; SI: v_mad_f32 [[RESULT:v[0-9]+]], -[[TRUNC]], [[Y]], [[X]] +; SI: buffer_store_dword [[RESULT]] +; SI: s_endpgm define void @unsafe_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1, float addrspace(1)* %in2) #1 { %gep2 = getelementptr float addrspace(1)* %in2, i32 4 @@ -44,7 +44,7 @@ define void @unsafe_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1, ; correctly ; FUNC-LABEL: {{^}}frem_f64: -; SI: S_ENDPGM +; SI: s_endpgm define void @frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1, double addrspace(1)* %in2) #0 { %r0 = load double addrspace(1)* %in1, align 8 @@ -55,11 +55,11 @@ define void @frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1, } ; FUNC-LABEL: {{^}}unsafe_frem_f64: -; SI: V_RCP_F64_e32 -; SI: V_MUL_F64 -; SI: V_BFE_U32 -; SI: V_FMA_F64 -; SI: S_ENDPGM +; SI: v_rcp_f64_e32 +; SI: v_mul_f64 +; SI: v_bfe_u32 +; SI: v_fma_f64 +; SI: s_endpgm define void @unsafe_frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1, double addrspace(1)* %in2) #1 { %r0 = load double addrspace(1)* %in1, align 8 diff --git a/test/CodeGen/R600/fsqrt.ll b/test/CodeGen/R600/fsqrt.ll index c8eb3f1dbcb..1f91faf52c0 100644 --- a/test/CodeGen/R600/fsqrt.ll +++ b/test/CodeGen/R600/fsqrt.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; CHECK: {{^}}fsqrt_f32: -; CHECK: V_SQRT_F32_e32 {{v[0-9]+, v[0-9]+}} +; CHECK: v_sqrt_f32_e32 {{v[0-9]+, v[0-9]+}} define void @fsqrt_f32(float addrspace(1)* %out, float addrspace(1)* %in) { %r0 = load float addrspace(1)* %in @@ -11,7 +11,7 @@ define void @fsqrt_f32(float addrspace(1)* %out, float addrspace(1)* %in) { } ; CHECK: {{^}}fsqrt_f64: -; CHECK: V_SQRT_F64_e32 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} +; CHECK: v_sqrt_f64_e32 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} define void @fsqrt_f64(double addrspace(1)* %out, double addrspace(1)* %in) { %r0 = load double addrspace(1)* %in diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll index 68f44881b66..6e5ccf1af48 100644 --- a/test/CodeGen/R600/fsub.ll +++ b/test/CodeGen/R600/fsub.ll @@ -3,7 +3,7 @@ ; FUNC-LABEL: {{^}}v_fsub_f32: -; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} define void @v_fsub_f32(float addrspace(1)* %out, float addrspace(1)* %in) { %b_ptr = getelementptr float addrspace(1)* %in, i32 1 %a = load float addrspace(1)* %in, align 4 @@ -16,7 +16,7 @@ define void @v_fsub_f32(float addrspace(1)* %out, float addrspace(1)* %in) { ; FUNC-LABEL: {{^}}s_fsub_f32: ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W -; SI: V_SUB_F32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} +; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} define void @s_fsub_f32(float addrspace(1)* %out, float %a, float %b) { %sub = fsub float %a, %b store float %sub, float addrspace(1)* %out, align 4 @@ -32,8 +32,8 @@ declare void @llvm.AMDGPU.store.output(float, i32) ; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y ; FIXME: Should be using SGPR directly for first operand -; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} -; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} define void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { %sub = fsub <2 x float> %a, %b store <2 x float> %sub, <2 x float> addrspace(1)* %out, align 8 @@ -46,10 +46,10 @@ define void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x flo ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} -; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} -; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} -; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} -; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} define void @v_fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 %a = load <4 x float> addrspace(1)* %in, align 16 @@ -62,11 +62,11 @@ define void @v_fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace( ; FIXME: Should be using SGPR directly for first operand ; FUNC-LABEL: {{^}}s_fsub_v4f32: -; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} -; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} -; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} -; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} -; SI: S_ENDPGM +; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; SI: s_endpgm define void @s_fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) { %result = fsub <4 x float> %a, %b store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16 diff --git a/test/CodeGen/R600/fsub64.ll b/test/CodeGen/R600/fsub64.ll index b9bee2f6aff..eca1b620ee2 100644 --- a/test/CodeGen/R600/fsub64.ll +++ b/test/CodeGen/R600/fsub64.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=r600 -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; SI-LABEL: {{^}}fsub_f64: -; SI: V_ADD_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}} +; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}} define void @fsub_f64(double addrspace(1)* %out, double addrspace(1)* %in1, double addrspace(1)* %in2) { %r0 = load double addrspace(1)* %in1 diff --git a/test/CodeGen/R600/ftrunc.f64.ll b/test/CodeGen/R600/ftrunc.f64.ll index c4e589212ea..fba6154ed10 100644 --- a/test/CodeGen/R600/ftrunc.f64.ll +++ b/test/CodeGen/R600/ftrunc.f64.ll @@ -9,9 +9,9 @@ declare <8 x double> @llvm.trunc.v8f64(<8 x double>) nounwind readnone declare <16 x double> @llvm.trunc.v16f64(<16 x double>) nounwind readnone ; FUNC-LABEL: {{^}}v_ftrunc_f64: -; CI: V_TRUNC_F64 -; SI: V_BFE_U32 {{v[0-9]+}}, {{v[0-9]+}}, 20, 11 -; SI: S_ENDPGM +; CI: v_trunc_f64 +; SI: v_bfe_u32 {{v[0-9]+}}, {{v[0-9]+}}, 20, 11 +; SI: s_endpgm define void @v_ftrunc_f64(double addrspace(1)* %out, double addrspace(1)* %in) { %x = load double addrspace(1)* %in, align 8 %y = call double @llvm.trunc.f64(double %x) nounwind readnone @@ -20,21 +20,21 @@ define void @v_ftrunc_f64(double addrspace(1)* %out, double addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}ftrunc_f64: -; CI: V_TRUNC_F64_e32 +; CI: v_trunc_f64_e32 -; SI: S_BFE_U32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014 -; SI: S_ADD_I32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01 -; SI: S_LSHR_B64 -; SI: S_NOT_B64 -; SI: S_AND_B64 -; SI: S_AND_B32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 -; SI: CMP_LT_I32 -; SI: CNDMASK_B32 -; SI: CNDMASK_B32 -; SI: CMP_GT_I32 -; SI: CNDMASK_B32 -; SI: CNDMASK_B32 -; SI: S_ENDPGM +; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014 +; SI: s_add_i32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01 +; SI: s_lshr_b64 +; SI: s_not_b64 +; SI: s_and_b64 +; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 +; SI: cmp_lt_i32 +; SI: cndmask_b32 +; SI: cndmask_b32 +; SI: cmp_gt_i32 +; SI: cndmask_b32 +; SI: cndmask_b32 +; SI: s_endpgm define void @ftrunc_f64(double addrspace(1)* %out, double %x) { %y = call double @llvm.trunc.f64(double %x) nounwind readnone store double %y, double addrspace(1)* %out @@ -42,8 +42,8 @@ define void @ftrunc_f64(double addrspace(1)* %out, double %x) { } ; FUNC-LABEL: {{^}}ftrunc_v2f64: -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 define void @ftrunc_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) { %y = call <2 x double> @llvm.trunc.v2f64(<2 x double> %x) nounwind readnone store <2 x double> %y, <2 x double> addrspace(1)* %out @@ -51,9 +51,9 @@ define void @ftrunc_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) { } ; FIXME-FUNC-LABEL: {{^}}ftrunc_v3f64: -; FIXME-CI: V_TRUNC_F64_e32 -; FIXME-CI: V_TRUNC_F64_e32 -; FIXME-CI: V_TRUNC_F64_e32 +; FIXME-CI: v_trunc_f64_e32 +; FIXME-CI: v_trunc_f64_e32 +; FIXME-CI: v_trunc_f64_e32 ; define void @ftrunc_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) { ; %y = call <3 x double> @llvm.trunc.v3f64(<3 x double> %x) nounwind readnone ; store <3 x double> %y, <3 x double> addrspace(1)* %out @@ -61,10 +61,10 @@ define void @ftrunc_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) { ; } ; FUNC-LABEL: {{^}}ftrunc_v4f64: -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 define void @ftrunc_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) { %y = call <4 x double> @llvm.trunc.v4f64(<4 x double> %x) nounwind readnone store <4 x double> %y, <4 x double> addrspace(1)* %out @@ -72,14 +72,14 @@ define void @ftrunc_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) { } ; FUNC-LABEL: {{^}}ftrunc_v8f64: -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 define void @ftrunc_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) { %y = call <8 x double> @llvm.trunc.v8f64(<8 x double> %x) nounwind readnone store <8 x double> %y, <8 x double> addrspace(1)* %out @@ -87,22 +87,22 @@ define void @ftrunc_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) { } ; FUNC-LABEL: {{^}}ftrunc_v16f64: -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 -; CI: V_TRUNC_F64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 +; CI: v_trunc_f64_e32 define void @ftrunc_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %x) { %y = call <16 x double> @llvm.trunc.v16f64(<16 x double> %x) nounwind readnone store <16 x double> %y, <16 x double> addrspace(1)* %out diff --git a/test/CodeGen/R600/ftrunc.ll b/test/CodeGen/R600/ftrunc.ll index 93e32bfac84..0eb1d7d3bce 100644 --- a/test/CodeGen/R600/ftrunc.ll +++ b/test/CodeGen/R600/ftrunc.ll @@ -10,7 +10,7 @@ declare <16 x float> @llvm.trunc.v16f32(<16 x float>) nounwind readnone ; FUNC-LABEL: {{^}}ftrunc_f32: ; EG: TRUNC -; SI: V_TRUNC_F32_e32 +; SI: v_trunc_f32_e32 define void @ftrunc_f32(float addrspace(1)* %out, float %x) { %y = call float @llvm.trunc.f32(float %x) nounwind readnone store float %y, float addrspace(1)* %out @@ -20,8 +20,8 @@ define void @ftrunc_f32(float addrspace(1)* %out, float %x) { ; FUNC-LABEL: {{^}}ftrunc_v2f32: ; EG: TRUNC ; EG: TRUNC -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 define void @ftrunc_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %x) { %y = call <2 x float> @llvm.trunc.v2f32(<2 x float> %x) nounwind readnone store <2 x float> %y, <2 x float> addrspace(1)* %out @@ -32,9 +32,9 @@ define void @ftrunc_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %x) { ; FIXME-EG: TRUNC ; FIXME-EG: TRUNC ; FIXME-EG: TRUNC -; FIXME-SI: V_TRUNC_F32_e32 -; FIXME-SI: V_TRUNC_F32_e32 -; FIXME-SI: V_TRUNC_F32_e32 +; FIXME-SI: v_trunc_f32_e32 +; FIXME-SI: v_trunc_f32_e32 +; FIXME-SI: v_trunc_f32_e32 ; define void @ftrunc_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %x) { ; %y = call <3 x float> @llvm.trunc.v3f32(<3 x float> %x) nounwind readnone ; store <3 x float> %y, <3 x float> addrspace(1)* %out @@ -46,10 +46,10 @@ define void @ftrunc_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %x) { ; EG: TRUNC ; EG: TRUNC ; EG: TRUNC -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 define void @ftrunc_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %x) { %y = call <4 x float> @llvm.trunc.v4f32(<4 x float> %x) nounwind readnone store <4 x float> %y, <4 x float> addrspace(1)* %out @@ -65,14 +65,14 @@ define void @ftrunc_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %x) { ; EG: TRUNC ; EG: TRUNC ; EG: TRUNC -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 define void @ftrunc_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %x) { %y = call <8 x float> @llvm.trunc.v8f32(<8 x float> %x) nounwind readnone store <8 x float> %y, <8 x float> addrspace(1)* %out @@ -96,22 +96,22 @@ define void @ftrunc_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %x) { ; EG: TRUNC ; EG: TRUNC ; EG: TRUNC -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 -; SI: V_TRUNC_F32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 +; SI: v_trunc_f32_e32 define void @ftrunc_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %x) { %y = call <16 x float> @llvm.trunc.v16f32(<16 x float> %x) nounwind readnone store <16 x float> %y, <16 x float> addrspace(1)* %out diff --git a/test/CodeGen/R600/gep-address-space.ll b/test/CodeGen/R600/gep-address-space.ll index 19d527f1b89..036daafd0e4 100644 --- a/test/CodeGen/R600/gep-address-space.ll +++ b/test/CodeGen/R600/gep-address-space.ll @@ -3,8 +3,8 @@ define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind { ; CHECK-LABEL: {{^}}use_gep_address_space: -; CHECK: V_MOV_B32_e32 [[PTR:v[0-9]+]], s{{[0-9]+}} -; CHECK: DS_WRITE_B32 [[PTR]], v{{[0-9]+}} offset:64 +; CHECK: v_mov_b32_e32 [[PTR:v[0-9]+]], s{{[0-9]+}} +; CHECK: ds_write_b32 [[PTR]], v{{[0-9]+}} offset:64 %p = getelementptr [1024 x i32] addrspace(3)* %array, i16 0, i16 16 store i32 99, i32 addrspace(3)* %p ret void @@ -14,9 +14,9 @@ define void @use_gep_address_space_large_offset([1024 x i32] addrspace(3)* %arra ; CHECK-LABEL: {{^}}use_gep_address_space_large_offset: ; The LDS offset will be 65536 bytes, which is larger than the size of LDS on ; SI, which is why it is being OR'd with the base pointer. -; SI: S_OR_B32 -; CI: S_ADD_I32 -; CHECK: DS_WRITE_B32 +; SI: s_or_b32 +; CI: s_add_i32 +; CHECK: ds_write_b32 %p = getelementptr [1024 x i32] addrspace(3)* %array, i16 0, i16 16384 store i32 99, i32 addrspace(3)* %p ret void @@ -24,10 +24,10 @@ define void @use_gep_address_space_large_offset([1024 x i32] addrspace(3)* %arra define void @gep_as_vector_v4(<4 x [1024 x i32] addrspace(3)*> %array) nounwind { ; CHECK-LABEL: {{^}}gep_as_vector_v4: -; CHECK: S_ADD_I32 -; CHECK: S_ADD_I32 -; CHECK: S_ADD_I32 -; CHECK: S_ADD_I32 +; CHECK: s_add_i32 +; CHECK: s_add_i32 +; CHECK: s_add_i32 +; CHECK: s_add_i32 %p = getelementptr <4 x [1024 x i32] addrspace(3)*> %array, <4 x i16> zeroinitializer, <4 x i16> %p0 = extractelement <4 x i32 addrspace(3)*> %p, i32 0 %p1 = extractelement <4 x i32 addrspace(3)*> %p, i32 1 @@ -42,8 +42,8 @@ define void @gep_as_vector_v4(<4 x [1024 x i32] addrspace(3)*> %array) nounwind define void @gep_as_vector_v2(<2 x [1024 x i32] addrspace(3)*> %array) nounwind { ; CHECK-LABEL: {{^}}gep_as_vector_v2: -; CHECK: S_ADD_I32 -; CHECK: S_ADD_I32 +; CHECK: s_add_i32 +; CHECK: s_add_i32 %p = getelementptr <2 x [1024 x i32] addrspace(3)*> %array, <2 x i16> zeroinitializer, <2 x i16> %p0 = extractelement <2 x i32 addrspace(3)*> %p, i32 0 %p1 = extractelement <2 x i32 addrspace(3)*> %p, i32 1 diff --git a/test/CodeGen/R600/global_atomics.ll b/test/CodeGen/R600/global_atomics.ll index 255f9ebba4f..533a96486e1 100644 --- a/test/CodeGen/R600/global_atomics.ll +++ b/test/CodeGen/R600/global_atomics.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s ; FUNC-LABEL: {{^}}atomic_add_i32_offset: -; SI: BUFFER_ATOMIC_ADD v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} +; SI: buffer_atomic_add v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} define void @atomic_add_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -10,8 +10,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_add_i32_ret_offset: -; SI: BUFFER_ATOMIC_ADD [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_add [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_add_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -21,7 +21,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_add_i32_addr64_offset: -; SI: BUFFER_ATOMIC_ADD v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} +; SI: buffer_atomic_add v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} define void @atomic_add_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -31,8 +31,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_add_i32_ret_addr64_offset: -; SI: BUFFER_ATOMIC_ADD [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_add_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -43,7 +43,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_add_i32: -; SI: BUFFER_ATOMIC_ADD v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; SI: buffer_atomic_add v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_add_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile add i32 addrspace(1)* %out, i32 %in seq_cst @@ -51,8 +51,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_add_i32_ret: -; SI: BUFFER_ATOMIC_ADD [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_add [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; SI: buffer_store_dword [[RET]] define void @atomic_add_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile add i32 addrspace(1)* %out, i32 %in seq_cst @@ -61,7 +61,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_add_i32_addr64: -; SI: BUFFER_ATOMIC_ADD v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; SI: buffer_atomic_add v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} define void @atomic_add_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -70,8 +70,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_add_i32_ret_addr64: -; SI: BUFFER_ATOMIC_ADD [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_add_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -81,7 +81,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_and_i32_offset: -; SI: BUFFER_ATOMIC_AND v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} +; SI: buffer_atomic_and v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} define void @atomic_and_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -90,8 +90,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_and_i32_ret_offset: -; SI: BUFFER_ATOMIC_AND [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_and [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_and_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -101,7 +101,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_and_i32_addr64_offset: -; SI: BUFFER_ATOMIC_AND v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} +; SI: buffer_atomic_and v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} define void @atomic_and_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -111,8 +111,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_and_i32_ret_addr64_offset: -; SI: BUFFER_ATOMIC_AND [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_and_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -123,7 +123,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_and_i32: -; SI: BUFFER_ATOMIC_AND v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; SI: buffer_atomic_and v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_and_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile and i32 addrspace(1)* %out, i32 %in seq_cst @@ -131,8 +131,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_and_i32_ret: -; SI: BUFFER_ATOMIC_AND [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_and [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; SI: buffer_store_dword [[RET]] define void @atomic_and_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile and i32 addrspace(1)* %out, i32 %in seq_cst @@ -141,7 +141,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_and_i32_addr64: -; SI: BUFFER_ATOMIC_AND v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; SI: buffer_atomic_and v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} define void @atomic_and_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -150,8 +150,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_and_i32_ret_addr64: -; SI: BUFFER_ATOMIC_AND [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_and_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -161,7 +161,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_sub_i32_offset: -; SI: BUFFER_ATOMIC_SUB v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} +; SI: buffer_atomic_sub v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} define void @atomic_sub_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -170,8 +170,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_sub_i32_ret_offset: -; SI: BUFFER_ATOMIC_SUB [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_sub [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_sub_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -181,7 +181,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_sub_i32_addr64_offset: -; SI: BUFFER_ATOMIC_SUB v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} +; SI: buffer_atomic_sub v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} define void @atomic_sub_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -191,8 +191,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_sub_i32_ret_addr64_offset: -; SI: BUFFER_ATOMIC_SUB [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_sub_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -203,7 +203,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_sub_i32: -; SI: BUFFER_ATOMIC_SUB v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; SI: buffer_atomic_sub v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_sub_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile sub i32 addrspace(1)* %out, i32 %in seq_cst @@ -211,8 +211,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_sub_i32_ret: -; SI: BUFFER_ATOMIC_SUB [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_sub [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; SI: buffer_store_dword [[RET]] define void @atomic_sub_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile sub i32 addrspace(1)* %out, i32 %in seq_cst @@ -221,7 +221,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_sub_i32_addr64: -; SI: BUFFER_ATOMIC_SUB v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; SI: buffer_atomic_sub v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} define void @atomic_sub_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -230,8 +230,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_sub_i32_ret_addr64: -; SI: BUFFER_ATOMIC_SUB [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_sub_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -241,7 +241,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_max_i32_offset: -; SI: BUFFER_ATOMIC_SMAX v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} +; SI: buffer_atomic_smax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} define void @atomic_max_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -250,8 +250,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_max_i32_ret_offset: -; SI: BUFFER_ATOMIC_SMAX [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_smax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_max_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -261,7 +261,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_max_i32_addr64_offset: -; SI: BUFFER_ATOMIC_SMAX v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} +; SI: buffer_atomic_smax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} define void @atomic_max_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -271,8 +271,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_max_i32_ret_addr64_offset: -; SI: BUFFER_ATOMIC_SMAX [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_max_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -283,7 +283,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_max_i32: -; SI: BUFFER_ATOMIC_SMAX v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; SI: buffer_atomic_smax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_max_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile max i32 addrspace(1)* %out, i32 %in seq_cst @@ -291,8 +291,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_max_i32_ret: -; SI: BUFFER_ATOMIC_SMAX [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_smax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; SI: buffer_store_dword [[RET]] define void @atomic_max_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile max i32 addrspace(1)* %out, i32 %in seq_cst @@ -301,7 +301,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_max_i32_addr64: -; SI: BUFFER_ATOMIC_SMAX v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; SI: buffer_atomic_smax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} define void @atomic_max_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -310,8 +310,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_max_i32_ret_addr64: -; SI: BUFFER_ATOMIC_SMAX [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_max_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -321,7 +321,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umax_i32_offset: -; SI: BUFFER_ATOMIC_UMAX v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} +; SI: buffer_atomic_umax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} define void @atomic_umax_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -330,8 +330,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umax_i32_ret_offset: -; SI: BUFFER_ATOMIC_UMAX [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_umax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_umax_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -341,7 +341,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umax_i32_addr64_offset: -; SI: BUFFER_ATOMIC_UMAX v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} +; SI: buffer_atomic_umax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} define void @atomic_umax_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -351,8 +351,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umax_i32_ret_addr64_offset: -; SI: BUFFER_ATOMIC_UMAX [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_umax_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -363,7 +363,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umax_i32: -; SI: BUFFER_ATOMIC_UMAX v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; SI: buffer_atomic_umax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_umax_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile umax i32 addrspace(1)* %out, i32 %in seq_cst @@ -371,8 +371,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umax_i32_ret: -; SI: BUFFER_ATOMIC_UMAX [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_umax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; SI: buffer_store_dword [[RET]] define void @atomic_umax_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile umax i32 addrspace(1)* %out, i32 %in seq_cst @@ -381,7 +381,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umax_i32_addr64: -; SI: BUFFER_ATOMIC_UMAX v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; SI: buffer_atomic_umax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} define void @atomic_umax_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -390,8 +390,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umax_i32_ret_addr64: -; SI: BUFFER_ATOMIC_UMAX [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_umax_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -401,7 +401,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_min_i32_offset: -; SI: BUFFER_ATOMIC_SMIN v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} +; SI: buffer_atomic_smin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} define void @atomic_min_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -410,8 +410,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_min_i32_ret_offset: -; SI: BUFFER_ATOMIC_SMIN [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_smin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_min_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -421,7 +421,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_min_i32_addr64_offset: -; SI: BUFFER_ATOMIC_SMIN v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} +; SI: buffer_atomic_smin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} define void @atomic_min_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -431,8 +431,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_min_i32_ret_addr64_offset: -; SI: BUFFER_ATOMIC_SMIN [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_min_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -443,7 +443,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_min_i32: -; SI: BUFFER_ATOMIC_SMIN v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; SI: buffer_atomic_smin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_min_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile min i32 addrspace(1)* %out, i32 %in seq_cst @@ -451,8 +451,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_min_i32_ret: -; SI: BUFFER_ATOMIC_SMIN [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_smin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; SI: buffer_store_dword [[RET]] define void @atomic_min_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile min i32 addrspace(1)* %out, i32 %in seq_cst @@ -461,7 +461,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_min_i32_addr64: -; SI: BUFFER_ATOMIC_SMIN v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; SI: buffer_atomic_smin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} define void @atomic_min_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -470,8 +470,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_min_i32_ret_addr64: -; SI: BUFFER_ATOMIC_SMIN [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_min_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -481,7 +481,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umin_i32_offset: -; SI: BUFFER_ATOMIC_UMIN v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} +; SI: buffer_atomic_umin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} define void @atomic_umin_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -490,8 +490,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umin_i32_ret_offset: -; SI: BUFFER_ATOMIC_UMIN [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_umin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_umin_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -501,7 +501,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umin_i32_addr64_offset: -; SI: BUFFER_ATOMIC_UMIN v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} +; SI: buffer_atomic_umin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} define void @atomic_umin_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -511,8 +511,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umin_i32_ret_addr64_offset: -; SI: BUFFER_ATOMIC_UMIN [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_umin_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -523,7 +523,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umin_i32: -; SI: BUFFER_ATOMIC_UMIN v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; SI: buffer_atomic_umin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_umin_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile umin i32 addrspace(1)* %out, i32 %in seq_cst @@ -531,8 +531,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umin_i32_ret: -; SI: BUFFER_ATOMIC_UMIN [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_umin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; SI: buffer_store_dword [[RET]] define void @atomic_umin_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile umin i32 addrspace(1)* %out, i32 %in seq_cst @@ -541,7 +541,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umin_i32_addr64: -; SI: BUFFER_ATOMIC_UMIN v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; SI: buffer_atomic_umin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} define void @atomic_umin_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -550,8 +550,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umin_i32_ret_addr64: -; SI: BUFFER_ATOMIC_UMIN [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_umin_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -561,7 +561,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_or_i32_offset: -; SI: BUFFER_ATOMIC_OR v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} +; SI: buffer_atomic_or v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} define void @atomic_or_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -570,8 +570,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_or_i32_ret_offset: -; SI: BUFFER_ATOMIC_OR [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_or [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_or_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -581,7 +581,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_or_i32_addr64_offset: -; SI: BUFFER_ATOMIC_OR v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} +; SI: buffer_atomic_or v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} define void @atomic_or_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -591,8 +591,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_or_i32_ret_addr64_offset: -; SI: BUFFER_ATOMIC_OR [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_or_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -603,7 +603,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_or_i32: -; SI: BUFFER_ATOMIC_OR v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; SI: buffer_atomic_or v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_or_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile or i32 addrspace(1)* %out, i32 %in seq_cst @@ -611,8 +611,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_or_i32_ret: -; SI: BUFFER_ATOMIC_OR [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_or [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; SI: buffer_store_dword [[RET]] define void @atomic_or_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile or i32 addrspace(1)* %out, i32 %in seq_cst @@ -621,7 +621,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_or_i32_addr64: -; SI: BUFFER_ATOMIC_OR v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; SI: buffer_atomic_or v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} define void @atomic_or_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -630,8 +630,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_or_i32_ret_addr64: -; SI: BUFFER_ATOMIC_OR [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_or_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -641,7 +641,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xchg_i32_offset: -; SI: BUFFER_ATOMIC_SWAP v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} +; SI: buffer_atomic_swap v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} define void @atomic_xchg_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -650,8 +650,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xchg_i32_ret_offset: -; SI: BUFFER_ATOMIC_SWAP [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_swap [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_xchg_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -661,7 +661,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xchg_i32_addr64_offset: -; SI: BUFFER_ATOMIC_SWAP v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} +; SI: buffer_atomic_swap v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} define void @atomic_xchg_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -671,8 +671,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xchg_i32_ret_addr64_offset: -; SI: BUFFER_ATOMIC_SWAP [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_xchg_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -683,7 +683,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xchg_i32: -; SI: BUFFER_ATOMIC_SWAP v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; SI: buffer_atomic_swap v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_xchg_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile xchg i32 addrspace(1)* %out, i32 %in seq_cst @@ -691,8 +691,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xchg_i32_ret: -; SI: BUFFER_ATOMIC_SWAP [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_swap [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; SI: buffer_store_dword [[RET]] define void @atomic_xchg_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile xchg i32 addrspace(1)* %out, i32 %in seq_cst @@ -701,7 +701,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xchg_i32_addr64: -; SI: BUFFER_ATOMIC_SWAP v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; SI: buffer_atomic_swap v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} define void @atomic_xchg_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -710,8 +710,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xchg_i32_ret_addr64: -; SI: BUFFER_ATOMIC_SWAP [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_xchg_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -721,7 +721,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xor_i32_offset: -; SI: BUFFER_ATOMIC_XOR v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} +; SI: buffer_atomic_xor v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10{{$}} define void @atomic_xor_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -730,8 +730,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xor_i32_ret_offset: -; SI: BUFFER_ATOMIC_XOR [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_xor [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:0x10 glc {{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_xor_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32 addrspace(1)* %out, i32 4 @@ -741,7 +741,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xor_i32_addr64_offset: -; SI: BUFFER_ATOMIC_XOR v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} +; SI: buffer_atomic_xor v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10{{$}} define void @atomic_xor_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -751,8 +751,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xor_i32_ret_addr64_offset: -; SI: BUFFER_ATOMIC_XOR [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:0x10 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_xor_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -763,7 +763,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xor_i32: -; SI: BUFFER_ATOMIC_XOR v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; SI: buffer_atomic_xor v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_xor_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile xor i32 addrspace(1)* %out, i32 %in seq_cst @@ -771,8 +771,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xor_i32_ret: -; SI: BUFFER_ATOMIC_XOR [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_xor [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; SI: buffer_store_dword [[RET]] define void @atomic_xor_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile xor i32 addrspace(1)* %out, i32 %in seq_cst @@ -781,7 +781,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xor_i32_addr64: -; SI: BUFFER_ATOMIC_XOR v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; SI: buffer_atomic_xor v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} define void @atomic_xor_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index @@ -790,8 +790,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xor_i32_ret_addr64: -; SI: BUFFER_ATOMIC_XOR [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: BUFFER_STORE_DWORD [[RET]] +; SI: buffer_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; SI: buffer_store_dword [[RET]] define void @atomic_xor_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32 addrspace(1)* %out, i64 %index diff --git a/test/CodeGen/R600/gv-const-addrspace-fail.ll b/test/CodeGen/R600/gv-const-addrspace-fail.ll index c377670a12f..905948fd9ce 100644 --- a/test/CodeGen/R600/gv-const-addrspace-fail.ll +++ b/test/CodeGen/R600/gv-const-addrspace-fail.ll @@ -6,8 +6,8 @@ ; FUNC-LABEL: {{^}}test_i8: ; EG: CF_END -; SI: BUFFER_STORE_BYTE -; SI: S_ENDPGM +; SI: buffer_store_byte +; SI: s_endpgm define void @test_i8( i32 %s, i8 addrspace(1)* %out) #3 { %arrayidx = getelementptr inbounds [1 x i8] addrspace(2)* @a, i32 0, i32 %s %1 = load i8 addrspace(2)* %arrayidx, align 1 @@ -19,8 +19,8 @@ define void @test_i8( i32 %s, i8 addrspace(1)* %out) #3 { ; FUNC-LABEL: {{^}}test_i16: ; EG: CF_END -; SI: BUFFER_STORE_SHORT -; SI: S_ENDPGM +; SI: buffer_store_short +; SI: s_endpgm define void @test_i16( i32 %s, i16 addrspace(1)* %out) #3 { %arrayidx = getelementptr inbounds [1 x i16] addrspace(2)* @b, i32 0, i32 %s %1 = load i16 addrspace(2)* %arrayidx, align 2 diff --git a/test/CodeGen/R600/gv-const-addrspace.ll b/test/CodeGen/R600/gv-const-addrspace.ll index 02c1ea16d7e..6aa20b8348e 100644 --- a/test/CodeGen/R600/gv-const-addrspace.ll +++ b/test/CodeGen/R600/gv-const-addrspace.ll @@ -7,8 +7,8 @@ @float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.0, float 1.0, float 2.0, float 3.0, float 4.0], align 4 ; FUNC-LABEL: {{^}}float: -; FIXME: We should be using S_LOAD_DWORD here. -; SI: BUFFER_LOAD_DWORD +; FIXME: We should be using s_load_dword here. +; SI: buffer_load_dword ; EG-DAG: MOV {{\** *}}T2.X ; EG-DAG: MOV {{\** *}}T3.X @@ -29,8 +29,8 @@ entry: ; FUNC-LABEL: {{^}}i32: -; FIXME: We should be using S_LOAD_DWORD here. -; SI: BUFFER_LOAD_DWORD +; FIXME: We should be using s_load_dword here. +; SI: buffer_load_dword ; EG-DAG: MOV {{\** *}}T2.X ; EG-DAG: MOV {{\** *}}T3.X @@ -53,7 +53,7 @@ entry: @struct_foo_gv = internal unnamed_addr addrspace(2) constant [1 x %struct.foo] [ %struct.foo { float 16.0, [5 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4] } ] ; FUNC-LABEL: {{^}}struct_foo_gv_load: -; SI: S_LOAD_DWORD +; SI: s_load_dword define void @struct_foo_gv_load(i32 addrspace(1)* %out, i32 %index) { %gep = getelementptr inbounds [1 x %struct.foo] addrspace(2)* @struct_foo_gv, i32 0, i32 0, i32 1, i32 %index @@ -68,8 +68,8 @@ define void @struct_foo_gv_load(i32 addrspace(1)* %out, i32 %index) { <1 x i32> ] ; FUNC-LABEL: {{^}}array_v1_gv_load: -; FIXME: We should be using S_LOAD_DWORD here. -; SI: BUFFER_LOAD_DWORD +; FIXME: We should be using s_load_dword here. +; SI: buffer_load_dword define void @array_v1_gv_load(<1 x i32> addrspace(1)* %out, i32 %index) { %gep = getelementptr inbounds [4 x <1 x i32>] addrspace(2)* @array_v1_gv, i32 0, i32 %index %load = load <1 x i32> addrspace(2)* %gep, align 4 diff --git a/test/CodeGen/R600/half.ll b/test/CodeGen/R600/half.ll index ce3a1d0d71c..6ad9b2f4024 100644 --- a/test/CodeGen/R600/half.ll +++ b/test/CodeGen/R600/half.ll @@ -2,8 +2,8 @@ define void @test_load_store(half addrspace(1)* %in, half addrspace(1)* %out) { ; CHECK-LABEL: {{^}}test_load_store: -; CHECK: BUFFER_LOAD_USHORT [[TMP:v[0-9]+]] -; CHECK: BUFFER_STORE_SHORT [[TMP]] +; CHECK: buffer_load_ushort [[TMP:v[0-9]+]] +; CHECK: buffer_store_short [[TMP]] %val = load half addrspace(1)* %in store half %val, half addrspace(1) * %out ret void @@ -11,8 +11,8 @@ define void @test_load_store(half addrspace(1)* %in, half addrspace(1)* %out) { define void @test_bitcast_from_half(half addrspace(1)* %in, i16 addrspace(1)* %out) { ; CHECK-LABEL: {{^}}test_bitcast_from_half: -; CHECK: BUFFER_LOAD_USHORT [[TMP:v[0-9]+]] -; CHECK: BUFFER_STORE_SHORT [[TMP]] +; CHECK: buffer_load_ushort [[TMP:v[0-9]+]] +; CHECK: buffer_store_short [[TMP]] %val = load half addrspace(1) * %in %val_int = bitcast half %val to i16 store i16 %val_int, i16 addrspace(1)* %out @@ -21,8 +21,8 @@ define void @test_bitcast_from_half(half addrspace(1)* %in, i16 addrspace(1)* %o define void @test_bitcast_to_half(half addrspace(1)* %out, i16 addrspace(1)* %in) { ; CHECK-LABEL: {{^}}test_bitcast_to_half: -; CHECK: BUFFER_LOAD_USHORT [[TMP:v[0-9]+]] -; CHECK: BUFFER_STORE_SHORT [[TMP]] +; CHECK: buffer_load_ushort [[TMP:v[0-9]+]] +; CHECK: buffer_store_short [[TMP]] %val = load i16 addrspace(1)* %in %val_fp = bitcast i16 %val to half store half %val_fp, half addrspace(1)* %out @@ -31,7 +31,7 @@ define void @test_bitcast_to_half(half addrspace(1)* %out, i16 addrspace(1)* %in define void @test_extend32(half addrspace(1)* %in, float addrspace(1)* %out) { ; CHECK-LABEL: {{^}}test_extend32: -; CHECK: V_CVT_F32_F16_e32 +; CHECK: v_cvt_f32_f16_e32 %val16 = load half addrspace(1)* %in %val32 = fpext half %val16 to float @@ -41,8 +41,8 @@ define void @test_extend32(half addrspace(1)* %in, float addrspace(1)* %out) { define void @test_extend64(half addrspace(1)* %in, double addrspace(1)* %out) { ; CHECK-LABEL: {{^}}test_extend64: -; CHECK: V_CVT_F32_F16_e32 -; CHECK: V_CVT_F64_F32_e32 +; CHECK: v_cvt_f32_f16_e32 +; CHECK: v_cvt_f64_f32_e32 %val16 = load half addrspace(1)* %in %val64 = fpext half %val16 to double @@ -52,7 +52,7 @@ define void @test_extend64(half addrspace(1)* %in, double addrspace(1)* %out) { define void @test_trunc32(float addrspace(1)* %in, half addrspace(1)* %out) { ; CHECK-LABEL: {{^}}test_trunc32: -; CHECK: V_CVT_F16_F32_e32 +; CHECK: v_cvt_f16_f32_e32 %val32 = load float addrspace(1)* %in %val16 = fptrunc float %val32 to half diff --git a/test/CodeGen/R600/icmp64.ll b/test/CodeGen/R600/icmp64.ll index aec88ba2eea..870bf7fc72b 100644 --- a/test/CodeGen/R600/icmp64.ll +++ b/test/CodeGen/R600/icmp64.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; SI-LABEL: {{^}}test_i64_eq: -; SI: V_CMP_EQ_I64 +; SI: v_cmp_eq_i64 define void @test_i64_eq(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { %cmp = icmp eq i64 %a, %b %result = sext i1 %cmp to i32 @@ -10,7 +10,7 @@ define void @test_i64_eq(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { } ; SI-LABEL: {{^}}test_i64_ne: -; SI: V_CMP_NE_I64 +; SI: v_cmp_ne_i64 define void @test_i64_ne(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { %cmp = icmp ne i64 %a, %b %result = sext i1 %cmp to i32 @@ -19,7 +19,7 @@ define void @test_i64_ne(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { } ; SI-LABEL: {{^}}test_i64_slt: -; SI: V_CMP_LT_I64 +; SI: v_cmp_lt_i64 define void @test_i64_slt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { %cmp = icmp slt i64 %a, %b %result = sext i1 %cmp to i32 @@ -28,7 +28,7 @@ define void @test_i64_slt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { } ; SI-LABEL: {{^}}test_i64_ult: -; SI: V_CMP_LT_U64 +; SI: v_cmp_lt_u64 define void @test_i64_ult(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { %cmp = icmp ult i64 %a, %b %result = sext i1 %cmp to i32 @@ -37,7 +37,7 @@ define void @test_i64_ult(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { } ; SI-LABEL: {{^}}test_i64_sle: -; SI: V_CMP_LE_I64 +; SI: v_cmp_le_i64 define void @test_i64_sle(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { %cmp = icmp sle i64 %a, %b %result = sext i1 %cmp to i32 @@ -46,7 +46,7 @@ define void @test_i64_sle(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { } ; SI-LABEL: {{^}}test_i64_ule: -; SI: V_CMP_LE_U64 +; SI: v_cmp_le_u64 define void @test_i64_ule(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { %cmp = icmp ule i64 %a, %b %result = sext i1 %cmp to i32 @@ -55,7 +55,7 @@ define void @test_i64_ule(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { } ; SI-LABEL: {{^}}test_i64_sgt: -; SI: V_CMP_GT_I64 +; SI: v_cmp_gt_i64 define void @test_i64_sgt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { %cmp = icmp sgt i64 %a, %b %result = sext i1 %cmp to i32 @@ -64,7 +64,7 @@ define void @test_i64_sgt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { } ; SI-LABEL: {{^}}test_i64_ugt: -; SI: V_CMP_GT_U64 +; SI: v_cmp_gt_u64 define void @test_i64_ugt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { %cmp = icmp ugt i64 %a, %b %result = sext i1 %cmp to i32 @@ -73,7 +73,7 @@ define void @test_i64_ugt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { } ; SI-LABEL: {{^}}test_i64_sge: -; SI: V_CMP_GE_I64 +; SI: v_cmp_ge_i64 define void @test_i64_sge(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { %cmp = icmp sge i64 %a, %b %result = sext i1 %cmp to i32 @@ -82,7 +82,7 @@ define void @test_i64_sge(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { } ; SI-LABEL: {{^}}test_i64_uge: -; SI: V_CMP_GE_U64 +; SI: v_cmp_ge_u64 define void @test_i64_uge(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { %cmp = icmp uge i64 %a, %b %result = sext i1 %cmp to i32 diff --git a/test/CodeGen/R600/imm.ll b/test/CodeGen/R600/imm.ll index 44b5daca8d3..1fcaf292d7a 100644 --- a/test/CodeGen/R600/imm.ll +++ b/test/CodeGen/R600/imm.ll @@ -2,9 +2,9 @@ ; Use a 64-bit value with lo bits that can be represented as an inline constant ; CHECK-LABEL: {{^}}i64_imm_inline_lo: -; CHECK: S_MOV_B32 [[LO:s[0-9]+]], 5 -; CHECK: V_MOV_B32_e32 v[[LO_VGPR:[0-9]+]], [[LO]] -; CHECK: BUFFER_STORE_DWORDX2 v{{\[}}[[LO_VGPR]]: +; CHECK: s_mov_b32 [[LO:s[0-9]+]], 5 +; CHECK: v_mov_b32_e32 v[[LO_VGPR:[0-9]+]], [[LO]] +; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VGPR]]: define void @i64_imm_inline_lo(i64 addrspace(1) *%out) { entry: store i64 1311768464867721221, i64 addrspace(1) *%out ; 0x1234567800000005 @@ -13,9 +13,9 @@ entry: ; Use a 64-bit value with hi bits that can be represented as an inline constant ; CHECK-LABEL: {{^}}i64_imm_inline_hi: -; CHECK: S_MOV_B32 [[HI:s[0-9]+]], 5 -; CHECK: V_MOV_B32_e32 v[[HI_VGPR:[0-9]+]], [[HI]] -; CHECK: BUFFER_STORE_DWORDX2 v{{\[[0-9]+:}}[[HI_VGPR]] +; CHECK: s_mov_b32 [[HI:s[0-9]+]], 5 +; CHECK: v_mov_b32_e32 v[[HI_VGPR:[0-9]+]], [[HI]] +; CHECK: buffer_store_dwordx2 v{{\[[0-9]+:}}[[HI_VGPR]] define void @i64_imm_inline_hi(i64 addrspace(1) *%out) { entry: store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678 @@ -23,89 +23,89 @@ entry: } ; CHECK-LABEL: {{^}}store_inline_imm_0.0_f32 -; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) { store float 0.0, float addrspace(1)* %out ret void } ; CHECK-LABEL: {{^}}store_inline_imm_0.5_f32 -; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0.5{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @store_inline_imm_0.5_f32(float addrspace(1)* %out) { store float 0.5, float addrspace(1)* %out ret void } ; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f32 -; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -0.5{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -0.5{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @store_inline_imm_m_0.5_f32(float addrspace(1)* %out) { store float -0.5, float addrspace(1)* %out ret void } ; CHECK-LABEL: {{^}}store_inline_imm_1.0_f32 -; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 1.0{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @store_inline_imm_1.0_f32(float addrspace(1)* %out) { store float 1.0, float addrspace(1)* %out ret void } ; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f32 -; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -1.0{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -1.0{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @store_inline_imm_m_1.0_f32(float addrspace(1)* %out) { store float -1.0, float addrspace(1)* %out ret void } ; CHECK-LABEL: {{^}}store_inline_imm_2.0_f32 -; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 2.0{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @store_inline_imm_2.0_f32(float addrspace(1)* %out) { store float 2.0, float addrspace(1)* %out ret void } ; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f32 -; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -2.0{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -2.0{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @store_inline_imm_m_2.0_f32(float addrspace(1)* %out) { store float -2.0, float addrspace(1)* %out ret void } ; CHECK-LABEL: {{^}}store_inline_imm_4.0_f32 -; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 4.0{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 4.0{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @store_inline_imm_4.0_f32(float addrspace(1)* %out) { store float 4.0, float addrspace(1)* %out ret void } ; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f32 -; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -4.0{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -4.0{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) { store float -4.0, float addrspace(1)* %out ret void } ; CHECK-LABEL: {{^}}store_literal_imm_f32: -; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x45800000 -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x45800000 +; CHECK-NEXT: buffer_store_dword [[REG]] define void @store_literal_imm_f32(float addrspace(1)* %out) { store float 4096.0, float addrspace(1)* %out ret void } ; CHECK-LABEL: {{^}}add_inline_imm_0.0_f32 -; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]] -; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], 0.0, [[VAL]]{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: s_load_dword [[VAL:s[0-9]+]] +; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0.0, [[VAL]]{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) { %y = fadd float %x, 0.0 store float %y, float addrspace(1)* %out @@ -113,9 +113,9 @@ define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) { } ; CHECK-LABEL: {{^}}add_inline_imm_0.5_f32 -; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]] -; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], 0.5, [[VAL]]{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: s_load_dword [[VAL:s[0-9]+]] +; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0.5, [[VAL]]{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) { %y = fadd float %x, 0.5 store float %y, float addrspace(1)* %out @@ -123,9 +123,9 @@ define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) { } ; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f32 -; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]] -; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], -0.5, [[VAL]]{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: s_load_dword [[VAL:s[0-9]+]] +; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -0.5, [[VAL]]{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) { %y = fadd float %x, -0.5 store float %y, float addrspace(1)* %out @@ -133,9 +133,9 @@ define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) { } ; CHECK-LABEL: {{^}}add_inline_imm_1.0_f32 -; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]] -; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], 1.0, [[VAL]]{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: s_load_dword [[VAL:s[0-9]+]] +; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1.0, [[VAL]]{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) { %y = fadd float %x, 1.0 store float %y, float addrspace(1)* %out @@ -143,9 +143,9 @@ define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) { } ; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f32 -; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]] -; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], -1.0, [[VAL]]{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: s_load_dword [[VAL:s[0-9]+]] +; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1.0, [[VAL]]{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) { %y = fadd float %x, -1.0 store float %y, float addrspace(1)* %out @@ -153,9 +153,9 @@ define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) { } ; CHECK-LABEL: {{^}}add_inline_imm_2.0_f32 -; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]] -; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], 2.0, [[VAL]]{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: s_load_dword [[VAL:s[0-9]+]] +; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, [[VAL]]{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) { %y = fadd float %x, 2.0 store float %y, float addrspace(1)* %out @@ -163,9 +163,9 @@ define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) { } ; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f32 -; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]] -; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], -2.0, [[VAL]]{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: s_load_dword [[VAL:s[0-9]+]] +; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2.0, [[VAL]]{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) { %y = fadd float %x, -2.0 store float %y, float addrspace(1)* %out @@ -173,9 +173,9 @@ define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) { } ; CHECK-LABEL: {{^}}add_inline_imm_4.0_f32 -; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]] -; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], 4.0, [[VAL]]{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: s_load_dword [[VAL:s[0-9]+]] +; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 4.0, [[VAL]]{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) { %y = fadd float %x, 4.0 store float %y, float addrspace(1)* %out @@ -183,9 +183,9 @@ define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) { } ; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f32 -; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]] -; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], -4.0, [[VAL]]{{$}} -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: s_load_dword [[VAL:s[0-9]+]] +; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -4.0, [[VAL]]{{$}} +; CHECK-NEXT: buffer_store_dword [[REG]] define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) { %y = fadd float %x, -4.0 store float %y, float addrspace(1)* %out @@ -193,9 +193,9 @@ define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) { } ; CHECK-LABEL: @commute_add_inline_imm_0.5_f32 -; CHECK: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]] -; CHECK: V_ADD_F32_e32 [[REG:v[0-9]+]], 0.5, [[VAL]] -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: buffer_load_dword [[VAL:v[0-9]+]] +; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0.5, [[VAL]] +; CHECK-NEXT: buffer_store_dword [[REG]] define void @commute_add_inline_imm_0.5_f32(float addrspace(1)* %out, float addrspace(1)* %in) { %x = load float addrspace(1)* %in %y = fadd float %x, 0.5 @@ -204,9 +204,9 @@ define void @commute_add_inline_imm_0.5_f32(float addrspace(1)* %out, float addr } ; CHECK-LABEL: @commute_add_literal_f32 -; CHECK: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]] -; CHECK: V_ADD_F32_e32 [[REG:v[0-9]+]], 0x44800000, [[VAL]] -; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]] +; CHECK: buffer_load_dword [[VAL:v[0-9]+]] +; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0x44800000, [[VAL]] +; CHECK-NEXT: buffer_store_dword [[REG]] define void @commute_add_literal_f32(float addrspace(1)* %out, float addrspace(1)* %in) { %x = load float addrspace(1)* %in %y = fadd float %x, 1024.0 diff --git a/test/CodeGen/R600/indirect-addressing-si.ll b/test/CodeGen/R600/indirect-addressing-si.ll index 169d69b7c25..0ba16142794 100644 --- a/test/CodeGen/R600/indirect-addressing-si.ll +++ b/test/CodeGen/R600/indirect-addressing-si.ll @@ -4,8 +4,8 @@ ; indexing of vectors. ; CHECK: extract_w_offset -; CHECK: S_MOV_B32 m0 -; CHECK-NEXT: V_MOVRELS_B32_e32 +; CHECK: s_mov_b32 m0 +; CHECK-NEXT: v_movrels_b32_e32 define void @extract_w_offset(float addrspace(1)* %out, i32 %in) { entry: %0 = add i32 %in, 1 @@ -15,8 +15,8 @@ entry: } ; CHECK: extract_wo_offset -; CHECK: S_MOV_B32 m0 -; CHECK-NEXT: V_MOVRELS_B32_e32 +; CHECK: s_mov_b32 m0 +; CHECK-NEXT: v_movrels_b32_e32 define void @extract_wo_offset(float addrspace(1)* %out, i32 %in) { entry: %0 = extractelement <4 x float> , i32 %in @@ -25,8 +25,8 @@ entry: } ; CHECK: insert_w_offset -; CHECK: S_MOV_B32 m0 -; CHECK-NEXT: V_MOVRELD_B32_e32 +; CHECK: s_mov_b32 m0 +; CHECK-NEXT: v_movreld_b32_e32 define void @insert_w_offset(float addrspace(1)* %out, i32 %in) { entry: %0 = add i32 %in, 1 @@ -37,8 +37,8 @@ entry: } ; CHECK: insert_wo_offset -; CHECK: S_MOV_B32 m0 -; CHECK-NEXT: V_MOVRELD_B32_e32 +; CHECK: s_mov_b32 m0 +; CHECK-NEXT: v_movreld_b32_e32 define void @insert_wo_offset(float addrspace(1)* %out, i32 %in) { entry: %0 = insertelement <4 x float> , float 5.0, i32 %in diff --git a/test/CodeGen/R600/indirect-private-64.ll b/test/CodeGen/R600/indirect-private-64.ll index afae1e7cb58..e0a6ce1f7b7 100644 --- a/test/CodeGen/R600/indirect-private-64.ll +++ b/test/CodeGen/R600/indirect-private-64.ll @@ -6,11 +6,11 @@ declare void @llvm.AMDGPU.barrier.local() noduplicate nounwind ; SI-LABEL: {{^}}private_access_f64_alloca: -; SI-ALLOCA: BUFFER_STORE_DWORDX2 -; SI-ALLOCA: BUFFER_LOAD_DWORDX2 +; SI-ALLOCA: buffer_store_dwordx2 +; SI-ALLOCA: buffer_load_dwordx2 -; SI-PROMOTE: DS_WRITE_B64 -; SI-PROMOTE: DS_READ_B64 +; SI-PROMOTE: ds_write_b64 +; SI-PROMOTE: ds_read_b64 define void @private_access_f64_alloca(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in, i32 %b) nounwind { %val = load double addrspace(1)* %in, align 8 %array = alloca double, i32 16, align 8 @@ -24,17 +24,17 @@ define void @private_access_f64_alloca(double addrspace(1)* noalias %out, double ; SI-LABEL: {{^}}private_access_v2f64_alloca: -; SI-ALLOCA: BUFFER_STORE_DWORDX4 -; SI-ALLOCA: BUFFER_LOAD_DWORDX4 +; SI-ALLOCA: buffer_store_dwordx4 +; SI-ALLOCA: buffer_load_dwordx4 -; SI-PROMOTE: DS_WRITE_B32 -; SI-PROMOTE: DS_WRITE_B32 -; SI-PROMOTE: DS_WRITE_B32 -; SI-PROMOTE: DS_WRITE_B32 -; SI-PROMOTE: DS_READ_B32 -; SI-PROMOTE: DS_READ_B32 -; SI-PROMOTE: DS_READ_B32 -; SI-PROMOTE: DS_READ_B32 +; SI-PROMOTE: ds_write_b32 +; SI-PROMOTE: ds_write_b32 +; SI-PROMOTE: ds_write_b32 +; SI-PROMOTE: ds_write_b32 +; SI-PROMOTE: ds_read_b32 +; SI-PROMOTE: ds_read_b32 +; SI-PROMOTE: ds_read_b32 +; SI-PROMOTE: ds_read_b32 define void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out, <2 x double> addrspace(1)* noalias %in, i32 %b) nounwind { %val = load <2 x double> addrspace(1)* %in, align 16 %array = alloca <2 x double>, i32 16, align 16 @@ -48,11 +48,11 @@ define void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out ; SI-LABEL: {{^}}private_access_i64_alloca: -; SI-ALLOCA: BUFFER_STORE_DWORDX2 -; SI-ALLOCA: BUFFER_LOAD_DWORDX2 +; SI-ALLOCA: buffer_store_dwordx2 +; SI-ALLOCA: buffer_load_dwordx2 -; SI-PROMOTE: DS_WRITE_B64 -; SI-PROMOTE: DS_READ_B64 +; SI-PROMOTE: ds_write_b64 +; SI-PROMOTE: ds_read_b64 define void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i32 %b) nounwind { %val = load i64 addrspace(1)* %in, align 8 %array = alloca i64, i32 16, align 8 @@ -66,17 +66,17 @@ define void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrs ; SI-LABEL: {{^}}private_access_v2i64_alloca: -; SI-ALLOCA: BUFFER_STORE_DWORDX4 -; SI-ALLOCA: BUFFER_LOAD_DWORDX4 +; SI-ALLOCA: buffer_store_dwordx4 +; SI-ALLOCA: buffer_load_dwordx4 -; SI-PROMOTE: DS_WRITE_B32 -; SI-PROMOTE: DS_WRITE_B32 -; SI-PROMOTE: DS_WRITE_B32 -; SI-PROMOTE: DS_WRITE_B32 -; SI-PROMOTE: DS_READ_B32 -; SI-PROMOTE: DS_READ_B32 -; SI-PROMOTE: DS_READ_B32 -; SI-PROMOTE: DS_READ_B32 +; SI-PROMOTE: ds_write_b32 +; SI-PROMOTE: ds_write_b32 +; SI-PROMOTE: ds_write_b32 +; SI-PROMOTE: ds_write_b32 +; SI-PROMOTE: ds_read_b32 +; SI-PROMOTE: ds_read_b32 +; SI-PROMOTE: ds_read_b32 +; SI-PROMOTE: ds_read_b32 define void @private_access_v2i64_alloca(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in, i32 %b) nounwind { %val = load <2 x i64> addrspace(1)* %in, align 16 %array = alloca <2 x i64>, i32 16, align 16 diff --git a/test/CodeGen/R600/infinite-loop.ll b/test/CodeGen/R600/infinite-loop.ll index 7bce2f32c24..48edab00b94 100644 --- a/test/CodeGen/R600/infinite-loop.ll +++ b/test/CodeGen/R600/infinite-loop.ll @@ -1,11 +1,11 @@ ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; SI-LABEL: {{^}}infinite_loop: -; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x3e7 +; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e7 ; SI: BB0_1: -; SI: BUFFER_STORE_DWORD [[REG]] -; SI: S_WAITCNT vmcnt(0) expcnt(0) -; SI: S_BRANCH BB0_1 +; SI: buffer_store_dword [[REG]] +; SI: s_waitcnt vmcnt(0) expcnt(0) +; SI: s_branch BB0_1 define void @infinite_loop(i32 addrspace(1)* %out) { entry: br label %for.body diff --git a/test/CodeGen/R600/insert_vector_elt.ll b/test/CodeGen/R600/insert_vector_elt.ll index 2f9730bdcc6..857c414c818 100644 --- a/test/CodeGen/R600/insert_vector_elt.ll +++ b/test/CodeGen/R600/insert_vector_elt.ll @@ -9,11 +9,11 @@ ; not just directly into the vector component? ; SI-LABEL: {{^}}insertelement_v4f32_0: -; S_LOAD_DWORDX4 s{{[}}[[LOW_REG:[0-9]+]]: -; V_MOV_B32_e32 -; V_MOV_B32_e32 [[CONSTREG:v[0-9]+]], 5.000000e+00 -; V_MOV_B32_e32 v[[LOW_REG]], [[CONSTREG]] -; BUFFER_STORE_DWORDX4 v{{[}}[[LOW_REG]]: +; s_load_dwordx4 s{{[}}[[LOW_REG:[0-9]+]]: +; v_mov_b32_e32 +; v_mov_b32_e32 [[CONSTREG:v[0-9]+]], 5.000000e+00 +; v_mov_b32_e32 v[[LOW_REG]], [[CONSTREG]] +; buffer_store_dwordx4 v{{[}}[[LOW_REG]]: define void @insertelement_v4f32_0(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 0 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 @@ -49,9 +49,9 @@ define void @insertelement_v4i32_0(<4 x i32> addrspace(1)* %out, <4 x i32> %a) n } ; SI-LABEL: {{^}}dynamic_insertelement_v2f32: -; SI: V_MOV_B32_e32 [[CONST:v[0-9]+]], 0x40a00000 -; SI: V_MOVRELD_B32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] -; SI: BUFFER_STORE_DWORDX2 {{v\[}}[[LOW_RESULT_REG]]: +; SI: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 +; SI: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] +; SI: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: define void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, i32 %b) nounwind { %vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 %b store <2 x float> %vecins, <2 x float> addrspace(1)* %out, align 8 @@ -59,9 +59,9 @@ define void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x fl } ; SI-LABEL: {{^}}dynamic_insertelement_v4f32: -; SI: V_MOV_B32_e32 [[CONST:v[0-9]+]], 0x40a00000 -; SI: V_MOVRELD_B32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] -; SI: BUFFER_STORE_DWORDX4 {{v\[}}[[LOW_RESULT_REG]]: +; SI: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 +; SI: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] +; SI: buffer_store_dwordx4 {{v\[}}[[LOW_RESULT_REG]]: define void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %b) nounwind { %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 %b store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 @@ -69,8 +69,8 @@ define void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x fl } ; SI-LABEL: {{^}}dynamic_insertelement_v8f32: -; FIXMESI: BUFFER_STORE_DWORDX4 -; FIXMESI: BUFFER_STORE_DWORDX4 +; FIXMESI: buffer_store_dwordx4 +; FIXMESI: buffer_store_dwordx4 define void @dynamic_insertelement_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, i32 %b) nounwind { %vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b store <8 x float> %vecins, <8 x float> addrspace(1)* %out, align 32 @@ -78,10 +78,10 @@ define void @dynamic_insertelement_v8f32(<8 x float> addrspace(1)* %out, <8 x fl } ; SI-LABEL: {{^}}dynamic_insertelement_v16f32: -; FIXMESI: BUFFER_STORE_DWORDX4 -; FIXMESI: BUFFER_STORE_DWORDX4 -; FIXMESI: BUFFER_STORE_DWORDX4 -; FIXMESI: BUFFER_STORE_DWORDX4 +; FIXMESI: buffer_store_dwordx4 +; FIXMESI: buffer_store_dwordx4 +; FIXMESI: buffer_store_dwordx4 +; FIXMESI: buffer_store_dwordx4 define void @dynamic_insertelement_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, i32 %b) nounwind { %vecins = insertelement <16 x float> %a, float 5.000000e+00, i32 %b store <16 x float> %vecins, <16 x float> addrspace(1)* %out, align 64 @@ -89,7 +89,7 @@ define void @dynamic_insertelement_v16f32(<16 x float> addrspace(1)* %out, <16 x } ; SI-LABEL: {{^}}dynamic_insertelement_v2i32: -; SI: BUFFER_STORE_DWORDX2 +; SI: buffer_store_dwordx2 define void @dynamic_insertelement_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, i32 %b) nounwind { %vecins = insertelement <2 x i32> %a, i32 5, i32 %b store <2 x i32> %vecins, <2 x i32> addrspace(1)* %out, align 8 @@ -97,7 +97,7 @@ define void @dynamic_insertelement_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> } ; SI-LABEL: {{^}}dynamic_insertelement_v4i32: -; SI: BUFFER_STORE_DWORDX4 +; SI: buffer_store_dwordx4 define void @dynamic_insertelement_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, i32 %b) nounwind { %vecins = insertelement <4 x i32> %a, i32 5, i32 %b store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16 @@ -105,8 +105,8 @@ define void @dynamic_insertelement_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> } ; SI-LABEL: {{^}}dynamic_insertelement_v8i32: -; FIXMESI: BUFFER_STORE_DWORDX4 -; FIXMESI: BUFFER_STORE_DWORDX4 +; FIXMESI: buffer_store_dwordx4 +; FIXMESI: buffer_store_dwordx4 define void @dynamic_insertelement_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, i32 %b) nounwind { %vecins = insertelement <8 x i32> %a, i32 5, i32 %b store <8 x i32> %vecins, <8 x i32> addrspace(1)* %out, align 32 @@ -114,10 +114,10 @@ define void @dynamic_insertelement_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> } ; SI-LABEL: {{^}}dynamic_insertelement_v16i32: -; FIXMESI: BUFFER_STORE_DWORDX4 -; FIXMESI: BUFFER_STORE_DWORDX4 -; FIXMESI: BUFFER_STORE_DWORDX4 -; FIXMESI: BUFFER_STORE_DWORDX4 +; FIXMESI: buffer_store_dwordx4 +; FIXMESI: buffer_store_dwordx4 +; FIXMESI: buffer_store_dwordx4 +; FIXMESI: buffer_store_dwordx4 define void @dynamic_insertelement_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> %a, i32 %b) nounwind { %vecins = insertelement <16 x i32> %a, i32 5, i32 %b store <16 x i32> %vecins, <16 x i32> addrspace(1)* %out, align 64 @@ -126,7 +126,7 @@ define void @dynamic_insertelement_v16i32(<16 x i32> addrspace(1)* %out, <16 x i ; SI-LABEL: {{^}}dynamic_insertelement_v2i16: -; FIXMESI: BUFFER_STORE_DWORDX2 +; FIXMESI: buffer_store_dwordx2 define void @dynamic_insertelement_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %a, i32 %b) nounwind { %vecins = insertelement <2 x i16> %a, i16 5, i32 %b store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out, align 8 @@ -134,7 +134,7 @@ define void @dynamic_insertelement_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> } ; SI-LABEL: {{^}}dynamic_insertelement_v4i16: -; FIXMESI: BUFFER_STORE_DWORDX4 +; FIXMESI: buffer_store_dwordx4 define void @dynamic_insertelement_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %a, i32 %b) nounwind { %vecins = insertelement <4 x i16> %a, i16 5, i32 %b store <4 x i16> %vecins, <4 x i16> addrspace(1)* %out, align 16 @@ -151,7 +151,7 @@ define void @dynamic_insertelement_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> %a } ; SI-LABEL: {{^}}dynamic_insertelement_v4i8: -; FIXMESI: BUFFER_STORE_DWORD +; FIXMESI: buffer_store_dword define void @dynamic_insertelement_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, i32 %b) nounwind { %vecins = insertelement <4 x i8> %a, i8 5, i32 %b store <4 x i8> %vecins, <4 x i8> addrspace(1)* %out, align 16 @@ -159,7 +159,7 @@ define void @dynamic_insertelement_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a } ; SI-LABEL: {{^}}dynamic_insertelement_v8i8: -; FIXMESI: BUFFER_STORE_DWORDX2 +; FIXMESI: buffer_store_dwordx2 define void @dynamic_insertelement_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> %a, i32 %b) nounwind { %vecins = insertelement <8 x i8> %a, i8 5, i32 %b store <8 x i8> %vecins, <8 x i8> addrspace(1)* %out, align 16 @@ -167,7 +167,7 @@ define void @dynamic_insertelement_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> %a } ; SI-LABEL: {{^}}dynamic_insertelement_v16i8: -; FIXMESI: BUFFER_STORE_DWORDX4 +; FIXMESI: buffer_store_dwordx4 define void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> %a, i32 %b) nounwind { %vecins = insertelement <16 x i8> %a, i8 5, i32 %b store <16 x i8> %vecins, <16 x i8> addrspace(1)* %out, align 16 @@ -201,11 +201,11 @@ endif: } ; SI-LABEL: {{^}}dynamic_insertelement_v2f64: -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: S_ENDPGM +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: s_endpgm define void @dynamic_insertelement_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, i32 %b) nounwind { %vecins = insertelement <2 x double> %a, double 8.0, i32 %b store <2 x double> %vecins, <2 x double> addrspace(1)* %out, align 16 @@ -213,9 +213,9 @@ define void @dynamic_insertelement_v2f64(<2 x double> addrspace(1)* %out, <2 x d } ; SI-LABEL: {{^}}dynamic_insertelement_v2i64: -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: S_ENDPGM +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: s_endpgm define void @dynamic_insertelement_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %a, i32 %b) nounwind { %vecins = insertelement <2 x i64> %a, i64 5, i32 %b store <2 x i64> %vecins, <2 x i64> addrspace(1)* %out, align 8 @@ -223,11 +223,11 @@ define void @dynamic_insertelement_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> } ; SI-LABEL: {{^}}dynamic_insertelement_v4f64: -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: S_ENDPGM +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: s_endpgm define void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, i32 %b) nounwind { %vecins = insertelement <4 x double> %a, double 8.0, i32 %b store <4 x double> %vecins, <4 x double> addrspace(1)* %out, align 16 @@ -235,15 +235,15 @@ define void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)* %out, <4 x d } ; SI-LABEL: {{^}}dynamic_insertelement_v8f64: -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: S_ENDPGM +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: s_endpgm define void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, i32 %b) nounwind { %vecins = insertelement <8 x double> %a, double 8.0, i32 %b store <8 x double> %vecins, <8 x double> addrspace(1)* %out, align 16 diff --git a/test/CodeGen/R600/kernel-args.ll b/test/CodeGen/R600/kernel-args.ll index a229534134a..9a7da907c7b 100644 --- a/test/CodeGen/R600/kernel-args.ll +++ b/test/CodeGen/R600/kernel-args.ll @@ -5,7 +5,7 @@ ; EG-CHECK-LABEL: {{^}}i8_arg: ; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI-CHECK-LABEL: {{^}}i8_arg: -; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: buffer_load_ubyte define void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind { entry: @@ -17,7 +17,7 @@ entry: ; EG-CHECK-LABEL: {{^}}i8_zext_arg: ; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI-CHECK-LABEL: {{^}}i8_zext_arg: -; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb +; SI-CHECK: s_load_dword s{{[0-9]}}, s[0:1], 0xb define void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind { entry: @@ -29,7 +29,7 @@ entry: ; EG-CHECK-LABEL: {{^}}i8_sext_arg: ; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI-CHECK-LABEL: {{^}}i8_sext_arg: -; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb +; SI-CHECK: s_load_dword s{{[0-9]}}, s[0:1], 0xb define void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind { entry: @@ -41,7 +41,7 @@ entry: ; EG-CHECK-LABEL: {{^}}i16_arg: ; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI-CHECK-LABEL: {{^}}i16_arg: -; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: buffer_load_ushort define void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind { entry: @@ -53,7 +53,7 @@ entry: ; EG-CHECK-LABEL: {{^}}i16_zext_arg: ; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI-CHECK-LABEL: {{^}}i16_zext_arg: -; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb +; SI-CHECK: s_load_dword s{{[0-9]}}, s[0:1], 0xb define void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind { entry: @@ -65,7 +65,7 @@ entry: ; EG-CHECK-LABEL: {{^}}i16_sext_arg: ; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI-CHECK-LABEL: {{^}}i16_sext_arg: -; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb +; SI-CHECK: s_load_dword s{{[0-9]}}, s[0:1], 0xb define void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind { entry: @@ -77,7 +77,7 @@ entry: ; EG-CHECK-LABEL: {{^}}i32_arg: ; EG-CHECK: T{{[0-9]\.[XYZW]}}, KC0[2].Z ; SI-CHECK-LABEL: {{^}}i32_arg: -; S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb +; s_load_dword s{{[0-9]}}, s[0:1], 0xb define void @i32_arg(i32 addrspace(1)* nocapture %out, i32 %in) nounwind { entry: store i32 %in, i32 addrspace(1)* %out, align 4 @@ -87,7 +87,7 @@ entry: ; EG-CHECK-LABEL: {{^}}f32_arg: ; EG-CHECK: T{{[0-9]\.[XYZW]}}, KC0[2].Z ; SI-CHECK-LABEL: {{^}}f32_arg: -; S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb +; s_load_dword s{{[0-9]}}, s[0:1], 0xb define void @f32_arg(float addrspace(1)* nocapture %out, float %in) nounwind { entry: store float %in, float addrspace(1)* %out, align 4 @@ -98,8 +98,8 @@ entry: ; EG-CHECK: VTX_READ_8 ; EG-CHECK: VTX_READ_8 ; SI-CHECK-LABEL: {{^}}v2i8_arg: -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte define void @v2i8_arg(<2 x i8> addrspace(1)* %out, <2 x i8> %in) { entry: store <2 x i8> %in, <2 x i8> addrspace(1)* %out @@ -110,8 +110,8 @@ entry: ; EG-CHECK: VTX_READ_16 ; EG-CHECK: VTX_READ_16 ; SI-CHECK-LABEL: {{^}}v2i16_arg: -; SI-CHECK-DAG: BUFFER_LOAD_USHORT -; SI-CHECK-DAG: BUFFER_LOAD_USHORT +; SI-CHECK-DAG: buffer_load_ushort +; SI-CHECK-DAG: buffer_load_ushort define void @v2i16_arg(<2 x i16> addrspace(1)* %out, <2 x i16> %in) { entry: store <2 x i16> %in, <2 x i16> addrspace(1)* %out @@ -122,7 +122,7 @@ entry: ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W ; SI-CHECK-LABEL: {{^}}v2i32_arg: -; SI-CHECK: S_LOAD_DWORDX2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb +; SI-CHECK: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb define void @v2i32_arg(<2 x i32> addrspace(1)* nocapture %out, <2 x i32> %in) nounwind { entry: store <2 x i32> %in, <2 x i32> addrspace(1)* %out, align 4 @@ -133,7 +133,7 @@ entry: ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W ; SI-CHECK-LABEL: {{^}}v2f32_arg: -; SI-CHECK: S_LOAD_DWORDX2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb +; SI-CHECK: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb define void @v2f32_arg(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) nounwind { entry: store <2 x float> %in, <2 x float> addrspace(1)* %out, align 4 @@ -166,7 +166,7 @@ entry: ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W ; SI-CHECK-LABEL: {{^}}v3i32_arg: -; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd +; SI-CHECK: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd define void @v3i32_arg(<3 x i32> addrspace(1)* nocapture %out, <3 x i32> %in) nounwind { entry: store <3 x i32> %in, <3 x i32> addrspace(1)* %out, align 4 @@ -178,7 +178,7 @@ entry: ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W ; SI-CHECK-LABEL: {{^}}v3f32_arg: -; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd +; SI-CHECK: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd define void @v3f32_arg(<3 x float> addrspace(1)* nocapture %out, <3 x float> %in) nounwind { entry: store <3 x float> %in, <3 x float> addrspace(1)* %out, align 4 @@ -191,10 +191,10 @@ entry: ; EG-CHECK: VTX_READ_8 ; EG-CHECK: VTX_READ_8 ; SI-CHECK-LABEL: {{^}}v4i8_arg: -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte define void @v4i8_arg(<4 x i8> addrspace(1)* %out, <4 x i8> %in) { entry: store <4 x i8> %in, <4 x i8> addrspace(1)* %out @@ -207,10 +207,10 @@ entry: ; EG-CHECK: VTX_READ_16 ; EG-CHECK: VTX_READ_16 ; SI-CHECK-LABEL: {{^}}v4i16_arg: -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort define void @v4i16_arg(<4 x i16> addrspace(1)* %out, <4 x i16> %in) { entry: store <4 x i16> %in, <4 x i16> addrspace(1)* %out @@ -223,7 +223,7 @@ entry: ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X ; SI-CHECK-LABEL: {{^}}v4i32_arg: -; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd +; SI-CHECK: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd define void @v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> %in) nounwind { entry: store <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4 @@ -236,7 +236,7 @@ entry: ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X ; SI-CHECK-LABEL: {{^}}v4f32_arg: -; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd +; SI-CHECK: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd define void @v4f32_arg(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) nounwind { entry: store <4 x float> %in, <4 x float> addrspace(1)* %out, align 4 @@ -253,13 +253,13 @@ entry: ; EG-CHECK: VTX_READ_8 ; EG-CHECK: VTX_READ_8 ; SI-CHECK-LABEL: {{^}}v8i8_arg: -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte define void @v8i8_arg(<8 x i8> addrspace(1)* %out, <8 x i8> %in) { entry: store <8 x i8> %in, <8 x i8> addrspace(1)* %out @@ -276,14 +276,14 @@ entry: ; EG-CHECK: VTX_READ_16 ; EG-CHECK: VTX_READ_16 ; SI-CHECK-LABEL: {{^}}v8i16_arg: -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort define void @v8i16_arg(<8 x i16> addrspace(1)* %out, <8 x i16> %in) { entry: store <8 x i16> %in, <8 x i16> addrspace(1)* %out @@ -300,7 +300,7 @@ entry: ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X ; SI-CHECK-LABEL: {{^}}v8i32_arg: -; SI-CHECK: S_LOAD_DWORDX8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11 +; SI-CHECK: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11 define void @v8i32_arg(<8 x i32> addrspace(1)* nocapture %out, <8 x i32> %in) nounwind { entry: store <8 x i32> %in, <8 x i32> addrspace(1)* %out, align 4 @@ -317,7 +317,7 @@ entry: ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X ; SI-CHECK-LABEL: {{^}}v8f32_arg: -; SI-CHECK: S_LOAD_DWORDX8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11 +; SI-CHECK: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11 define void @v8f32_arg(<8 x float> addrspace(1)* nocapture %out, <8 x float> %in) nounwind { entry: store <8 x float> %in, <8 x float> addrspace(1)* %out, align 4 @@ -342,22 +342,22 @@ entry: ; EG-CHECK: VTX_READ_8 ; EG-CHECK: VTX_READ_8 ; SI-CHECK-LABEL: {{^}}v16i8_arg: -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte define void @v16i8_arg(<16 x i8> addrspace(1)* %out, <16 x i8> %in) { entry: store <16 x i8> %in, <16 x i8> addrspace(1)* %out @@ -382,22 +382,22 @@ entry: ; EG-CHECK: VTX_READ_16 ; EG-CHECK: VTX_READ_16 ; SI-CHECK-LABEL: {{^}}v16i16_arg: -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort define void @v16i16_arg(<16 x i16> addrspace(1)* %out, <16 x i16> %in) { entry: store <16 x i16> %in, <16 x i16> addrspace(1)* %out @@ -422,7 +422,7 @@ entry: ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X ; SI-CHECK-LABEL: {{^}}v16i32_arg: -; SI-CHECK: S_LOAD_DWORDX16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19 +; SI-CHECK: s_load_dwordx16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19 define void @v16i32_arg(<16 x i32> addrspace(1)* nocapture %out, <16 x i32> %in) nounwind { entry: store <16 x i32> %in, <16 x i32> addrspace(1)* %out, align 4 @@ -447,7 +447,7 @@ entry: ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W ; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X ; SI-CHECK-LABEL: {{^}}v16f32_arg: -; SI-CHECK: S_LOAD_DWORDX16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19 +; SI-CHECK: s_load_dwordx16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19 define void @v16f32_arg(<16 x float> addrspace(1)* nocapture %out, <16 x float> %in) nounwind { entry: store <16 x float> %in, <16 x float> addrspace(1)* %out, align 4 @@ -455,18 +455,18 @@ entry: } ; FUNC-LABEL: {{^}}kernel_arg_i64: -; SI: S_LOAD_DWORDX2 -; SI: S_LOAD_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 +; SI: s_load_dwordx2 +; SI: s_load_dwordx2 +; SI: buffer_store_dwordx2 define void @kernel_arg_i64(i64 addrspace(1)* %out, i64 %a) nounwind { store i64 %a, i64 addrspace(1)* %out, align 8 ret void } ; XFUNC-LABEL: {{^}}kernel_arg_v1i64: -; XSI: S_LOAD_DWORDX2 -; XSI: S_LOAD_DWORDX2 -; XSI: BUFFER_STORE_DWORDX2 +; XSI: s_load_dwordx2 +; XSI: s_load_dwordx2 +; XSI: buffer_store_dwordx2 ; define void @kernel_arg_v1i64(<1 x i64> addrspace(1)* %out, <1 x i64> %a) nounwind { ; store <1 x i64> %a, <1 x i64> addrspace(1)* %out, align 8 ; ret void diff --git a/test/CodeGen/R600/large-constant-initializer.ll b/test/CodeGen/R600/large-constant-initializer.ll index 191b5c3de91..5612dd343fd 100644 --- a/test/CodeGen/R600/large-constant-initializer.ll +++ b/test/CodeGen/R600/large-constant-initializer.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=r600 -mcpu=SI < %s -; CHECK: S_ENDPGM +; CHECK: s_endpgm @gv = external unnamed_addr addrspace(2) constant [239 x i32], align 4 diff --git a/test/CodeGen/R600/llvm.AMDGPU.abs.ll b/test/CodeGen/R600/llvm.AMDGPU.abs.ll index 2a0d8f9ec28..b4aede8e751 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.abs.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.abs.ll @@ -7,9 +7,9 @@ declare i32 @llvm.AMDGPU.abs(i32) nounwind readnone declare i32 @llvm.AMDIL.abs.i32(i32) nounwind readnone ; FUNC-LABEL: {{^}}s_abs_i32: -; SI: S_SUB_I32 -; SI: S_MAX_I32 -; SI: S_ENDPGM +; SI: s_sub_i32 +; SI: s_max_i32 +; SI: s_endpgm ; EG: SUB_INT ; EG: MAX_INT @@ -20,9 +20,9 @@ define void @s_abs_i32(i32 addrspace(1)* %out, i32 %src) nounwind { } ; FUNC-LABEL: {{^}}v_abs_i32: -; SI: V_SUB_I32_e32 -; SI: V_MAX_I32_e32 -; SI: S_ENDPGM +; SI: v_sub_i32_e32 +; SI: v_max_i32_e32 +; SI: s_endpgm ; EG: SUB_INT ; EG: MAX_INT @@ -34,9 +34,9 @@ define void @v_abs_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind } ; FUNC-LABEL: {{^}}abs_i32_legacy_amdil: -; SI: V_SUB_I32_e32 -; SI: V_MAX_I32_e32 -; SI: S_ENDPGM +; SI: v_sub_i32_e32 +; SI: v_max_i32_e32 +; SI: s_endpgm ; EG: SUB_INT ; EG: MAX_INT diff --git a/test/CodeGen/R600/llvm.AMDGPU.barrier.global.ll b/test/CodeGen/R600/llvm.AMDGPU.barrier.global.ll index dd5b8fdd895..98f6695f731 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.barrier.global.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.barrier.global.ll @@ -3,7 +3,7 @@ ; FUNC-LABEL: {{^}}test_barrier_global: ; EG: GROUP_BARRIER -; SI: S_BARRIER +; SI: s_barrier define void @test_barrier_global(i32 addrspace(1)* %out) { entry: diff --git a/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll b/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll index c5cd3b7b239..92fe9f263e9 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll @@ -3,7 +3,7 @@ ; FUNC-LABEL: {{^}}test_barrier_local: ; EG: GROUP_BARRIER -; SI: S_BARRIER +; SI: s_barrier define void @test_barrier_local(i32 addrspace(1)* %out) { entry: diff --git a/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll b/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll index c230a2e2afb..0b60d0d03ee 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll @@ -4,7 +4,7 @@ declare i32 @llvm.AMDGPU.bfe.i32(i32, i32, i32) nounwind readnone ; FUNC-LABEL: {{^}}bfe_i32_arg_arg_arg: -; SI: V_BFE_I32 +; SI: v_bfe_i32 ; EG: BFE_INT ; EG: encoding: [{{[x0-9a-f]+,[x0-9a-f]+,[x0-9a-f]+,[x0-9a-f]+,[x0-9a-f]+}},0xac define void @bfe_i32_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind { @@ -14,7 +14,7 @@ define void @bfe_i32_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i } ; FUNC-LABEL: {{^}}bfe_i32_arg_arg_imm: -; SI: V_BFE_I32 +; SI: v_bfe_i32 ; EG: BFE_INT define void @bfe_i32_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 %src1, i32 123) nounwind readnone @@ -23,7 +23,7 @@ define void @bfe_i32_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) n } ; FUNC-LABEL: {{^}}bfe_i32_arg_imm_arg: -; SI: V_BFE_I32 +; SI: v_bfe_i32 ; EG: BFE_INT define void @bfe_i32_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 123, i32 %src2) nounwind readnone @@ -32,7 +32,7 @@ define void @bfe_i32_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) n } ; FUNC-LABEL: {{^}}bfe_i32_imm_arg_arg: -; SI: V_BFE_I32 +; SI: v_bfe_i32 ; EG: BFE_INT define void @bfe_i32_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 123, i32 %src1, i32 %src2) nounwind readnone @@ -41,7 +41,7 @@ define void @bfe_i32_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) n } ; FUNC-LABEL: {{^}}v_bfe_print_arg: -; SI: V_BFE_I32 v{{[0-9]+}}, v{{[0-9]+}}, 2, 8 +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 2, 8 define void @v_bfe_print_arg(i32 addrspace(1)* %out, i32 addrspace(1)* %src0) nounwind { %load = load i32 addrspace(1)* %src0, align 4 %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 2, i32 8) nounwind readnone @@ -50,8 +50,8 @@ define void @v_bfe_print_arg(i32 addrspace(1)* %out, i32 addrspace(1)* %src0) no } ; FUNC-LABEL: {{^}}bfe_i32_arg_0_width_reg_offset: -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_arg_0_width_reg_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 %src1, i32 0) nounwind readnone @@ -60,8 +60,8 @@ define void @bfe_i32_arg_0_width_reg_offset(i32 addrspace(1)* %out, i32 %src0, i } ; FUNC-LABEL: {{^}}bfe_i32_arg_0_width_imm_offset: -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 8, i32 0) nounwind readnone @@ -70,9 +70,9 @@ define void @bfe_i32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i } ; FUNC-LABEL: {{^}}bfe_i32_test_6: -; SI: V_LSHLREV_B32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} -; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} +; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} +; SI: s_endpgm define void @bfe_i32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -82,11 +82,11 @@ define void @bfe_i32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_i32_test_7: -; SI-NOT: SHL -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: shl +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm define void @bfe_i32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -97,9 +97,9 @@ define void @bfe_i32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw ; FIXME: The shifts should be 1 BFE ; FUNC-LABEL: {{^}}bfe_i32_test_8: -; SI: BUFFER_LOAD_DWORD -; SI: V_BFE_I32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1 -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1 +; SI: s_endpgm define void @bfe_i32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -109,10 +109,10 @@ define void @bfe_i32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_i32_test_9: -; SI-NOT: BFE -; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_i32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 31, i32 1) @@ -121,10 +121,10 @@ define void @bfe_i32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_i32_test_10: -; SI-NOT: BFE -; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_i32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 1, i32 31) @@ -133,10 +133,10 @@ define void @bfe_i32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun } ; FUNC-LABEL: {{^}}bfe_i32_test_11: -; SI-NOT: BFE -; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 8, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 8, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_i32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 8, i32 24) @@ -145,10 +145,10 @@ define void @bfe_i32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun } ; FUNC-LABEL: {{^}}bfe_i32_test_12: -; SI-NOT: BFE -; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 24, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 24, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_i32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 24, i32 8) @@ -157,9 +157,9 @@ define void @bfe_i32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun } ; FUNC-LABEL: {{^}}bfe_i32_test_13: -; SI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 31, {{v[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI: v_ashrrev_i32_e32 {{v[0-9]+}}, 31, {{v[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_i32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = ashr i32 %x, 31 @@ -168,9 +168,9 @@ define void @bfe_i32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun } ; FUNC-LABEL: {{^}}bfe_i32_test_14: -; SI-NOT: LSHR -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: lshr +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_i32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = lshr i32 %x, 31 @@ -179,10 +179,10 @@ define void @bfe_i32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_0: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_0(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 0, i32 0, i32 0) nounwind readnone @@ -191,10 +191,10 @@ define void @bfe_i32_constant_fold_test_0(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_1: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_1(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 12334, i32 0, i32 0) nounwind readnone @@ -203,10 +203,10 @@ define void @bfe_i32_constant_fold_test_1(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_2: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_2(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 0, i32 0, i32 1) nounwind readnone @@ -215,10 +215,10 @@ define void @bfe_i32_constant_fold_test_2(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_3: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_3(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 1, i32 0, i32 1) nounwind readnone @@ -227,10 +227,10 @@ define void @bfe_i32_constant_fold_test_3(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_4: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_4(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 4294967295, i32 0, i32 1) nounwind readnone @@ -239,10 +239,10 @@ define void @bfe_i32_constant_fold_test_4(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_5: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_5(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 128, i32 7, i32 1) nounwind readnone @@ -251,10 +251,10 @@ define void @bfe_i32_constant_fold_test_5(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_6: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0xffffff80 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0xffffff80 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_6(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 128, i32 0, i32 8) nounwind readnone @@ -263,10 +263,10 @@ define void @bfe_i32_constant_fold_test_6(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_7: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x7f -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_7(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 127, i32 0, i32 8) nounwind readnone @@ -275,10 +275,10 @@ define void @bfe_i32_constant_fold_test_7(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_8: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_8(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 127, i32 6, i32 8) nounwind readnone @@ -287,10 +287,10 @@ define void @bfe_i32_constant_fold_test_8(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_9: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_9(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 65536, i32 16, i32 8) nounwind readnone @@ -299,10 +299,10 @@ define void @bfe_i32_constant_fold_test_9(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_10: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_10(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 65535, i32 16, i32 16) nounwind readnone @@ -311,10 +311,10 @@ define void @bfe_i32_constant_fold_test_10(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_11: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -6 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -6 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_11(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 4, i32 4) nounwind readnone @@ -323,10 +323,10 @@ define void @bfe_i32_constant_fold_test_11(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_12: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_12(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 31, i32 1) nounwind readnone @@ -335,10 +335,10 @@ define void @bfe_i32_constant_fold_test_12(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_13: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_13(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 131070, i32 16, i32 16) nounwind readnone @@ -347,10 +347,10 @@ define void @bfe_i32_constant_fold_test_13(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_14: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 40 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 40 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_14(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 2, i32 30) nounwind readnone @@ -359,10 +359,10 @@ define void @bfe_i32_constant_fold_test_14(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_15: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 10 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 10 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_15(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 4, i32 28) nounwind readnone @@ -371,10 +371,10 @@ define void @bfe_i32_constant_fold_test_15(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_16: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_16(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 4294967295, i32 1, i32 7) nounwind readnone @@ -383,10 +383,10 @@ define void @bfe_i32_constant_fold_test_16(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_17: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x7f -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_17(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 255, i32 1, i32 31) nounwind readnone @@ -395,10 +395,10 @@ define void @bfe_i32_constant_fold_test_17(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_18: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_i32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind { %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 255, i32 31, i32 1) nounwind readnone @@ -409,13 +409,13 @@ define void @bfe_i32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind { ; XXX - This should really be a single BFE, but the sext_inreg of the ; extended type i24 is never custom lowered. ; FUNC-LABEL: {{^}}bfe_sext_in_reg_i24: -; SI: BUFFER_LOAD_DWORD [[LOAD:v[0-9]+]], -; SI: V_LSHLREV_B32_e32 {{v[0-9]+}}, 8, {{v[0-9]+}} -; SI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 8, {{v[0-9]+}} -; XSI: V_BFE_I32 [[BFE:v[0-9]+]], [[LOAD]], 0, 8 +; SI: buffer_load_dword [[LOAD:v[0-9]+]], +; SI: v_lshlrev_b32_e32 {{v[0-9]+}}, 8, {{v[0-9]+}} +; SI: v_ashrrev_i32_e32 {{v[0-9]+}}, 8, {{v[0-9]+}} +; XSI: v_bfe_i32 [[BFE:v[0-9]+]], [[LOAD]], 0, 8 ; XSI-NOT: SHL ; XSI-NOT: SHR -; XSI: BUFFER_STORE_DWORD [[BFE]], +; XSI: buffer_store_dword [[BFE]], define void @bfe_sext_in_reg_i24(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 0, i32 24) @@ -426,12 +426,12 @@ define void @bfe_sext_in_reg_i24(i32 addrspace(1)* %out, i32 addrspace(1)* %in) } ; FUNC-LABEL: @simplify_demanded_bfe_sdiv -; SI: BUFFER_LOAD_DWORD [[LOAD:v[0-9]+]] -; SI: V_BFE_I32 [[BFE:v[0-9]+]], [[LOAD]], 1, 16 -; SI: V_LSHRREV_B32_e32 [[TMP0:v[0-9]+]], 31, [[BFE]] -; SI: V_ADD_I32_e32 [[TMP1:v[0-9]+]], [[TMP0]], [[BFE]] -; SI: V_ASHRREV_I32_e32 [[TMP2:v[0-9]+]], 1, [[TMP1]] -; SI: BUFFER_STORE_DWORD [[TMP2]] +; SI: buffer_load_dword [[LOAD:v[0-9]+]] +; SI: v_bfe_i32 [[BFE:v[0-9]+]], [[LOAD]], 1, 16 +; SI: v_lshrrev_b32_e32 [[TMP0:v[0-9]+]], 31, [[BFE]] +; SI: v_add_i32_e32 [[TMP1:v[0-9]+]], [[TMP0]], [[BFE]] +; SI: v_ashrrev_i32_e32 [[TMP2:v[0-9]+]], 1, [[TMP1]] +; SI: buffer_store_dword [[TMP2]] define void @simplify_demanded_bfe_sdiv(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %src = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %src, i32 1, i32 16) nounwind readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll b/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll index 1d239af7aa4..0794ac4480d 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll @@ -4,7 +4,7 @@ declare i32 @llvm.AMDGPU.bfe.u32(i32, i32, i32) nounwind readnone ; FUNC-LABEL: {{^}}bfe_u32_arg_arg_arg: -; SI: V_BFE_U32 +; SI: v_bfe_u32 ; EG: BFE_UINT define void @bfe_u32_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 %src1, i32 %src1) nounwind readnone @@ -13,7 +13,7 @@ define void @bfe_u32_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i } ; FUNC-LABEL: {{^}}bfe_u32_arg_arg_imm: -; SI: V_BFE_U32 +; SI: v_bfe_u32 ; EG: BFE_UINT define void @bfe_u32_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 %src1, i32 123) nounwind readnone @@ -22,7 +22,7 @@ define void @bfe_u32_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) n } ; FUNC-LABEL: {{^}}bfe_u32_arg_imm_arg: -; SI: V_BFE_U32 +; SI: v_bfe_u32 ; EG: BFE_UINT define void @bfe_u32_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 123, i32 %src2) nounwind readnone @@ -31,7 +31,7 @@ define void @bfe_u32_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) n } ; FUNC-LABEL: {{^}}bfe_u32_imm_arg_arg: -; SI: V_BFE_U32 +; SI: v_bfe_u32 ; EG: BFE_UINT define void @bfe_u32_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 123, i32 %src1, i32 %src2) nounwind readnone @@ -40,8 +40,8 @@ define void @bfe_u32_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) n } ; FUNC-LABEL: {{^}}bfe_u32_arg_0_width_reg_offset: -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_arg_0_width_reg_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 %src1, i32 0) nounwind readnone @@ -50,8 +50,8 @@ define void @bfe_u32_arg_0_width_reg_offset(i32 addrspace(1)* %out, i32 %src0, i } ; FUNC-LABEL: {{^}}bfe_u32_arg_0_width_imm_offset: -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 8, i32 0) nounwind readnone @@ -60,9 +60,9 @@ define void @bfe_u32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i } ; FUNC-LABEL: {{^}}bfe_u32_zextload_i8: -; SI: BUFFER_LOAD_UBYTE -; SI-NOT: BFE -; SI: S_ENDPGM +; SI: buffer_load_ubyte +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_zextload_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind { %load = load i8 addrspace(1)* %in %ext = zext i8 %load to i32 @@ -72,11 +72,11 @@ define void @bfe_u32_zextload_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) n } ; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8: -; SI: BUFFER_LOAD_DWORD -; SI: V_ADD_I32 -; SI-NEXT: V_AND_B32_e32 -; SI-NOT: BFE -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI: v_add_i32 +; SI-NEXT: v_and_b32_e32 +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_zext_in_reg_i8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %load = load i32 addrspace(1)* %in, align 4 %add = add i32 %load, 1 @@ -87,11 +87,11 @@ define void @bfe_u32_zext_in_reg_i8(i32 addrspace(1)* %out, i32 addrspace(1)* %i } ; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i16: -; SI: BUFFER_LOAD_DWORD -; SI: V_ADD_I32 -; SI-NEXT: V_AND_B32_e32 -; SI-NOT: BFE -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI: v_add_i32 +; SI-NEXT: v_and_b32_e32 +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_zext_in_reg_i16(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %load = load i32 addrspace(1)* %in, align 4 %add = add i32 %load, 1 @@ -102,10 +102,10 @@ define void @bfe_u32_zext_in_reg_i16(i32 addrspace(1)* %out, i32 addrspace(1)* % } ; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8_offset_1: -; SI: BUFFER_LOAD_DWORD -; SI: V_ADD_I32 -; SI: BFE -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI: v_add_i32 +; SI: bfe +; SI: s_endpgm define void @bfe_u32_zext_in_reg_i8_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %load = load i32 addrspace(1)* %in, align 4 %add = add i32 %load, 1 @@ -116,11 +116,11 @@ define void @bfe_u32_zext_in_reg_i8_offset_1(i32 addrspace(1)* %out, i32 addrspa } ; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8_offset_3: -; SI: BUFFER_LOAD_DWORD -; SI: V_ADD_I32 -; SI-NEXT: V_AND_B32_e32 {{v[0-9]+}}, 0xf8 -; SI-NEXT: BFE -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI: v_add_i32 +; SI-NEXT: v_and_b32_e32 {{v[0-9]+}}, 0xf8 +; SI-NEXT: bfe +; SI: s_endpgm define void @bfe_u32_zext_in_reg_i8_offset_3(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %load = load i32 addrspace(1)* %in, align 4 %add = add i32 %load, 1 @@ -131,11 +131,11 @@ define void @bfe_u32_zext_in_reg_i8_offset_3(i32 addrspace(1)* %out, i32 addrspa } ; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8_offset_7: -; SI: BUFFER_LOAD_DWORD -; SI: V_ADD_I32 -; SI-NEXT: V_AND_B32_e32 {{v[0-9]+}}, 0x80 -; SI-NEXT: BFE -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI: v_add_i32 +; SI-NEXT: v_and_b32_e32 {{v[0-9]+}}, 0x80 +; SI-NEXT: bfe +; SI: s_endpgm define void @bfe_u32_zext_in_reg_i8_offset_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %load = load i32 addrspace(1)* %in, align 4 %add = add i32 %load, 1 @@ -146,10 +146,10 @@ define void @bfe_u32_zext_in_reg_i8_offset_7(i32 addrspace(1)* %out, i32 addrspa } ; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i16_offset_8: -; SI: BUFFER_LOAD_DWORD -; SI: V_ADD_I32 -; SI-NEXT: BFE -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI: v_add_i32 +; SI-NEXT: bfe +; SI: s_endpgm define void @bfe_u32_zext_in_reg_i16_offset_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %load = load i32 addrspace(1)* %in, align 4 %add = add i32 %load, 1 @@ -160,9 +160,9 @@ define void @bfe_u32_zext_in_reg_i16_offset_8(i32 addrspace(1)* %out, i32 addrsp } ; FUNC-LABEL: {{^}}bfe_u32_test_1: -; SI: BUFFER_LOAD_DWORD -; SI: V_AND_B32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}} -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI: v_and_b32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}} +; SI: s_endpgm ; EG: AND_INT T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, 1, define void @bfe_u32_test_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 @@ -188,12 +188,12 @@ define void @bfe_u32_test_3(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_u32_test_4: -; SI-NOT: LSHL -; SI-NOT: SHR -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: lshl +; SI-NOT: shr +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm define void @bfe_u32_test_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -204,11 +204,11 @@ define void @bfe_u32_test_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_u32_test_5: -; SI: BUFFER_LOAD_DWORD -; SI-NOT: LSHL -; SI-NOT: SHR -; SI: V_BFE_I32 {{v[0-9]+}}, {{v[0-9]+}}, 0, 1 -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI-NOT: lshl +; SI-NOT: shr +; SI: v_bfe_i32 {{v[0-9]+}}, {{v[0-9]+}}, 0, 1 +; SI: s_endpgm define void @bfe_u32_test_5(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -219,9 +219,9 @@ define void @bfe_u32_test_5(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_u32_test_6: -; SI: V_LSHLREV_B32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} -; SI: V_LSHRREV_B32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} +; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} +; SI: s_endpgm define void @bfe_u32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -231,9 +231,9 @@ define void @bfe_u32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_u32_test_7: -; SI: V_LSHLREV_B32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -243,10 +243,10 @@ define void @bfe_u32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_u32_test_8: -; SI-NOT: BFE -; SI: V_AND_B32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_and_b32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -256,10 +256,10 @@ define void @bfe_u32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_u32_test_9: -; SI-NOT: BFE -; SI: V_LSHRREV_B32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 31, i32 1) @@ -268,10 +268,10 @@ define void @bfe_u32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounw } ; FUNC-LABEL: {{^}}bfe_u32_test_10: -; SI-NOT: BFE -; SI: V_LSHRREV_B32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 1, i32 31) @@ -280,10 +280,10 @@ define void @bfe_u32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun } ; FUNC-LABEL: {{^}}bfe_u32_test_11: -; SI-NOT: BFE -; SI: V_LSHRREV_B32_e32 v{{[0-9]+}}, 8, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 8, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 8, i32 24) @@ -292,10 +292,10 @@ define void @bfe_u32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun } ; FUNC-LABEL: {{^}}bfe_u32_test_12: -; SI-NOT: BFE -; SI: V_LSHRREV_B32_e32 v{{[0-9]+}}, 24, v{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 24, v{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 24, i32 8) @@ -305,8 +305,8 @@ define void @bfe_u32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun ; FUNC-LABEL: {{^}}bfe_u32_test_13: ; V_ASHRREV_U32_e32 {{v[0-9]+}}, 31, {{v[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = ashr i32 %x, 31 @@ -315,9 +315,9 @@ define void @bfe_u32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun } ; FUNC-LABEL: {{^}}bfe_u32_test_14: -; SI-NOT: LSHR -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: lshr +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_u32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = lshr i32 %x, 31 @@ -326,10 +326,10 @@ define void @bfe_u32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) noun } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_0: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_0(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 0, i32 0, i32 0) nounwind readnone @@ -338,10 +338,10 @@ define void @bfe_u32_constant_fold_test_0(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_1: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_1(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 12334, i32 0, i32 0) nounwind readnone @@ -350,10 +350,10 @@ define void @bfe_u32_constant_fold_test_1(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_2: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_2(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 0, i32 0, i32 1) nounwind readnone @@ -362,10 +362,10 @@ define void @bfe_u32_constant_fold_test_2(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_3: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_3(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 1, i32 0, i32 1) nounwind readnone @@ -374,10 +374,10 @@ define void @bfe_u32_constant_fold_test_3(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_4: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_4(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 4294967295, i32 0, i32 1) nounwind readnone @@ -386,10 +386,10 @@ define void @bfe_u32_constant_fold_test_4(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_5: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_5(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 128, i32 7, i32 1) nounwind readnone @@ -398,10 +398,10 @@ define void @bfe_u32_constant_fold_test_5(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_6: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x80 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x80 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_6(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 128, i32 0, i32 8) nounwind readnone @@ -410,10 +410,10 @@ define void @bfe_u32_constant_fold_test_6(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_7: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x7f -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_7(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 127, i32 0, i32 8) nounwind readnone @@ -422,10 +422,10 @@ define void @bfe_u32_constant_fold_test_7(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_8: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_8(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 127, i32 6, i32 8) nounwind readnone @@ -434,10 +434,10 @@ define void @bfe_u32_constant_fold_test_8(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_9: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFEfppppppppppppp define void @bfe_u32_constant_fold_test_9(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 65536, i32 16, i32 8) nounwind readnone @@ -446,10 +446,10 @@ define void @bfe_u32_constant_fold_test_9(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_10: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_10(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 65535, i32 16, i32 16) nounwind readnone @@ -458,10 +458,10 @@ define void @bfe_u32_constant_fold_test_10(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_11: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 10 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 10 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_11(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 4, i32 4) nounwind readnone @@ -470,10 +470,10 @@ define void @bfe_u32_constant_fold_test_11(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_12: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_12(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 31, i32 1) nounwind readnone @@ -482,10 +482,10 @@ define void @bfe_u32_constant_fold_test_12(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_13: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_13(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 131070, i32 16, i32 16) nounwind readnone @@ -494,10 +494,10 @@ define void @bfe_u32_constant_fold_test_13(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_14: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 40 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 40 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_14(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 2, i32 30) nounwind readnone @@ -506,10 +506,10 @@ define void @bfe_u32_constant_fold_test_14(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_15: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 10 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 10 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_15(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 4, i32 28) nounwind readnone @@ -518,10 +518,10 @@ define void @bfe_u32_constant_fold_test_15(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_16: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x7f -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_16(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 4294967295, i32 1, i32 7) nounwind readnone @@ -530,10 +530,10 @@ define void @bfe_u32_constant_fold_test_16(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_17: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x7f -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_17(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 255, i32 1, i32 31) nounwind readnone @@ -542,10 +542,10 @@ define void @bfe_u32_constant_fold_test_17(i32 addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_18: -; SI-NOT: BFE -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0 -; SI: BUFFER_STORE_DWORD [[VREG]], -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 +; SI: buffer_store_dword [[VREG]], +; SI: s_endpgm ; EG-NOT: BFE define void @bfe_u32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind { %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 255, i32 31, i32 1) nounwind readnone @@ -558,12 +558,12 @@ define void @bfe_u32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind { ; XXX: The operand to v_bfe_u32 could also just directly be the load register. ; FUNC-LABEL: {{^}}simplify_bfe_u32_multi_use_arg: -; SI: BUFFER_LOAD_DWORD [[ARG:v[0-9]+]] -; SI: V_AND_B32_e32 [[AND:v[0-9]+]], 63, [[ARG]] -; SI: V_BFE_U32 [[BFE:v[0-9]+]], [[AND]], 2, 2 -; SI-DAG: BUFFER_STORE_DWORD [[AND]] -; SI-DAG: BUFFER_STORE_DWORD [[BFE]] -; SI: S_ENDPGM +; SI: buffer_load_dword [[ARG:v[0-9]+]] +; SI: v_and_b32_e32 [[AND:v[0-9]+]], 63, [[ARG]] +; SI: v_bfe_u32 [[BFE:v[0-9]+]], [[AND]], 2, 2 +; SI-DAG: buffer_store_dword [[AND]] +; SI-DAG: buffer_store_dword [[BFE]] +; SI: s_endpgm define void @simplify_bfe_u32_multi_use_arg(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %in) nounwind { diff --git a/test/CodeGen/R600/llvm.AMDGPU.bfi.ll b/test/CodeGen/R600/llvm.AMDGPU.bfi.ll index 698f374872e..df61b0b0793 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.bfi.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.bfi.ll @@ -4,7 +4,7 @@ declare i32 @llvm.AMDGPU.bfi(i32, i32, i32) nounwind readnone ; FUNC-LABEL: {{^}}bfi_arg_arg_arg: -; SI: V_BFI_B32 +; SI: v_bfi_b32 ; EG: BFI_INT define void @bfi_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind { %bfi = call i32 @llvm.AMDGPU.bfi(i32 %src0, i32 %src1, i32 %src1) nounwind readnone @@ -13,7 +13,7 @@ define void @bfi_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 % } ; FUNC-LABEL: {{^}}bfi_arg_arg_imm: -; SI: V_BFI_B32 +; SI: v_bfi_b32 ; EG: BFI_INT define void @bfi_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { %bfi = call i32 @llvm.AMDGPU.bfi(i32 %src0, i32 %src1, i32 123) nounwind readnone @@ -22,7 +22,7 @@ define void @bfi_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounw } ; FUNC-LABEL: {{^}}bfi_arg_imm_arg: -; SI: V_BFI_B32 +; SI: v_bfi_b32 ; EG: BFI_INT define void @bfi_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) nounwind { %bfi = call i32 @llvm.AMDGPU.bfi(i32 %src0, i32 123, i32 %src2) nounwind readnone @@ -31,7 +31,7 @@ define void @bfi_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) nounw } ; FUNC-LABEL: {{^}}bfi_imm_arg_arg: -; SI: V_BFI_B32 +; SI: v_bfi_b32 ; EG: BFI_INT define void @bfi_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) nounwind { %bfi = call i32 @llvm.AMDGPU.bfi(i32 123, i32 %src1, i32 %src2) nounwind readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.bfm.ll b/test/CodeGen/R600/llvm.AMDGPU.bfm.ll index d1b0b3ee41a..0ba4af50cb0 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.bfm.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.bfm.ll @@ -4,7 +4,7 @@ declare i32 @llvm.AMDGPU.bfm(i32, i32) nounwind readnone ; FUNC-LABEL: {{^}}bfm_arg_arg: -; SI: V_BFM +; SI: v_bfm ; EG: BFM_INT define void @bfm_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { %bfm = call i32 @llvm.AMDGPU.bfm(i32 %src0, i32 %src1) nounwind readnone @@ -13,7 +13,7 @@ define void @bfm_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind } ; FUNC-LABEL: {{^}}bfm_arg_imm: -; SI: V_BFM +; SI: v_bfm ; EG: BFM_INT define void @bfm_arg_imm(i32 addrspace(1)* %out, i32 %src0) nounwind { %bfm = call i32 @llvm.AMDGPU.bfm(i32 %src0, i32 123) nounwind readnone @@ -22,7 +22,7 @@ define void @bfm_arg_imm(i32 addrspace(1)* %out, i32 %src0) nounwind { } ; FUNC-LABEL: {{^}}bfm_imm_arg: -; SI: V_BFM +; SI: v_bfm ; EG: BFM_INT define void @bfm_imm_arg(i32 addrspace(1)* %out, i32 %src1) nounwind { %bfm = call i32 @llvm.AMDGPU.bfm(i32 123, i32 %src1) nounwind readnone @@ -31,7 +31,7 @@ define void @bfm_imm_arg(i32 addrspace(1)* %out, i32 %src1) nounwind { } ; FUNC-LABEL: {{^}}bfm_imm_imm: -; SI: V_BFM +; SI: v_bfm ; EG: BFM_INT define void @bfm_imm_imm(i32 addrspace(1)* %out) nounwind { %bfm = call i32 @llvm.AMDGPU.bfm(i32 123, i32 456) nounwind readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.brev.ll b/test/CodeGen/R600/llvm.AMDGPU.brev.ll index 87f6cb4230b..647df347861 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.brev.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.brev.ll @@ -3,11 +3,11 @@ declare i32 @llvm.AMDGPU.brev(i32) nounwind readnone ; FUNC-LABEL: {{^}}s_brev_i32: -; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], -; SI: S_BREV_B32 [[SRESULT:s[0-9]+]], [[VAL]] -; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] -; SI: BUFFER_STORE_DWORD [[VRESULT]], -; SI: S_ENDPGM +; SI: s_load_dword [[VAL:s[0-9]+]], +; SI: s_brev_b32 [[SRESULT:s[0-9]+]], [[VAL]] +; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] +; SI: buffer_store_dword [[VRESULT]], +; SI: s_endpgm define void @s_brev_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { %ctlz = call i32 @llvm.AMDGPU.brev(i32 %val) nounwind readnone store i32 %ctlz, i32 addrspace(1)* %out, align 4 @@ -15,10 +15,10 @@ define void @s_brev_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { } ; FUNC-LABEL: {{^}}v_brev_i32: -; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]], -; SI: V_BFREV_B32_e32 [[RESULT:v[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: buffer_load_dword [[VAL:v[0-9]+]], +; SI: v_bfrev_b32_e32 [[RESULT:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm define void @v_brev_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { %val = load i32 addrspace(1)* %valptr, align 4 %ctlz = call i32 @llvm.AMDGPU.brev(i32 %val) nounwind readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.clamp.ll b/test/CodeGen/R600/llvm.AMDGPU.clamp.ll index 11c887f204b..9cf7ca86c52 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.clamp.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.clamp.ll @@ -5,10 +5,10 @@ declare float @llvm.AMDGPU.clamp.f32(float, float, float) nounwind readnone declare float @llvm.AMDIL.clamp.f32(float, float, float) nounwind readnone ; FUNC-LABEL: {{^}}clamp_0_1_f32: -; SI: S_LOAD_DWORD [[ARG:s[0-9]+]], -; SI: V_ADD_F32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}} -; SI: BUFFER_STORE_DWORD [[RESULT]] -; SI: S_ENDPGM +; SI: s_load_dword [[ARG:s[0-9]+]], +; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}} +; SI: buffer_store_dword [[RESULT]] +; SI: s_endpgm ; EG: MOV_SAT define void @clamp_0_1_f32(float addrspace(1)* %out, float %src) nounwind { @@ -18,9 +18,9 @@ define void @clamp_0_1_f32(float addrspace(1)* %out, float %src) nounwind { } ; FUNC-LABEL: {{^}}clamp_0_1_amdil_legacy_f32: -; SI: S_LOAD_DWORD [[ARG:s[0-9]+]], -; SI: V_ADD_F32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}} -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI: s_load_dword [[ARG:s[0-9]+]], +; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}} +; SI: buffer_store_dword [[RESULT]] define void @clamp_0_1_amdil_legacy_f32(float addrspace(1)* %out, float %src) nounwind { %clamp = call float @llvm.AMDIL.clamp.f32(float %src, float 0.0, float 1.0) nounwind readnone store float %clamp, float addrspace(1)* %out, align 4 diff --git a/test/CodeGen/R600/llvm.AMDGPU.cvt_f32_ubyte.ll b/test/CodeGen/R600/llvm.AMDGPU.cvt_f32_ubyte.ll index 4295d24d8bd..7aacbb95432 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.cvt_f32_ubyte.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.cvt_f32_ubyte.ll @@ -6,7 +6,7 @@ declare float @llvm.AMDGPU.cvt.f32.ubyte2(i32) nounwind readnone declare float @llvm.AMDGPU.cvt.f32.ubyte3(i32) nounwind readnone ; SI-LABEL: {{^}}test_unpack_byte0_to_float: -; SI: V_CVT_F32_UBYTE0 +; SI: v_cvt_f32_ubyte0 define void @test_unpack_byte0_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %val = load i32 addrspace(1)* %in, align 4 %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte0(i32 %val) nounwind readnone @@ -15,7 +15,7 @@ define void @test_unpack_byte0_to_float(float addrspace(1)* %out, i32 addrspace( } ; SI-LABEL: {{^}}test_unpack_byte1_to_float: -; SI: V_CVT_F32_UBYTE1 +; SI: v_cvt_f32_ubyte1 define void @test_unpack_byte1_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %val = load i32 addrspace(1)* %in, align 4 %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %val) nounwind readnone @@ -24,7 +24,7 @@ define void @test_unpack_byte1_to_float(float addrspace(1)* %out, i32 addrspace( } ; SI-LABEL: {{^}}test_unpack_byte2_to_float: -; SI: V_CVT_F32_UBYTE2 +; SI: v_cvt_f32_ubyte2 define void @test_unpack_byte2_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %val = load i32 addrspace(1)* %in, align 4 %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte2(i32 %val) nounwind readnone @@ -33,7 +33,7 @@ define void @test_unpack_byte2_to_float(float addrspace(1)* %out, i32 addrspace( } ; SI-LABEL: {{^}}test_unpack_byte3_to_float: -; SI: V_CVT_F32_UBYTE3 +; SI: v_cvt_f32_ubyte3 define void @test_unpack_byte3_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %val = load i32 addrspace(1)* %in, align 4 %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte3(i32 %val) nounwind readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll b/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll index 7fbbc2104f8..009fd737d00 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll @@ -4,14 +4,14 @@ declare float @llvm.AMDGPU.div.fixup.f32(float, float, float) nounwind readnone declare double @llvm.AMDGPU.div.fixup.f64(double, double, double) nounwind readnone ; SI-LABEL: {{^}}test_div_fixup_f32: -; SI-DAG: S_LOAD_DWORD [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: S_LOAD_DWORD [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: S_LOAD_DWORD [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI-DAG: V_MOV_B32_e32 [[VC:v[0-9]+]], [[SC]] -; SI-DAG: V_MOV_B32_e32 [[VB:v[0-9]+]], [[SB]] -; SI: V_DIV_FIXUP_F32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] +; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] +; SI: v_div_fixup_f32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm define void @test_div_fixup_f32(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { %result = call float @llvm.AMDGPU.div.fixup.f32(float %a, float %b, float %c) nounwind readnone store float %result, float addrspace(1)* %out, align 4 @@ -19,7 +19,7 @@ define void @test_div_fixup_f32(float addrspace(1)* %out, float %a, float %b, fl } ; SI-LABEL: {{^}}test_div_fixup_f64: -; SI: V_DIV_FIXUP_F64 +; SI: v_div_fixup_f64 define void @test_div_fixup_f64(double addrspace(1)* %out, double %a, double %b, double %c) nounwind { %result = call double @llvm.AMDGPU.div.fixup.f64(double %a, double %b, double %c) nounwind readnone store double %result, double addrspace(1)* %out, align 8 diff --git a/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll b/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll index 43bfc7cd3f0..dcca9e95adc 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll @@ -4,14 +4,14 @@ declare float @llvm.AMDGPU.div.fmas.f32(float, float, float, i1) nounwind readno declare double @llvm.AMDGPU.div.fmas.f64(double, double, double, i1) nounwind readnone ; SI-LABEL: {{^}}test_div_fmas_f32: -; SI-DAG: S_LOAD_DWORD [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: S_LOAD_DWORD [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: S_LOAD_DWORD [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI-DAG: V_MOV_B32_e32 [[VC:v[0-9]+]], [[SC]] -; SI-DAG: V_MOV_B32_e32 [[VB:v[0-9]+]], [[SB]] -; SI: V_DIV_FMAS_F32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] +; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] +; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm define void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind { %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone store float %result, float addrspace(1)* %out, align 4 @@ -19,7 +19,7 @@ define void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, flo } ; SI-LABEL: {{^}}test_div_fmas_f64: -; SI: V_DIV_FMAS_F64 +; SI: v_div_fmas_f64 define void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind { %result = call double @llvm.AMDGPU.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone store double %result, double addrspace(1)* %out, align 8 diff --git a/test/CodeGen/R600/llvm.AMDGPU.div_scale.ll b/test/CodeGen/R600/llvm.AMDGPU.div_scale.ll index 1c192ea659c..641c8caf7e2 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.div_scale.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.div_scale.ll @@ -5,11 +5,11 @@ declare { float, i1 } @llvm.AMDGPU.div.scale.f32(float, float, i1) nounwind read declare { double, i1 } @llvm.AMDGPU.div.scale.f64(double, double, i1) nounwind readnone ; SI-LABEL @test_div_scale_f32_1: -; SI-DAG: BUFFER_LOAD_DWORD [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 -; SI-DAG: BUFFER_LOAD_DWORD [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 -; SI: V_DIV_SCALE_F32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] -; SI: BUFFER_STORE_DWORD [[RESULT0]] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 +; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm define void @test_div_scale_f32_1(float addrspace(1)* %out, float addrspace(1)* %in) nounwind { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid @@ -25,11 +25,11 @@ define void @test_div_scale_f32_1(float addrspace(1)* %out, float addrspace(1)* } ; SI-LABEL @test_div_scale_f32_2: -; SI-DAG: BUFFER_LOAD_DWORD [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 -; SI-DAG: BUFFER_LOAD_DWORD [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 -; SI: V_DIV_SCALE_F32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] -; SI: BUFFER_STORE_DWORD [[RESULT0]] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 +; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm define void @test_div_scale_f32_2(float addrspace(1)* %out, float addrspace(1)* %in) nounwind { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid @@ -45,11 +45,11 @@ define void @test_div_scale_f32_2(float addrspace(1)* %out, float addrspace(1)* } ; SI-LABEL @test_div_scale_f64_1: -; SI-DAG: BUFFER_LOAD_DWORDX2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 -; SI-DAG: BUFFER_LOAD_DWORDX2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x8 -; SI: V_DIV_SCALE_F64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] -; SI: BUFFER_STORE_DWORDX2 [[RESULT0]] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 +; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x8 +; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] +; SI: buffer_store_dwordx2 [[RESULT0]] +; SI: s_endpgm define void @test_div_scale_f64_1(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) nounwind { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep.0 = getelementptr double addrspace(1)* %in, i32 %tid @@ -65,11 +65,11 @@ define void @test_div_scale_f64_1(double addrspace(1)* %out, double addrspace(1) } ; SI-LABEL @test_div_scale_f64_1: -; SI-DAG: BUFFER_LOAD_DWORDX2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 -; SI-DAG: BUFFER_LOAD_DWORDX2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x8 -; SI: V_DIV_SCALE_F64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] -; SI: BUFFER_STORE_DWORDX2 [[RESULT0]] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 +; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x8 +; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] +; SI: buffer_store_dwordx2 [[RESULT0]] +; SI: s_endpgm define void @test_div_scale_f64_2(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) nounwind { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep.0 = getelementptr double addrspace(1)* %in, i32 %tid @@ -85,11 +85,11 @@ define void @test_div_scale_f64_2(double addrspace(1)* %out, double addrspace(1) } ; SI-LABEL @test_div_scale_f32_scalar_num_1: -; SI-DAG: BUFFER_LOAD_DWORD [[B:v[0-9]+]] -; SI-DAG: S_LOAD_DWORD [[A:s[0-9]+]] -; SI: V_DIV_SCALE_F32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] -; SI: BUFFER_STORE_DWORD [[RESULT0]] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[B:v[0-9]+]] +; SI-DAG: s_load_dword [[A:s[0-9]+]] +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm define void @test_div_scale_f32_scalar_num_1(float addrspace(1)* %out, float addrspace(1)* %in, float %a) nounwind { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep = getelementptr float addrspace(1)* %in, i32 %tid @@ -103,11 +103,11 @@ define void @test_div_scale_f32_scalar_num_1(float addrspace(1)* %out, float add } ; SI-LABEL @test_div_scale_f32_scalar_num_2: -; SI-DAG: BUFFER_LOAD_DWORD [[B:v[0-9]+]] -; SI-DAG: S_LOAD_DWORD [[A:s[0-9]+]] -; SI: V_DIV_SCALE_F32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] -; SI: BUFFER_STORE_DWORD [[RESULT0]] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[B:v[0-9]+]] +; SI-DAG: s_load_dword [[A:s[0-9]+]] +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm define void @test_div_scale_f32_scalar_num_2(float addrspace(1)* %out, float addrspace(1)* %in, float %a) nounwind { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep = getelementptr float addrspace(1)* %in, i32 %tid @@ -121,11 +121,11 @@ define void @test_div_scale_f32_scalar_num_2(float addrspace(1)* %out, float add } ; SI-LABEL @test_div_scale_f32_scalar_den_1: -; SI-DAG: BUFFER_LOAD_DWORD [[A:v[0-9]+]] -; SI-DAG: S_LOAD_DWORD [[B:s[0-9]+]] -; SI: V_DIV_SCALE_F32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] -; SI: BUFFER_STORE_DWORD [[RESULT0]] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[A:v[0-9]+]] +; SI-DAG: s_load_dword [[B:s[0-9]+]] +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm define void @test_div_scale_f32_scalar_den_1(float addrspace(1)* %out, float addrspace(1)* %in, float %b) nounwind { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep = getelementptr float addrspace(1)* %in, i32 %tid @@ -139,11 +139,11 @@ define void @test_div_scale_f32_scalar_den_1(float addrspace(1)* %out, float add } ; SI-LABEL @test_div_scale_f32_scalar_den_2: -; SI-DAG: BUFFER_LOAD_DWORD [[A:v[0-9]+]] -; SI-DAG: S_LOAD_DWORD [[B:s[0-9]+]] -; SI: V_DIV_SCALE_F32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] -; SI: BUFFER_STORE_DWORD [[RESULT0]] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[A:v[0-9]+]] +; SI-DAG: s_load_dword [[B:s[0-9]+]] +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm define void @test_div_scale_f32_scalar_den_2(float addrspace(1)* %out, float addrspace(1)* %in, float %b) nounwind { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep = getelementptr float addrspace(1)* %in, i32 %tid @@ -157,11 +157,11 @@ define void @test_div_scale_f32_scalar_den_2(float addrspace(1)* %out, float add } ; SI-LABEL @test_div_scale_f64_scalar_num_1: -; SI-DAG: BUFFER_LOAD_DWORDX2 [[B:v\[[0-9]+:[0-9]+\]]] -; SI-DAG: S_LOAD_DWORDX2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd -; SI: V_DIV_SCALE_F64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] -; SI: BUFFER_STORE_DWORDX2 [[RESULT0]] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]] +; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd +; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] +; SI: buffer_store_dwordx2 [[RESULT0]] +; SI: s_endpgm define void @test_div_scale_f64_scalar_num_1(double addrspace(1)* %out, double addrspace(1)* %in, double %a) nounwind { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep = getelementptr double addrspace(1)* %in, i32 %tid @@ -175,11 +175,11 @@ define void @test_div_scale_f64_scalar_num_1(double addrspace(1)* %out, double a } ; SI-LABEL @test_div_scale_f64_scalar_num_2: -; SI-DAG: S_LOAD_DWORDX2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: BUFFER_LOAD_DWORDX2 [[B:v\[[0-9]+:[0-9]+\]]] -; SI: V_DIV_SCALE_F64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] -; SI: BUFFER_STORE_DWORDX2 [[RESULT0]] -; SI: S_ENDPGM +; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]] +; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] +; SI: buffer_store_dwordx2 [[RESULT0]] +; SI: s_endpgm define void @test_div_scale_f64_scalar_num_2(double addrspace(1)* %out, double addrspace(1)* %in, double %a) nounwind { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep = getelementptr double addrspace(1)* %in, i32 %tid @@ -193,11 +193,11 @@ define void @test_div_scale_f64_scalar_num_2(double addrspace(1)* %out, double a } ; SI-LABEL @test_div_scale_f64_scalar_den_1: -; SI-DAG: BUFFER_LOAD_DWORDX2 [[A:v\[[0-9]+:[0-9]+\]]] -; SI-DAG: S_LOAD_DWORDX2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd -; SI: V_DIV_SCALE_F64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] -; SI: BUFFER_STORE_DWORDX2 [[RESULT0]] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]] +; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd +; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] +; SI: buffer_store_dwordx2 [[RESULT0]] +; SI: s_endpgm define void @test_div_scale_f64_scalar_den_1(double addrspace(1)* %out, double addrspace(1)* %in, double %b) nounwind { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep = getelementptr double addrspace(1)* %in, i32 %tid @@ -211,11 +211,11 @@ define void @test_div_scale_f64_scalar_den_1(double addrspace(1)* %out, double a } ; SI-LABEL @test_div_scale_f64_scalar_den_2: -; SI-DAG: BUFFER_LOAD_DWORDX2 [[A:v\[[0-9]+:[0-9]+\]]] -; SI-DAG: S_LOAD_DWORDX2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd -; SI: V_DIV_SCALE_F64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] -; SI: BUFFER_STORE_DWORDX2 [[RESULT0]] -; SI: S_ENDPGM +; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]] +; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd +; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] +; SI: buffer_store_dwordx2 [[RESULT0]] +; SI: s_endpgm define void @test_div_scale_f64_scalar_den_2(double addrspace(1)* %out, double addrspace(1)* %in, double %b) nounwind { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep = getelementptr double addrspace(1)* %in, i32 %tid @@ -229,12 +229,12 @@ define void @test_div_scale_f64_scalar_den_2(double addrspace(1)* %out, double a } ; SI-LABEL @test_div_scale_f32_all_scalar_1: -; SI-DAG: S_LOAD_DWORD [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: S_LOAD_DWORD [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc -; SI: V_MOV_B32_e32 [[VA:v[0-9]+]], [[A]] -; SI: V_DIV_SCALE_F32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[VA]] -; SI: BUFFER_STORE_DWORD [[RESULT0]] -; SI: S_ENDPGM +; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc +; SI: v_mov_b32_e32 [[VA:v[0-9]+]], [[A]] +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[VA]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm define void @test_div_scale_f32_all_scalar_1(float addrspace(1)* %out, float %a, float %b) nounwind { %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone %result0 = extractvalue { float, i1 } %result, 0 @@ -243,12 +243,12 @@ define void @test_div_scale_f32_all_scalar_1(float addrspace(1)* %out, float %a, } ; SI-LABEL @test_div_scale_f32_all_scalar_2: -; SI-DAG: S_LOAD_DWORD [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: S_LOAD_DWORD [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc -; SI: V_MOV_B32_e32 [[VB:v[0-9]+]], [[B]] -; SI: V_DIV_SCALE_F32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[VB]], [[A]] -; SI: BUFFER_STORE_DWORD [[RESULT0]] -; SI: S_ENDPGM +; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc +; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]] +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[VB]], [[A]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm define void @test_div_scale_f32_all_scalar_2(float addrspace(1)* %out, float %a, float %b) nounwind { %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone %result0 = extractvalue { float, i1 } %result, 0 @@ -257,13 +257,13 @@ define void @test_div_scale_f32_all_scalar_2(float addrspace(1)* %out, float %a, } ; SI-LABEL @test_div_scale_f64_all_scalar_1: -; SI-DAG: S_LOAD_DWORDX2 s{{\[}}[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: S_LOAD_DWORDX2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: V_MOV_B32_e32 v[[VA_LO:[0-9]+]], s[[A_LO]] -; SI-DAG: V_MOV_B32_e32 v[[VA_HI:[0-9]+]], s[[A_HI]] -; SI: V_DIV_SCALE_F64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], v{{\[}}[[VA_LO]]:[[VA_HI]]{{\]}} -; SI: BUFFER_STORE_DWORDX2 [[RESULT0]] -; SI: S_ENDPGM +; SI-DAG: s_load_dwordx2 s{{\[}}[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: v_mov_b32_e32 v[[VA_LO:[0-9]+]], s[[A_LO]] +; SI-DAG: v_mov_b32_e32 v[[VA_HI:[0-9]+]], s[[A_HI]] +; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], v{{\[}}[[VA_LO]]:[[VA_HI]]{{\]}} +; SI: buffer_store_dwordx2 [[RESULT0]] +; SI: s_endpgm define void @test_div_scale_f64_all_scalar_1(double addrspace(1)* %out, double %a, double %b) nounwind { %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone %result0 = extractvalue { double, i1 } %result, 0 @@ -272,13 +272,13 @@ define void @test_div_scale_f64_all_scalar_1(double addrspace(1)* %out, double % } ; SI-LABEL @test_div_scale_f64_all_scalar_2: -; SI-DAG: S_LOAD_DWORDX2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: S_LOAD_DWORDX2 s{{\[}}[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: V_MOV_B32_e32 v[[VB_LO:[0-9]+]], s[[B_LO]] -; SI-DAG: V_MOV_B32_e32 v[[VB_HI:[0-9]+]], s[[B_HI]] -; SI: V_DIV_SCALE_F64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], v{{\[}}[[VB_LO]]:[[VB_HI]]{{\]}}, [[A]] -; SI: BUFFER_STORE_DWORDX2 [[RESULT0]] -; SI: S_ENDPGM +; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dwordx2 s{{\[}}[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: v_mov_b32_e32 v[[VB_LO:[0-9]+]], s[[B_LO]] +; SI-DAG: v_mov_b32_e32 v[[VB_HI:[0-9]+]], s[[B_HI]] +; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], v{{\[}}[[VB_LO]]:[[VB_HI]]{{\]}}, [[A]] +; SI: buffer_store_dwordx2 [[RESULT0]] +; SI: s_endpgm define void @test_div_scale_f64_all_scalar_2(double addrspace(1)* %out, double %a, double %b) nounwind { %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone %result0 = extractvalue { double, i1 } %result, 0 diff --git a/test/CodeGen/R600/llvm.AMDGPU.fract.ll b/test/CodeGen/R600/llvm.AMDGPU.fract.ll index 7463b942dde..235068c146f 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.fract.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.fract.ll @@ -7,7 +7,7 @@ declare float @llvm.AMDGPU.fract.f32(float) nounwind readnone declare float @llvm.AMDIL.fraction.f32(float) nounwind readnone ; FUNC-LABEL: {{^}}fract_f32: -; SI: V_FRACT_F32 +; SI: v_fract_f32 ; EG: FRACT define void @fract_f32(float addrspace(1)* %out, float addrspace(1)* %src) nounwind { %val = load float addrspace(1)* %src, align 4 @@ -17,7 +17,7 @@ define void @fract_f32(float addrspace(1)* %out, float addrspace(1)* %src) nounw } ; FUNC-LABEL: {{^}}fract_f32_legacy_amdil: -; SI: V_FRACT_F32 +; SI: v_fract_f32 ; EG: FRACT define void @fract_f32_legacy_amdil(float addrspace(1)* %out, float addrspace(1)* %src) nounwind { %val = load float addrspace(1)* %src, align 4 diff --git a/test/CodeGen/R600/llvm.AMDGPU.imad24.ll b/test/CodeGen/R600/llvm.AMDGPU.imad24.ll index e1b41c4ac8d..89988406fda 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.imad24.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.imad24.ll @@ -9,7 +9,7 @@ declare i32 @llvm.AMDGPU.imad24(i32, i32, i32) nounwind readnone ; FUNC-LABEL: {{^}}test_imad24: -; SI: V_MAD_I32_I24 +; SI: v_mad_i32_i24 ; CM: MULADD_INT24 ; R600: MULLO_INT ; R600: ADD_INT diff --git a/test/CodeGen/R600/llvm.AMDGPU.imax.ll b/test/CodeGen/R600/llvm.AMDGPU.imax.ll index 36f5ac7766d..dac21a460cd 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.imax.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.imax.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s ; SI-LABEL: {{^}}vector_imax: -; SI: V_MAX_I32_e32 +; SI: v_max_i32_e32 define void @vector_imax(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 { main_body: %load = load i32 addrspace(1)* %in, align 4 @@ -12,7 +12,7 @@ main_body: } ; SI-LABEL: {{^}}scalar_imax: -; SI: S_MAX_I32 +; SI: s_max_i32 define void @scalar_imax(i32 %p0, i32 %p1) #0 { entry: %max = call i32 @llvm.AMDGPU.imax(i32 %p0, i32 %p1) diff --git a/test/CodeGen/R600/llvm.AMDGPU.imin.ll b/test/CodeGen/R600/llvm.AMDGPU.imin.ll index e7ae7bd5f0d..462c497dfda 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.imin.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.imin.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s ; SI-LABEL: {{^}}vector_imin: -; SI: V_MIN_I32_e32 +; SI: v_min_i32_e32 define void @vector_imin(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 { main_body: %load = load i32 addrspace(1)* %in, align 4 @@ -12,7 +12,7 @@ main_body: } ; SI-LABEL: {{^}}scalar_imin: -; SI: S_MIN_I32 +; SI: s_min_i32 define void @scalar_imin(i32 %p0, i32 %p1) #0 { entry: %min = call i32 @llvm.AMDGPU.imin(i32 %p0, i32 %p1) diff --git a/test/CodeGen/R600/llvm.AMDGPU.imul24.ll b/test/CodeGen/R600/llvm.AMDGPU.imul24.ll index 2b0d87601a0..db563dd5b44 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.imul24.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.imul24.ll @@ -5,7 +5,7 @@ declare i32 @llvm.AMDGPU.imul24(i32, i32) nounwind readnone ; FUNC-LABEL: {{^}}test_imul24: -; SI: V_MUL_I32_I24 +; SI: v_mul_i32_i24 ; CM: MUL_INT24 ; R600: MULLO_INT define void @test_imul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { diff --git a/test/CodeGen/R600/llvm.AMDGPU.kill.ll b/test/CodeGen/R600/llvm.AMDGPU.kill.ll index 0d61eb637ed..988b43c9ad8 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.kill.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.kill.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=r600 -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; SI-LABEL: {{^}}kill_gs_const: -; SI-NOT: V_CMPX_LE_F32 -; SI: S_MOV_B64 exec, 0 +; SI-NOT: v_cmpx_le_f32 +; SI: s_mov_b64 exec, 0 define void @kill_gs_const() #0 { main_body: diff --git a/test/CodeGen/R600/llvm.AMDGPU.ldexp.ll b/test/CodeGen/R600/llvm.AMDGPU.ldexp.ll index 473b95142d2..72719fe8686 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.ldexp.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.ldexp.ll @@ -4,8 +4,8 @@ declare float @llvm.AMDGPU.ldexp.f32(float, i32) nounwind readnone declare double @llvm.AMDGPU.ldexp.f64(double, i32) nounwind readnone ; SI-LABEL: {{^}}test_ldexp_f32: -; SI: V_LDEXP_F32 -; SI: S_ENDPGM +; SI: v_ldexp_f32 +; SI: s_endpgm define void @test_ldexp_f32(float addrspace(1)* %out, float %a, i32 %b) nounwind { %result = call float @llvm.AMDGPU.ldexp.f32(float %a, i32 %b) nounwind readnone store float %result, float addrspace(1)* %out, align 4 @@ -13,8 +13,8 @@ define void @test_ldexp_f32(float addrspace(1)* %out, float %a, i32 %b) nounwind } ; SI-LABEL: {{^}}test_ldexp_f64: -; SI: V_LDEXP_F64 -; SI: S_ENDPGM +; SI: v_ldexp_f64 +; SI: s_endpgm define void @test_ldexp_f64(double addrspace(1)* %out, double %a, i32 %b) nounwind { %result = call double @llvm.AMDGPU.ldexp.f64(double %a, i32 %b) nounwind readnone store double %result, double addrspace(1)* %out, align 8 diff --git a/test/CodeGen/R600/llvm.AMDGPU.legacy.rsq.ll b/test/CodeGen/R600/llvm.AMDGPU.legacy.rsq.ll index ac6e8fd4a5e..6e3fa25ff9e 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.legacy.rsq.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.legacy.rsq.ll @@ -4,7 +4,7 @@ declare float @llvm.AMDGPU.legacy.rsq(float) nounwind readnone ; FUNC-LABEL: {{^}}rsq_legacy_f32: -; SI: V_RSQ_LEGACY_F32_e32 +; SI: v_rsq_legacy_f32_e32 ; EG: RECIPSQRT_IEEE define void @rsq_legacy_f32(float addrspace(1)* %out, float %src) nounwind { %rsq = call float @llvm.AMDGPU.legacy.rsq(float %src) nounwind readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.rcp.f64.ll b/test/CodeGen/R600/llvm.AMDGPU.rcp.f64.ll index 85c902c0d4f..c4b04c5c745 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.rcp.f64.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.rcp.f64.ll @@ -4,7 +4,7 @@ declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone declare double @llvm.sqrt.f64(double) nounwind readnone ; FUNC-LABEL: {{^}}rcp_f64: -; SI: V_RCP_F64_e32 +; SI: v_rcp_f64_e32 define void @rcp_f64(double addrspace(1)* %out, double %src) nounwind { %rcp = call double @llvm.AMDGPU.rcp.f64(double %src) nounwind readnone store double %rcp, double addrspace(1)* %out, align 8 @@ -12,7 +12,7 @@ define void @rcp_f64(double addrspace(1)* %out, double %src) nounwind { } ; FUNC-LABEL: {{^}}rcp_pat_f64: -; SI: V_RCP_F64_e32 +; SI: v_rcp_f64_e32 define void @rcp_pat_f64(double addrspace(1)* %out, double %src) nounwind { %rcp = fdiv double 1.0, %src store double %rcp, double addrspace(1)* %out, align 8 @@ -20,8 +20,8 @@ define void @rcp_pat_f64(double addrspace(1)* %out, double %src) nounwind { } ; FUNC-LABEL: {{^}}rsq_rcp_pat_f64: -; SI-UNSAFE: V_RSQ_F64_e32 -; SI-SAFE-NOT: V_RSQ_F64_e32 +; SI-UNSAFE: v_rsq_f64_e32 +; SI-SAFE-NOT: v_rsq_f64_e32 define void @rsq_rcp_pat_f64(double addrspace(1)* %out, double %src) nounwind { %sqrt = call double @llvm.sqrt.f64(double %src) nounwind readnone %rcp = call double @llvm.AMDGPU.rcp.f64(double %sqrt) nounwind readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.rcp.ll b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll index dcfa07f8fa2..3ee3e6b3396 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.rcp.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll @@ -11,7 +11,7 @@ declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone declare float @llvm.sqrt.f32(float) nounwind readnone ; FUNC-LABEL: {{^}}rcp_f32: -; SI: V_RCP_F32_e32 +; SI: v_rcp_f32_e32 ; EG: RECIP_IEEE define void @rcp_f32(float addrspace(1)* %out, float %src) nounwind { %rcp = call float @llvm.AMDGPU.rcp.f32(float %src) nounwind readnone @@ -22,8 +22,8 @@ define void @rcp_f32(float addrspace(1)* %out, float %src) nounwind { ; FIXME: Evergreen only ever does unsafe fp math. ; FUNC-LABEL: {{^}}rcp_pat_f32: -; SI-SAFE: V_RCP_F32_e32 -; XSI-SAFE-SPDENORM-NOT: V_RCP_F32_e32 +; SI-SAFE: v_rcp_f32_e32 +; XSI-SAFE-SPDENORM-NOT: v_rcp_f32_e32 ; EG: RECIP_IEEE @@ -34,9 +34,9 @@ define void @rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind { } ; FUNC-LABEL: {{^}}rsq_rcp_pat_f32: -; SI-UNSAFE: V_RSQ_F32_e32 -; SI-SAFE: V_SQRT_F32_e32 -; SI-SAFE: V_RCP_F32_e32 +; SI-UNSAFE: v_rsq_f32_e32 +; SI-SAFE: v_sqrt_f32_e32 +; SI-SAFE: v_rcp_f32_e32 ; EG: RECIPSQRT_IEEE define void @rsq_rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind { diff --git a/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.f64.ll b/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.f64.ll index 7ca5e8a9077..18854be84b2 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.f64.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.f64.ll @@ -3,7 +3,7 @@ declare double @llvm.AMDGPU.rsq.clamped.f64(double) nounwind readnone ; FUNC-LABEL: {{^}}rsq_clamped_f64: -; SI: V_RSQ_CLAMP_F64_e32 +; SI: v_rsq_clamp_f64_e32 define void @rsq_clamped_f64(double addrspace(1)* %out, double %src) nounwind { %rsq_clamped = call double @llvm.AMDGPU.rsq.clamped.f64(double %src) nounwind readnone store double %rsq_clamped, double addrspace(1)* %out, align 8 diff --git a/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.ll b/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.ll index ace9653e44d..6bf9f0c5353 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.ll @@ -5,7 +5,7 @@ declare float @llvm.AMDGPU.rsq.clamped.f32(float) nounwind readnone ; FUNC-LABEL: {{^}}rsq_clamped_f32: -; SI: V_RSQ_CLAMP_F32_e32 +; SI: v_rsq_clamp_f32_e32 ; EG: RECIPSQRT_CLAMPED define void @rsq_clamped_f32(float addrspace(1)* %out, float %src) nounwind { %rsq_clamped = call float @llvm.AMDGPU.rsq.clamped.f32(float %src) nounwind readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.rsq.ll b/test/CodeGen/R600/llvm.AMDGPU.rsq.ll index 709d445ebe2..d6299b8bb14 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.rsq.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.rsq.ll @@ -4,7 +4,7 @@ declare float @llvm.AMDGPU.rsq.f32(float) nounwind readnone ; FUNC-LABEL: {{^}}rsq_f32: -; SI: V_RSQ_F32_e32 {{v[0-9]+}}, {{s[0-9]+}} +; SI: v_rsq_f32_e32 {{v[0-9]+}}, {{s[0-9]+}} ; EG: RECIPSQRT_IEEE define void @rsq_f32(float addrspace(1)* %out, float %src) nounwind { %rsq = call float @llvm.AMDGPU.rsq.f32(float %src) nounwind readnone @@ -14,7 +14,7 @@ define void @rsq_f32(float addrspace(1)* %out, float %src) nounwind { ; TODO: Really these should be constant folded ; FUNC-LABEL: {{^}}rsq_f32_constant_4.0 -; SI: V_RSQ_F32_e32 {{v[0-9]+}}, 4.0 +; SI: v_rsq_f32_e32 {{v[0-9]+}}, 4.0 ; EG: RECIPSQRT_IEEE define void @rsq_f32_constant_4.0(float addrspace(1)* %out) nounwind { %rsq = call float @llvm.AMDGPU.rsq.f32(float 4.0) nounwind readnone @@ -23,7 +23,7 @@ define void @rsq_f32_constant_4.0(float addrspace(1)* %out) nounwind { } ; FUNC-LABEL: {{^}}rsq_f32_constant_100.0 -; SI: V_RSQ_F32_e32 {{v[0-9]+}}, 0x42c80000 +; SI: v_rsq_f32_e32 {{v[0-9]+}}, 0x42c80000 ; EG: RECIPSQRT_IEEE define void @rsq_f32_constant_100.0(float addrspace(1)* %out) nounwind { %rsq = call float @llvm.AMDGPU.rsq.f32(float 100.0) nounwind readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.trig_preop.ll b/test/CodeGen/R600/llvm.AMDGPU.trig_preop.ll index 8eecd6eaef1..2e6bd5c0633 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.trig_preop.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.trig_preop.ll @@ -3,11 +3,11 @@ declare double @llvm.AMDGPU.trig.preop.f64(double, i32) nounwind readnone ; SI-LABEL: {{^}}test_trig_preop_f64: -; SI-DAG: BUFFER_LOAD_DWORD [[SEG:v[0-9]+]] -; SI-DAG: BUFFER_LOAD_DWORDX2 [[SRC:v\[[0-9]+:[0-9]+\]]], -; SI: V_TRIG_PREOP_F64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], [[SEG]] -; SI: BUFFER_STORE_DWORDX2 [[RESULT]], -; SI: S_ENDPGM +; SI-DAG: buffer_load_dword [[SEG:v[0-9]+]] +; SI-DAG: buffer_load_dwordx2 [[SRC:v\[[0-9]+:[0-9]+\]]], +; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], [[SEG]] +; SI: buffer_store_dwordx2 [[RESULT]], +; SI: s_endpgm define void @test_trig_preop_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind { %a = load double addrspace(1)* %aptr, align 8 %b = load i32 addrspace(1)* %bptr, align 4 @@ -17,10 +17,10 @@ define void @test_trig_preop_f64(double addrspace(1)* %out, double addrspace(1)* } ; SI-LABEL: {{^}}test_trig_preop_f64_imm_segment: -; SI: BUFFER_LOAD_DWORDX2 [[SRC:v\[[0-9]+:[0-9]+\]]], -; SI: V_TRIG_PREOP_F64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], 7 -; SI: BUFFER_STORE_DWORDX2 [[RESULT]], -; SI: S_ENDPGM +; SI: buffer_load_dwordx2 [[SRC:v\[[0-9]+:[0-9]+\]]], +; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], 7 +; SI: buffer_store_dwordx2 [[RESULT]], +; SI: s_endpgm define void @test_trig_preop_f64_imm_segment(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind { %a = load double addrspace(1)* %aptr, align 8 %result = call double @llvm.AMDGPU.trig.preop.f64(double %a, i32 7) nounwind readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll index 8f85a845ec1..fdd531d7913 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll @@ -4,7 +4,7 @@ ; R600-CHECK: {{^}}amdgpu_trunc: ; R600-CHECK: TRUNC T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI-CHECK: {{^}}amdgpu_trunc: -; SI-CHECK: V_TRUNC_F32 +; SI-CHECK: v_trunc_f32 define void @amdgpu_trunc(float addrspace(1)* %out, float %x) { entry: diff --git a/test/CodeGen/R600/llvm.AMDGPU.umad24.ll b/test/CodeGen/R600/llvm.AMDGPU.umad24.ll index 3331ba488f2..4de1f75db69 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.umad24.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.umad24.ll @@ -7,7 +7,7 @@ declare i32 @llvm.AMDGPU.umad24(i32, i32, i32) nounwind readnone ; FUNC-LABEL: {{^}}test_umad24: -; SI: V_MAD_U32_U24 +; SI: v_mad_u32_u24 ; EG: MULADD_UINT24 ; R600: MULLO_UINT ; R600: ADD_INT diff --git a/test/CodeGen/R600/llvm.AMDGPU.umax.ll b/test/CodeGen/R600/llvm.AMDGPU.umax.ll index 83c6b06ec70..ee854ec8c48 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.umax.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.umax.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s ; SI-LABEL: {{^}}vector_umax: -; SI: V_MAX_U32_e32 +; SI: v_max_u32_e32 define void @vector_umax(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 { main_body: %load = load i32 addrspace(1)* %in, align 4 @@ -12,7 +12,7 @@ main_body: } ; SI-LABEL: {{^}}scalar_umax: -; SI: S_MAX_U32 +; SI: s_max_u32 define void @scalar_umax(i32 %p0, i32 %p1) #0 { entry: %max = call i32 @llvm.AMDGPU.umax(i32 %p0, i32 %p1) @@ -22,10 +22,10 @@ entry: } ; SI-LABEL: {{^}}trunc_zext_umax: -; SI: BUFFER_LOAD_UBYTE [[VREG:v[0-9]+]], -; SI: V_MAX_U32_e32 [[RESULT:v[0-9]+]], 0, [[VREG]] -; SI-NOT: AND -; SI: BUFFER_STORE_SHORT [[RESULT]], +; SI: buffer_load_ubyte [[VREG:v[0-9]+]], +; SI: v_max_u32_e32 [[RESULT:v[0-9]+]], 0, [[VREG]] +; SI-NOT: and +; SI: buffer_store_short [[RESULT]], define void @trunc_zext_umax(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind { %tmp5 = load i8 addrspace(1)* %src, align 1 %tmp2 = zext i8 %tmp5 to i32 diff --git a/test/CodeGen/R600/llvm.AMDGPU.umin.ll b/test/CodeGen/R600/llvm.AMDGPU.umin.ll index 6b76a2a028e..2eaa3728ed3 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.umin.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.umin.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s ; SI-LABEL: {{^}}vector_umin: -; SI: V_MIN_U32_e32 +; SI: v_min_u32_e32 define void @vector_umin(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 { main_body: %load = load i32 addrspace(1)* %in, align 4 @@ -12,7 +12,7 @@ main_body: } ; SI-LABEL: {{^}}scalar_umin: -; SI: S_MIN_U32 +; SI: s_min_u32 define void @scalar_umin(i32 %p0, i32 %p1) #0 { entry: %min = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %p1) @@ -22,10 +22,10 @@ entry: } ; SI-LABEL: {{^}}trunc_zext_umin: -; SI: BUFFER_LOAD_UBYTE [[VREG:v[0-9]+]], -; SI: V_MIN_U32_e32 [[RESULT:v[0-9]+]], 0, [[VREG]] -; SI-NOT: AND -; SI: BUFFER_STORE_SHORT [[RESULT]], +; SI: buffer_load_ubyte [[VREG:v[0-9]+]], +; SI: v_min_u32_e32 [[RESULT:v[0-9]+]], 0, [[VREG]] +; SI-NOT: and +; SI: buffer_store_short [[RESULT]], define void @trunc_zext_umin(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind { %tmp5 = load i8 addrspace(1)* %src, align 1 %tmp2 = zext i8 %tmp5 to i32 diff --git a/test/CodeGen/R600/llvm.AMDGPU.umul24.ll b/test/CodeGen/R600/llvm.AMDGPU.umul24.ll index 18bc7033f2e..567ac31f364 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.umul24.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.umul24.ll @@ -7,7 +7,7 @@ declare i32 @llvm.AMDGPU.umul24(i32, i32) nounwind readnone ; FUNC-LABEL: {{^}}test_umul24: -; SI: V_MUL_U32_U24 +; SI: v_mul_u32_u24 ; R600: MUL_UINT24 ; R600: MULLO_UINT define void @test_umul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { diff --git a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll index 0438eccc886..d26bc322ec9 100644 --- a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll +++ b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll @@ -1,7 +1,7 @@ ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s -;CHECK: S_MOV_B32 -;CHECK-NEXT: V_INTERP_MOV_F32 +;CHECK: s_mov_b32 +;CHECK-NEXT: v_interp_mov_f32 define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" { main_body: diff --git a/test/CodeGen/R600/llvm.SI.gather4.ll b/test/CodeGen/R600/llvm.SI.gather4.ll index ad9789bd9b6..91a2012a95e 100644 --- a/test/CodeGen/R600/llvm.SI.gather4.ll +++ b/test/CodeGen/R600/llvm.SI.gather4.ll @@ -1,7 +1,7 @@ ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK-LABEL: {{^}}gather4_v2: -;CHECK: IMAGE_GATHER4 {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_v2() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -14,7 +14,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4: -;CHECK: IMAGE_GATHER4 {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -27,7 +27,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_cl: -;CHECK: IMAGE_GATHER4_CL {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -40,7 +40,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_l: -;CHECK: IMAGE_GATHER4_L {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_l() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -53,7 +53,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_b: -;CHECK: IMAGE_GATHER4_B {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_b() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -66,7 +66,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_b_cl: -;CHECK: IMAGE_GATHER4_B_CL {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_b_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -79,7 +79,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_b_cl_v8: -;CHECK: IMAGE_GATHER4_B_CL {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_b_cl_v8() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -92,7 +92,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_lz_v2: -;CHECK: IMAGE_GATHER4_LZ {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_lz_v2() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -105,7 +105,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_lz: -;CHECK: IMAGE_GATHER4_LZ {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_lz() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -120,7 +120,7 @@ main_body: ;CHECK-LABEL: {{^}}gather4_o: -;CHECK: IMAGE_GATHER4_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_o() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -133,7 +133,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_cl_o: -;CHECK: IMAGE_GATHER4_CL_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_cl_o() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -146,7 +146,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_cl_o_v8: -;CHECK: IMAGE_GATHER4_CL_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_cl_o_v8() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -159,7 +159,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_l_o: -;CHECK: IMAGE_GATHER4_L_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_l_o() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -172,7 +172,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_l_o_v8: -;CHECK: IMAGE_GATHER4_L_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_l_o_v8() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -185,7 +185,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_b_o: -;CHECK: IMAGE_GATHER4_B_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_b_o() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -198,7 +198,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_b_o_v8: -;CHECK: IMAGE_GATHER4_B_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_b_o_v8() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -211,7 +211,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_b_cl_o: -;CHECK: IMAGE_GATHER4_B_CL_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_b_cl_o() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -224,7 +224,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_lz_o: -;CHECK: IMAGE_GATHER4_LZ_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_lz_o() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.lz.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -239,7 +239,7 @@ main_body: ;CHECK-LABEL: {{^}}gather4_c: -;CHECK: IMAGE_GATHER4_C {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -252,7 +252,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_cl: -;CHECK: IMAGE_GATHER4_C_CL {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -265,7 +265,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_cl_v8: -;CHECK: IMAGE_GATHER4_C_CL {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c_cl_v8() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -278,7 +278,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_l: -;CHECK: IMAGE_GATHER4_C_L {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c_l() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.l.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -291,7 +291,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_l_v8: -;CHECK: IMAGE_GATHER4_C_L {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c_l_v8() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -304,7 +304,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_b: -;CHECK: IMAGE_GATHER4_C_B {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c_b() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.b.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -317,7 +317,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_b_v8: -;CHECK: IMAGE_GATHER4_C_B {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c_b_v8() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -330,7 +330,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_b_cl: -;CHECK: IMAGE_GATHER4_C_B_CL {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c_b_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -343,7 +343,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_lz: -;CHECK: IMAGE_GATHER4_C_LZ {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c_lz() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.lz.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -358,7 +358,7 @@ main_body: ;CHECK-LABEL: {{^}}gather4_c_o: -;CHECK: IMAGE_GATHER4_C_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c_o() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -371,7 +371,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_o_v8: -;CHECK: IMAGE_GATHER4_C_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c_o_v8() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -384,7 +384,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_cl_o: -;CHECK: IMAGE_GATHER4_C_CL_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c_cl_o() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -397,7 +397,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_l_o: -;CHECK: IMAGE_GATHER4_C_L_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c_l_o() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.l.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -410,7 +410,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_b_o: -;CHECK: IMAGE_GATHER4_C_B_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c_b_o() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.b.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -423,7 +423,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_b_cl_o: -;CHECK: IMAGE_GATHER4_C_B_CL_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c_b_cl_o() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.b.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -436,7 +436,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_lz_o: -;CHECK: IMAGE_GATHER4_C_LZ_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c_lz_o() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.lz.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -449,7 +449,7 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_lz_o_v8: -;CHECK: IMAGE_GATHER4_C_LZ_O {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @gather4_c_lz_o_v8() #0 { main_body: %r = call <4 x float> @llvm.SI.gather4.c.lz.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) diff --git a/test/CodeGen/R600/llvm.SI.getlod.ll b/test/CodeGen/R600/llvm.SI.getlod.ll index 225a72428ee..ec26fe5d680 100644 --- a/test/CodeGen/R600/llvm.SI.getlod.ll +++ b/test/CodeGen/R600/llvm.SI.getlod.ll @@ -1,7 +1,7 @@ ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK-LABEL: {{^}}getlod: -;CHECK: IMAGE_GET_LOD {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @getlod() #0 { main_body: %r = call <4 x float> @llvm.SI.getlod.i32(i32 undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -12,7 +12,7 @@ main_body: } ;CHECK-LABEL: {{^}}getlod_v2: -;CHECK: IMAGE_GET_LOD {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @getlod_v2() #0 { main_body: %r = call <4 x float> @llvm.SI.getlod.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) @@ -23,7 +23,7 @@ main_body: } ;CHECK-LABEL: {{^}}getlod_v4: -;CHECK: IMAGE_GET_LOD {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @getlod_v4() #0 { main_body: %r = call <4 x float> @llvm.SI.getlod.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) diff --git a/test/CodeGen/R600/llvm.SI.image.ll b/test/CodeGen/R600/llvm.SI.image.ll index d8fc748a810..4eec5432b3f 100644 --- a/test/CodeGen/R600/llvm.SI.image.ll +++ b/test/CodeGen/R600/llvm.SI.image.ll @@ -1,7 +1,7 @@ ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK-LABEL: {{^}}image_load: -;CHECK: IMAGE_LOAD {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_load {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @image_load() #0 { main_body: %r = call <4 x float> @llvm.SI.image.load.v4i32(<4 x i32> undef, <8 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -14,7 +14,7 @@ main_body: } ;CHECK-LABEL: {{^}}image_load_mip: -;CHECK: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @image_load_mip() #0 { main_body: %r = call <4 x float> @llvm.SI.image.load.mip.v4i32(<4 x i32> undef, <8 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -27,7 +27,7 @@ main_body: } ;CHECK-LABEL: {{^}}getresinfo: -;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} define void @getresinfo() #0 { main_body: %r = call <4 x float> @llvm.SI.getresinfo.i32(i32 undef, <8 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) diff --git a/test/CodeGen/R600/llvm.SI.image.sample.ll b/test/CodeGen/R600/llvm.SI.image.sample.ll index 934bf425f48..ebff3914183 100644 --- a/test/CodeGen/R600/llvm.SI.image.sample.ll +++ b/test/CodeGen/R600/llvm.SI.image.sample.ll @@ -1,7 +1,7 @@ ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK-LABEL: {{^}}sample: -;CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -14,7 +14,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_cl: -;CHECK: IMAGE_SAMPLE_CL {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -27,7 +27,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_d: -;CHECK: IMAGE_SAMPLE_D {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_d() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.d.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -40,7 +40,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_d_cl: -;CHECK: IMAGE_SAMPLE_D_CL {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_d_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_d_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.d.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -53,7 +53,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_l: -;CHECK: IMAGE_SAMPLE_L {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_l {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_l() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -66,7 +66,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_b: -;CHECK: IMAGE_SAMPLE_B {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_b {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_b() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -79,7 +79,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_b_cl: -;CHECK: IMAGE_SAMPLE_B_CL {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_b_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_b_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.b.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -92,7 +92,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_lz: -;CHECK: IMAGE_SAMPLE_LZ {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_lz {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_lz() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -105,7 +105,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_cd: -;CHECK: IMAGE_SAMPLE_CD {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_cd {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_cd() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.cd.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -118,7 +118,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_cd_cl: -;CHECK: IMAGE_SAMPLE_CD_CL {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_cd_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_cd_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.cd.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -131,7 +131,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c: -;CHECK: IMAGE_SAMPLE_C {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -144,7 +144,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_cl: -;CHECK: IMAGE_SAMPLE_C_CL {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -157,7 +157,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_d: -;CHECK: IMAGE_SAMPLE_C_D {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_d() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.d.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -170,7 +170,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_d_cl: -;CHECK: IMAGE_SAMPLE_C_D_CL {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_d_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_d_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.d.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -183,7 +183,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_l: -;CHECK: IMAGE_SAMPLE_C_L {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_l {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_l() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -196,7 +196,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_b: -;CHECK: IMAGE_SAMPLE_C_B {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_b {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_b() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -209,7 +209,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_b_cl: -;CHECK: IMAGE_SAMPLE_C_B_CL {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_b_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.b.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -222,7 +222,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_lz: -;CHECK: IMAGE_SAMPLE_C_LZ {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_lz {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_lz() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -235,7 +235,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_cd: -;CHECK: IMAGE_SAMPLE_C_CD {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_cd {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_cd() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.cd.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -248,7 +248,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_cd_cl: -;CHECK: IMAGE_SAMPLE_C_CD_CL {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_cd_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_cd_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.cd.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) diff --git a/test/CodeGen/R600/llvm.SI.image.sample.o.ll b/test/CodeGen/R600/llvm.SI.image.sample.o.ll index 71c2107e36f..dbc1b2bbddb 100644 --- a/test/CodeGen/R600/llvm.SI.image.sample.o.ll +++ b/test/CodeGen/R600/llvm.SI.image.sample.o.ll @@ -1,7 +1,7 @@ ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK-LABEL: {{^}}sample: -;CHECK: IMAGE_SAMPLE_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -14,7 +14,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_cl: -;CHECK: IMAGE_SAMPLE_CL_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -27,7 +27,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_d: -;CHECK: IMAGE_SAMPLE_D_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_d_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_d() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.d.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -40,7 +40,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_d_cl: -;CHECK: IMAGE_SAMPLE_D_CL_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_d_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.d.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -53,7 +53,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_l: -;CHECK: IMAGE_SAMPLE_L_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_l_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_l() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.l.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -66,7 +66,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_b: -;CHECK: IMAGE_SAMPLE_B_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_b_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_b() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.b.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -79,7 +79,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_b_cl: -;CHECK: IMAGE_SAMPLE_B_CL_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_b_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.b.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -92,7 +92,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_lz: -;CHECK: IMAGE_SAMPLE_LZ_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_lz_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_lz() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -105,7 +105,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_cd: -;CHECK: IMAGE_SAMPLE_CD_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_cd_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_cd() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.cd.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -118,7 +118,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_cd_cl: -;CHECK: IMAGE_SAMPLE_CD_CL_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_cd_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.cd.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -131,7 +131,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c: -;CHECK: IMAGE_SAMPLE_C_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -144,7 +144,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_cl: -;CHECK: IMAGE_SAMPLE_C_CL_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -157,7 +157,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_d: -;CHECK: IMAGE_SAMPLE_C_D_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_d_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_d() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.d.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -170,7 +170,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_d_cl: -;CHECK: IMAGE_SAMPLE_C_D_CL_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_d_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.d.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -183,7 +183,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_l: -;CHECK: IMAGE_SAMPLE_C_L_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_l_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_l() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.l.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -196,7 +196,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_b: -;CHECK: IMAGE_SAMPLE_C_B_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_b_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_b() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.b.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -209,7 +209,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_b_cl: -;CHECK: IMAGE_SAMPLE_C_B_CL_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_b_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.b.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -222,7 +222,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_lz: -;CHECK: IMAGE_SAMPLE_C_LZ_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_lz() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -235,7 +235,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_cd: -;CHECK: IMAGE_SAMPLE_C_CD_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_cd_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_cd() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.cd.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) @@ -248,7 +248,7 @@ main_body: } ;CHECK-LABEL: {{^}}sample_c_cd_cl: -;CHECK: IMAGE_SAMPLE_C_CD_CL_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +;CHECK: image_sample_c_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} define void @sample_c_cd_cl() #0 { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.cd.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) diff --git a/test/CodeGen/R600/llvm.SI.imageload.ll b/test/CodeGen/R600/llvm.SI.imageload.ll index 59e00f01c96..673d92db5fb 100644 --- a/test/CodeGen/R600/llvm.SI.imageload.ll +++ b/test/CodeGen/R600/llvm.SI.imageload.ll @@ -1,15 +1,15 @@ ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s -;CHECK-DAG: IMAGE_LOAD {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, -1 -;CHECK-DAG: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, 0 -;CHECK-DAG: IMAGE_LOAD_MIP {{v[0-9]+}}, 2, 0, 0, 0 -;CHECK-DAG: IMAGE_LOAD_MIP {{v[0-9]+}}, 1, 0, 0, 0 -;CHECK-DAG: IMAGE_LOAD_MIP {{v[0-9]+}}, 4, 0, 0, 0 -;CHECK-DAG: IMAGE_LOAD_MIP {{v[0-9]+}}, 8, 0, 0, 0 -;CHECK-DAG: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 5, 0, 0, 0 -;CHECK-DAG: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 12, 0, 0, -1 -;CHECK-DAG: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 7, 0, 0, 0 -;CHECK-DAG: IMAGE_LOAD_MIP {{v[0-9]+}}, 8, 0, 0, -1 +;CHECK-DAG: image_load {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, -1 +;CHECK-DAG: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, 0 +;CHECK-DAG: image_load_mip {{v[0-9]+}}, 2, 0, 0, 0 +;CHECK-DAG: image_load_mip {{v[0-9]+}}, 1, 0, 0, 0 +;CHECK-DAG: image_load_mip {{v[0-9]+}}, 4, 0, 0, 0 +;CHECK-DAG: image_load_mip {{v[0-9]+}}, 8, 0, 0, 0 +;CHECK-DAG: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, 5, 0, 0, 0 +;CHECK-DAG: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, 12, 0, 0, -1 +;CHECK-DAG: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, 7, 0, 0, 0 +;CHECK-DAG: image_load_mip {{v[0-9]+}}, 8, 0, 0, -1 define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { %v1 = insertelement <4 x i32> undef, i32 %a1, i32 0 @@ -84,7 +84,7 @@ define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { ; Test that ccordinates are stored in vgprs and not sgprs ; CHECK: vgpr_coords -; CHECK: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}} +; CHECK: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}} define void @vgpr_coords(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0 diff --git a/test/CodeGen/R600/llvm.SI.load.dword.ll b/test/CodeGen/R600/llvm.SI.load.dword.ll index 524040046af..e5c6201f9b2 100644 --- a/test/CodeGen/R600/llvm.SI.load.dword.ll +++ b/test/CodeGen/R600/llvm.SI.load.dword.ll @@ -4,10 +4,10 @@ ; ESGS ring buffer ; CHECK-LABEL: {{^}}main: -; CHECK: BUFFER_LOAD_DWORD -; CHECK: BUFFER_LOAD_DWORD -; CHECK: BUFFER_LOAD_DWORD -; CHECK: BUFFER_LOAD_DWORD +; CHECK: buffer_load_dword +; CHECK: buffer_load_dword +; CHECK: buffer_load_dword +; CHECK: buffer_load_dword define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32, i32, i32, i32) #0 { main_body: diff --git a/test/CodeGen/R600/llvm.SI.resinfo.ll b/test/CodeGen/R600/llvm.SI.resinfo.ll index a48510a96a6..d8f3722013c 100644 --- a/test/CodeGen/R600/llvm.SI.resinfo.ll +++ b/test/CodeGen/R600/llvm.SI.resinfo.ll @@ -1,21 +1,21 @@ ; RUN: llc -march=r600 -mcpu=verde -verify-machineinstrs < %s | FileCheck %s -; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, -1 -; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, 0 -; CHECK-DAG: IMAGE_GET_RESINFO {{v[0-9]+}}, 2, 0, 0, 0 -; CHECK-DAG: IMAGE_GET_RESINFO {{v[0-9]+}}, 1, 0, 0, 0 -; CHECK-DAG: IMAGE_GET_RESINFO {{v[0-9]+}}, 4, 0, 0, 0 -; CHECK-DAG: IMAGE_GET_RESINFO {{v[0-9]+}}, 8, 0, 0, 0 -; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 5, 0, 0, 0 -; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 9, 0, 0, 0 -; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 6, 0, 0, 0 -; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 10, 0, 0, -1 -; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 12, 0, 0, -1 -; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 7, 0, 0, 0 -; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 11, 0, 0, 0 -; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 13, 0, 0, 0 -; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 14, 0, 0, 0 -; CHECK-DAG: IMAGE_GET_RESINFO {{v[0-9]+}}, 8, 0, 0, -1 +; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, -1 +; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, 0 +; CHECK-DAG: image_get_resinfo {{v[0-9]+}}, 2, 0, 0, 0 +; CHECK-DAG: image_get_resinfo {{v[0-9]+}}, 1, 0, 0, 0 +; CHECK-DAG: image_get_resinfo {{v[0-9]+}}, 4, 0, 0, 0 +; CHECK-DAG: image_get_resinfo {{v[0-9]+}}, 8, 0, 0, 0 +; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 5, 0, 0, 0 +; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 9, 0, 0, 0 +; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 6, 0, 0, 0 +; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 10, 0, 0, -1 +; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 12, 0, 0, -1 +; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 7, 0, 0, 0 +; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 11, 0, 0, 0 +; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 13, 0, 0, 0 +; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 14, 0, 0, 0 +; CHECK-DAG: image_get_resinfo {{v[0-9]+}}, 8, 0, 0, -1 define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, i32 %a10, i32 %a11, i32 %a12, i32 %a13, i32 %a14, i32 %a15, i32 %a16) { diff --git a/test/CodeGen/R600/llvm.SI.sample-masked.ll b/test/CodeGen/R600/llvm.SI.sample-masked.ll index 2c511447277..9e86bec9d76 100644 --- a/test/CodeGen/R600/llvm.SI.sample-masked.ll +++ b/test/CodeGen/R600/llvm.SI.sample-masked.ll @@ -1,7 +1,7 @@ ;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ; CHECK-LABEL: {{^}}v1: -; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 13 +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 13 define void @v1(i32 %a1) #0 { entry: %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 @@ -14,7 +14,7 @@ entry: } ; CHECK-LABEL: {{^}}v2: -; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 11 +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 11 define void @v2(i32 %a1) #0 { entry: %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 @@ -27,7 +27,7 @@ entry: } ; CHECK-LABEL: {{^}}v3: -; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 14 +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 14 define void @v3(i32 %a1) #0 { entry: %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 @@ -40,7 +40,7 @@ entry: } ; CHECK-LABEL: {{^}}v4: -; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 7 +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 7 define void @v4(i32 %a1) #0 { entry: %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 @@ -53,7 +53,7 @@ entry: } ; CHECK-LABEL: {{^}}v5: -; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 10 +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 10 define void @v5(i32 %a1) #0 { entry: %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 @@ -65,7 +65,7 @@ entry: } ; CHECK-LABEL: {{^}}v6: -; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 6 +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 6 define void @v6(i32 %a1) #0 { entry: %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 @@ -77,7 +77,7 @@ entry: } ; CHECK-LABEL: {{^}}v7: -; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 9 +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 9 define void @v7(i32 %a1) #0 { entry: %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 diff --git a/test/CodeGen/R600/llvm.SI.sample.ll b/test/CodeGen/R600/llvm.SI.sample.ll index 951e9ea85bc..a1d2c022a22 100644 --- a/test/CodeGen/R600/llvm.SI.sample.ll +++ b/test/CodeGen/R600/llvm.SI.sample.ll @@ -1,21 +1,21 @@ ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s -;CHECK-DAG: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 15 -;CHECK-DAG: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 3 -;CHECK-DAG: IMAGE_SAMPLE {{v[0-9]+}}, 2 -;CHECK-DAG: IMAGE_SAMPLE {{v[0-9]+}}, 1 -;CHECK-DAG: IMAGE_SAMPLE {{v[0-9]+}}, 4 -;CHECK-DAG: IMAGE_SAMPLE {{v[0-9]+}}, 8 -;CHECK-DAG: IMAGE_SAMPLE_C {{v\[[0-9]+:[0-9]+\]}}, 5 -;CHECK-DAG: IMAGE_SAMPLE_C {{v\[[0-9]+:[0-9]+\]}}, 9 -;CHECK-DAG: IMAGE_SAMPLE_C {{v\[[0-9]+:[0-9]+\]}}, 6 -;CHECK-DAG: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 10 -;CHECK-DAG: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 12 -;CHECK-DAG: IMAGE_SAMPLE_C {{v\[[0-9]+:[0-9]+\]}}, 7 -;CHECK-DAG: IMAGE_SAMPLE_C {{v\[[0-9]+:[0-9]+\]}}, 11 -;CHECK-DAG: IMAGE_SAMPLE_C {{v\[[0-9]+:[0-9]+\]}}, 13 -;CHECK-DAG: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 14 -;CHECK-DAG: IMAGE_SAMPLE {{v[0-9]+}}, 8 +;CHECK-DAG: image_sample {{v\[[0-9]+:[0-9]+\]}}, 15 +;CHECK-DAG: image_sample {{v\[[0-9]+:[0-9]+\]}}, 3 +;CHECK-DAG: image_sample {{v[0-9]+}}, 2 +;CHECK-DAG: image_sample {{v[0-9]+}}, 1 +;CHECK-DAG: image_sample {{v[0-9]+}}, 4 +;CHECK-DAG: image_sample {{v[0-9]+}}, 8 +;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 5 +;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 9 +;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 6 +;CHECK-DAG: image_sample {{v\[[0-9]+:[0-9]+\]}}, 10 +;CHECK-DAG: image_sample {{v\[[0-9]+:[0-9]+\]}}, 12 +;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 7 +;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 11 +;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 13 +;CHECK-DAG: image_sample {{v\[[0-9]+:[0-9]+\]}}, 14 +;CHECK-DAG: image_sample {{v[0-9]+}}, 8 define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) #0 { %v1 = insertelement <4 x i32> undef, i32 %a1, i32 0 @@ -136,7 +136,7 @@ define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) #0 { } ; CHECK: {{^}}v1: -; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 15 +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 15 define void @v1(i32 %a1) #0 { entry: %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 diff --git a/test/CodeGen/R600/llvm.SI.sampled.ll b/test/CodeGen/R600/llvm.SI.sampled.ll index 366456f44e6..91b71f3e609 100644 --- a/test/CodeGen/R600/llvm.SI.sampled.ll +++ b/test/CodeGen/R600/llvm.SI.sampled.ll @@ -1,21 +1,21 @@ ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s -;CHECK-DAG: IMAGE_SAMPLE_D {{v\[[0-9]+:[0-9]+\]}}, 15 -;CHECK-DAG: IMAGE_SAMPLE_D {{v\[[0-9]+:[0-9]+\]}}, 3 -;CHECK-DAG: IMAGE_SAMPLE_D {{v[0-9]+}}, 2 -;CHECK-DAG: IMAGE_SAMPLE_D {{v[0-9]+}}, 1 -;CHECK-DAG: IMAGE_SAMPLE_D {{v[0-9]+}}, 4 -;CHECK-DAG: IMAGE_SAMPLE_D {{v[0-9]+}}, 8 -;CHECK-DAG: IMAGE_SAMPLE_C_D {{v\[[0-9]+:[0-9]+\]}}, 5 -;CHECK-DAG: IMAGE_SAMPLE_C_D {{v\[[0-9]+:[0-9]+\]}}, 9 -;CHECK-DAG: IMAGE_SAMPLE_C_D {{v\[[0-9]+:[0-9]+\]}}, 6 -;CHECK-DAG: IMAGE_SAMPLE_D {{v\[[0-9]+:[0-9]+\]}}, 10 -;CHECK-DAG: IMAGE_SAMPLE_D {{v\[[0-9]+:[0-9]+\]}}, 12 -;CHECK-DAG: IMAGE_SAMPLE_C_D {{v\[[0-9]+:[0-9]+\]}}, 7 -;CHECK-DAG: IMAGE_SAMPLE_C_D {{v\[[0-9]+:[0-9]+\]}}, 11 -;CHECK-DAG: IMAGE_SAMPLE_C_D {{v\[[0-9]+:[0-9]+\]}}, 13 -;CHECK-DAG: IMAGE_SAMPLE_D {{v\[[0-9]+:[0-9]+\]}}, 14 -;CHECK-DAG: IMAGE_SAMPLE_D {{v[0-9]+}}, 8 +;CHECK-DAG: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, 15 +;CHECK-DAG: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, 3 +;CHECK-DAG: image_sample_d {{v[0-9]+}}, 2 +;CHECK-DAG: image_sample_d {{v[0-9]+}}, 1 +;CHECK-DAG: image_sample_d {{v[0-9]+}}, 4 +;CHECK-DAG: image_sample_d {{v[0-9]+}}, 8 +;CHECK-DAG: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 5 +;CHECK-DAG: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 9 +;CHECK-DAG: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 6 +;CHECK-DAG: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, 10 +;CHECK-DAG: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, 12 +;CHECK-DAG: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 7 +;CHECK-DAG: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 11 +;CHECK-DAG: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 13 +;CHECK-DAG: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, 14 +;CHECK-DAG: image_sample_d {{v[0-9]+}}, 8 define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) #0 { %v1 = insertelement <4 x i32> undef, i32 %a1, i32 0 diff --git a/test/CodeGen/R600/llvm.SI.sendmsg.ll b/test/CodeGen/R600/llvm.SI.sendmsg.ll index 9763f882665..042fc5b8efe 100644 --- a/test/CodeGen/R600/llvm.SI.sendmsg.ll +++ b/test/CodeGen/R600/llvm.SI.sendmsg.ll @@ -1,10 +1,10 @@ ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ; CHECK-LABEL: {{^}}main: -; CHECK: S_SENDMSG Gs(emit stream 0) -; CHECK: S_SENDMSG Gs(cut stream 1) -; CHECK: S_SENDMSG Gs(emit-cut stream 2) -; CHECK: S_SENDMSG Gs_done(nop) +; CHECK: s_sendmsg Gs(emit stream 0) +; CHECK: s_sendmsg Gs(cut stream 1) +; CHECK: s_sendmsg Gs(emit-cut stream 2) +; CHECK: s_sendmsg Gs_done(nop) define void @main() { main_body: diff --git a/test/CodeGen/R600/llvm.SI.tbuffer.store.ll b/test/CodeGen/R600/llvm.SI.tbuffer.store.ll index 44472790b37..702daeafe8c 100644 --- a/test/CodeGen/R600/llvm.SI.tbuffer.store.ll +++ b/test/CodeGen/R600/llvm.SI.tbuffer.store.ll @@ -1,7 +1,7 @@ ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK-LABEL: {{^}}test1: -;CHECK: TBUFFER_STORE_FORMAT_XYZW {{v\[[0-9]+:[0-9]+\]}}, 0x20, -1, 0, -1, 0, 14, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 +;CHECK: tbuffer_store_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, 0x20, -1, 0, -1, 0, 14, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 define void @test1(i32 %a1, i32 %vaddr) #0 { %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0 call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata, @@ -11,7 +11,7 @@ define void @test1(i32 %a1, i32 %vaddr) #0 { } ;CHECK-LABEL: {{^}}test2: -;CHECK: TBUFFER_STORE_FORMAT_XYZ {{v\[[0-9]+:[0-9]+\]}}, 0x18, -1, 0, -1, 0, 13, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 +;CHECK: tbuffer_store_format_xyz {{v\[[0-9]+:[0-9]+\]}}, 0x18, -1, 0, -1, 0, 13, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 define void @test2(i32 %a1, i32 %vaddr) #0 { %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0 call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata, @@ -21,7 +21,7 @@ define void @test2(i32 %a1, i32 %vaddr) #0 { } ;CHECK-LABEL: {{^}}test3: -;CHECK: TBUFFER_STORE_FORMAT_XY {{v\[[0-9]+:[0-9]+\]}}, 0x10, -1, 0, -1, 0, 11, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 +;CHECK: tbuffer_store_format_xy {{v\[[0-9]+:[0-9]+\]}}, 0x10, -1, 0, -1, 0, 11, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 define void @test3(i32 %a1, i32 %vaddr) #0 { %vdata = insertelement <2 x i32> undef, i32 %a1, i32 0 call void @llvm.SI.tbuffer.store.v2i32(<16 x i8> undef, <2 x i32> %vdata, @@ -31,7 +31,7 @@ define void @test3(i32 %a1, i32 %vaddr) #0 { } ;CHECK-LABEL: {{^}}test4: -;CHECK: TBUFFER_STORE_FORMAT_X {{v[0-9]+}}, 0x8, -1, 0, -1, 0, 4, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 +;CHECK: tbuffer_store_format_x {{v[0-9]+}}, 0x8, -1, 0, -1, 0, 4, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 define void @test4(i32 %vdata, i32 %vaddr) #0 { call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 %vdata, i32 1, i32 %vaddr, i32 0, i32 8, i32 4, i32 4, i32 1, i32 0, i32 1, diff --git a/test/CodeGen/R600/llvm.SI.tid.ll b/test/CodeGen/R600/llvm.SI.tid.ll index fe17304732a..ee96124f81a 100644 --- a/test/CodeGen/R600/llvm.SI.tid.ll +++ b/test/CodeGen/R600/llvm.SI.tid.ll @@ -1,7 +1,7 @@ ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s -;CHECK: V_MBCNT_LO_U32_B32_e64 -;CHECK: V_MBCNT_HI_U32_B32_e32 +;CHECK: v_mbcnt_lo_u32_b32_e64 +;CHECK: v_mbcnt_hi_u32_b32_e32 define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" { main_body: diff --git a/test/CodeGen/R600/llvm.amdgpu.kilp.ll b/test/CodeGen/R600/llvm.amdgpu.kilp.ll index d2e2b6870df..08bee382cd6 100644 --- a/test/CodeGen/R600/llvm.amdgpu.kilp.ll +++ b/test/CodeGen/R600/llvm.amdgpu.kilp.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=r600 -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; SI-LABEL: {{^}}kilp_gs_const: -; SI: S_MOV_B64 exec, 0 +; SI: s_mov_b64 exec, 0 define void @kilp_gs_const() #0 { main_body: %0 = icmp ule i32 0, 3 diff --git a/test/CodeGen/R600/llvm.amdgpu.lrp.ll b/test/CodeGen/R600/llvm.amdgpu.lrp.ll index b360baca3c9..ee922fe9f08 100644 --- a/test/CodeGen/R600/llvm.amdgpu.lrp.ll +++ b/test/CodeGen/R600/llvm.amdgpu.lrp.ll @@ -3,8 +3,8 @@ declare float @llvm.AMDGPU.lrp(float, float, float) nounwind readnone ; FUNC-LABEL: {{^}}test_lrp: -; SI: V_SUB_F32 -; SI: V_MAD_F32 +; SI: v_sub_f32 +; SI: v_mad_f32 define void @test_lrp(float addrspace(1)* %out, float %src0, float %src1, float %src2) nounwind { %mad = call float @llvm.AMDGPU.lrp(float %src0, float %src1, float %src2) nounwind readnone store float %mad, float addrspace(1)* %out, align 4 diff --git a/test/CodeGen/R600/llvm.cos.ll b/test/CodeGen/R600/llvm.cos.ll index 9e7a4deda69..837340f6ebe 100644 --- a/test/CodeGen/R600/llvm.cos.ll +++ b/test/CodeGen/R600/llvm.cos.ll @@ -7,8 +7,8 @@ ;EG: ADD * ;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ;EG-NOT: COS -;SI: V_COS_F32 -;SI-NOT: V_COS_F32 +;SI: v_cos_f32 +;SI-NOT: v_cos_f32 define void @test(float addrspace(1)* %out, float %x) #1 { %cos = call float @llvm.cos.f32(float %x) @@ -22,11 +22,11 @@ define void @test(float addrspace(1)* %out, float %x) #1 { ;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ;EG-NOT: COS -;SI: V_COS_F32 -;SI: V_COS_F32 -;SI: V_COS_F32 -;SI: V_COS_F32 -;SI-NOT: V_COS_F32 +;SI: v_cos_f32 +;SI: v_cos_f32 +;SI: v_cos_f32 +;SI: v_cos_f32 +;SI-NOT: v_cos_f32 define void @testv(<4 x float> addrspace(1)* %out, <4 x float> inreg %vx) #1 { %cos = call <4 x float> @llvm.cos.v4f32(<4 x float> %vx) diff --git a/test/CodeGen/R600/llvm.exp2.ll b/test/CodeGen/R600/llvm.exp2.ll index db8419eb269..52dc67d0a66 100644 --- a/test/CodeGen/R600/llvm.exp2.ll +++ b/test/CodeGen/R600/llvm.exp2.ll @@ -8,7 +8,7 @@ ;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) ;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) ;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} -;SI-CHECK: V_EXP_F32 +;SI-CHECK: v_exp_f32 define void @test(float addrspace(1)* %out, float %in) { entry: @@ -30,8 +30,8 @@ entry: ;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) ;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} ;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} -;SI-CHECK: V_EXP_F32 -;SI-CHECK: V_EXP_F32 +;SI-CHECK: v_exp_f32 +;SI-CHECK: v_exp_f32 define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) { entry: @@ -63,10 +63,10 @@ entry: ;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} ;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} ;CM-CHECK-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} -;SI-CHECK: V_EXP_F32 -;SI-CHECK: V_EXP_F32 -;SI-CHECK: V_EXP_F32 -;SI-CHECK: V_EXP_F32 +;SI-CHECK: v_exp_f32 +;SI-CHECK: v_exp_f32 +;SI-CHECK: v_exp_f32 +;SI-CHECK: v_exp_f32 define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) { entry: %0 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %in) diff --git a/test/CodeGen/R600/llvm.floor.ll b/test/CodeGen/R600/llvm.floor.ll index fd5682c7e04..0c7a15b0e97 100644 --- a/test/CodeGen/R600/llvm.floor.ll +++ b/test/CodeGen/R600/llvm.floor.ll @@ -4,7 +4,7 @@ ; R600-CHECK: {{^}}f32: ; R600-CHECK: FLOOR ; SI-CHECK: {{^}}f32: -; SI-CHECK: V_FLOOR_F32_e32 +; SI-CHECK: v_floor_f32_e32 define void @f32(float addrspace(1)* %out, float %in) { entry: %0 = call float @llvm.floor.f32(float %in) @@ -16,8 +16,8 @@ entry: ; R600-CHECK: FLOOR ; R600-CHECK: FLOOR ; SI-CHECK: {{^}}v2f32: -; SI-CHECK: V_FLOOR_F32_e32 -; SI-CHECK: V_FLOOR_F32_e32 +; SI-CHECK: v_floor_f32_e32 +; SI-CHECK: v_floor_f32_e32 define void @v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { entry: %0 = call <2 x float> @llvm.floor.v2f32(<2 x float> %in) @@ -31,10 +31,10 @@ entry: ; R600-CHECK: FLOOR ; R600-CHECK: FLOOR ; SI-CHECK: {{^}}v4f32: -; SI-CHECK: V_FLOOR_F32_e32 -; SI-CHECK: V_FLOOR_F32_e32 -; SI-CHECK: V_FLOOR_F32_e32 -; SI-CHECK: V_FLOOR_F32_e32 +; SI-CHECK: v_floor_f32_e32 +; SI-CHECK: v_floor_f32_e32 +; SI-CHECK: v_floor_f32_e32 +; SI-CHECK: v_floor_f32_e32 define void @v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { entry: %0 = call <4 x float> @llvm.floor.v4f32(<4 x float> %in) diff --git a/test/CodeGen/R600/llvm.log2.ll b/test/CodeGen/R600/llvm.log2.ll index 954a70edb3e..0b54a46cee7 100644 --- a/test/CodeGen/R600/llvm.log2.ll +++ b/test/CodeGen/R600/llvm.log2.ll @@ -8,7 +8,7 @@ ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} -;SI-CHECK: V_LOG_F32 +;SI-CHECK: v_log_f32 define void @test(float addrspace(1)* %out, float %in) { entry: @@ -30,8 +30,8 @@ entry: ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} -;SI-CHECK: V_LOG_F32 -;SI-CHECK: V_LOG_F32 +;SI-CHECK: v_log_f32 +;SI-CHECK: v_log_f32 define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) { entry: @@ -63,10 +63,10 @@ entry: ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} ;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} -;SI-CHECK: V_LOG_F32 -;SI-CHECK: V_LOG_F32 -;SI-CHECK: V_LOG_F32 -;SI-CHECK: V_LOG_F32 +;SI-CHECK: v_log_f32 +;SI-CHECK: v_log_f32 +;SI-CHECK: v_log_f32 +;SI-CHECK: v_log_f32 define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) { entry: %0 = call <4 x float> @llvm.log2.v4f32(<4 x float> %in) diff --git a/test/CodeGen/R600/llvm.memcpy.ll b/test/CodeGen/R600/llvm.memcpy.ll index 5cf388daea6..5f2710aa37e 100644 --- a/test/CodeGen/R600/llvm.memcpy.ll +++ b/test/CodeGen/R600/llvm.memcpy.ll @@ -5,79 +5,79 @@ declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace ; FUNC-LABEL: {{^}}test_small_memcpy_i64_lds_to_lds_align1: -; SI: DS_READ_U8 -; SI: DS_WRITE_B8 -; SI: DS_READ_U8 -; SI: DS_WRITE_B8 -; SI: DS_READ_U8 -; SI: DS_WRITE_B8 -; SI: DS_READ_U8 -; SI: DS_WRITE_B8 -; SI: DS_READ_U8 -; SI: DS_WRITE_B8 - -; SI: DS_READ_U8 -; SI: DS_WRITE_B8 -; SI: DS_READ_U8 -; SI: DS_WRITE_B8 -; SI: DS_READ_U8 -; SI: DS_WRITE_B8 -; SI: DS_READ_U8 -; SI: DS_WRITE_B8 -; SI: DS_READ_U8 -; SI: DS_WRITE_B8 - -; SI: DS_READ_U8 -; SI: DS_WRITE_B8 -; SI: DS_READ_U8 -; SI: DS_WRITE_B8 -; SI: DS_READ_U8 -; SI: DS_WRITE_B8 -; SI: DS_READ_U8 -; SI: DS_WRITE_B8 -; SI: DS_READ_U8 -; SI: DS_READ_U8 - - -; SI: DS_READ_U8 -; SI: DS_READ_U8 -; SI: DS_READ_U8 -; SI: DS_READ_U8 -; SI: DS_READ_U8 -; SI: DS_READ_U8 -; SI: DS_READ_U8 -; SI: DS_READ_U8 - -; SI: DS_READ_U8 -; SI: DS_READ_U8 -; SI: DS_READ_U8 -; SI: DS_READ_U8 -; SI: DS_READ_U8 -; SI: DS_READ_U8 -; SI: DS_READ_U8 -; SI: DS_READ_U8 - -; SI: DS_WRITE_B8 -; SI: DS_WRITE_B8 -; SI: DS_WRITE_B8 -; SI: DS_WRITE_B8 -; SI: DS_WRITE_B8 -; SI: DS_WRITE_B8 -; SI: DS_WRITE_B8 -; SI: DS_WRITE_B8 -; SI: DS_WRITE_B8 - -; SI: DS_WRITE_B8 -; SI: DS_WRITE_B8 -; SI: DS_WRITE_B8 -; SI: DS_WRITE_B8 -; SI: DS_WRITE_B8 -; SI: DS_WRITE_B8 -; SI: DS_WRITE_B8 -; SI: DS_WRITE_B8 -; SI: DS_WRITE_B8 - -; SI: S_ENDPGM +; SI: ds_read_u8 +; SI: ds_write_b8 +; SI: ds_read_u8 +; SI: ds_write_b8 +; SI: ds_read_u8 +; SI: ds_write_b8 +; SI: ds_read_u8 +; SI: ds_write_b8 +; SI: ds_read_u8 +; SI: ds_write_b8 + +; SI: ds_read_u8 +; SI: ds_write_b8 +; SI: ds_read_u8 +; SI: ds_write_b8 +; SI: ds_read_u8 +; SI: ds_write_b8 +; SI: ds_read_u8 +; SI: ds_write_b8 +; SI: ds_read_u8 +; SI: ds_write_b8 + +; SI: ds_read_u8 +; SI: ds_write_b8 +; SI: ds_read_u8 +; SI: ds_write_b8 +; SI: ds_read_u8 +; SI: ds_write_b8 +; SI: ds_read_u8 +; SI: ds_write_b8 +; SI: ds_read_u8 +; SI: ds_read_u8 + + +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 + +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 +; SI: ds_read_u8 + +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 + +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 + +; SI: s_endpgm define void @test_small_memcpy_i64_lds_to_lds_align1(i64 addrspace(3)* noalias %out, i64 addrspace(3)* noalias %in) nounwind { %bcin = bitcast i64 addrspace(3)* %in to i8 addrspace(3)* %bcout = bitcast i64 addrspace(3)* %out to i8 addrspace(3)* @@ -86,43 +86,43 @@ define void @test_small_memcpy_i64_lds_to_lds_align1(i64 addrspace(3)* noalias % } ; FUNC-LABEL: {{^}}test_small_memcpy_i64_lds_to_lds_align2: -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 - -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 - -; SI: DS_WRITE_B16 -; SI: DS_WRITE_B16 -; SI: DS_WRITE_B16 -; SI: DS_WRITE_B16 -; SI: DS_WRITE_B16 -; SI: DS_WRITE_B16 -; SI: DS_WRITE_B16 -; SI: DS_WRITE_B16 - -; SI: DS_WRITE_B16 -; SI: DS_WRITE_B16 -; SI: DS_WRITE_B16 -; SI: DS_WRITE_B16 -; SI: DS_WRITE_B16 -; SI: DS_WRITE_B16 -; SI: DS_WRITE_B16 -; SI: DS_WRITE_B16 - -; SI: S_ENDPGM +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 + +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 + +; SI: ds_write_b16 +; SI: ds_write_b16 +; SI: ds_write_b16 +; SI: ds_write_b16 +; SI: ds_write_b16 +; SI: ds_write_b16 +; SI: ds_write_b16 +; SI: ds_write_b16 + +; SI: ds_write_b16 +; SI: ds_write_b16 +; SI: ds_write_b16 +; SI: ds_write_b16 +; SI: ds_write_b16 +; SI: ds_write_b16 +; SI: ds_write_b16 +; SI: ds_write_b16 + +; SI: s_endpgm define void @test_small_memcpy_i64_lds_to_lds_align2(i64 addrspace(3)* noalias %out, i64 addrspace(3)* noalias %in) nounwind { %bcin = bitcast i64 addrspace(3)* %in to i8 addrspace(3)* %bcout = bitcast i64 addrspace(3)* %out to i8 addrspace(3)* @@ -131,34 +131,34 @@ define void @test_small_memcpy_i64_lds_to_lds_align2(i64 addrspace(3)* noalias % } ; FUNC-LABEL: {{^}}test_small_memcpy_i64_lds_to_lds_align4: -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI: S_ENDPGM +; SI: s_endpgm define void @test_small_memcpy_i64_lds_to_lds_align4(i64 addrspace(3)* noalias %out, i64 addrspace(3)* noalias %in) nounwind { %bcin = bitcast i64 addrspace(3)* %in to i8 addrspace(3)* %bcout = bitcast i64 addrspace(3)* %out to i8 addrspace(3)* @@ -169,34 +169,34 @@ define void @test_small_memcpy_i64_lds_to_lds_align4(i64 addrspace(3)* noalias % ; FIXME: Use 64-bit ops ; FUNC-LABEL: {{^}}test_small_memcpy_i64_lds_to_lds_align8: -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: DS_READ_B32 -; SI-DAG: DS_WRITE_B32 +; SI-DAG: ds_read_b32 +; SI-DAG: ds_write_b32 -; SI-DAG: S_ENDPGM +; SI-DAG: s_endpgm define void @test_small_memcpy_i64_lds_to_lds_align8(i64 addrspace(3)* noalias %out, i64 addrspace(3)* noalias %in) nounwind { %bcin = bitcast i64 addrspace(3)* %in to i8 addrspace(3)* %bcout = bitcast i64 addrspace(3)* %out to i8 addrspace(3)* @@ -205,75 +205,75 @@ define void @test_small_memcpy_i64_lds_to_lds_align8(i64 addrspace(3)* noalias % } ; FUNC-LABEL: {{^}}test_small_memcpy_i64_global_to_global_align1: -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE - -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE - -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE - -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE -; SI-DAG: BUFFER_LOAD_UBYTE -; SI-DAG: BUFFER_STORE_BYTE - -; SI: S_ENDPGM +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte + +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte + +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte + +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_load_ubyte +; SI-DAG: buffer_store_byte + +; SI: s_endpgm define void @test_small_memcpy_i64_global_to_global_align1(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { %bcin = bitcast i64 addrspace(1)* %in to i8 addrspace(1)* %bcout = bitcast i64 addrspace(1)* %out to i8 addrspace(1)* @@ -282,41 +282,41 @@ define void @test_small_memcpy_i64_global_to_global_align1(i64 addrspace(1)* noa } ; FUNC-LABEL: {{^}}test_small_memcpy_i64_global_to_global_align2: -; SI-DAG: BUFFER_LOAD_USHORT -; SI-DAG: BUFFER_LOAD_USHORT -; SI-DAG: BUFFER_LOAD_USHORT -; SI-DAG: BUFFER_LOAD_USHORT -; SI-DAG: BUFFER_LOAD_USHORT -; SI-DAG: BUFFER_LOAD_USHORT -; SI-DAG: BUFFER_LOAD_USHORT -; SI-DAG: BUFFER_LOAD_USHORT -; SI-DAG: BUFFER_LOAD_USHORT -; SI-DAG: BUFFER_LOAD_USHORT -; SI-DAG: BUFFER_LOAD_USHORT -; SI-DAG: BUFFER_LOAD_USHORT -; SI-DAG: BUFFER_LOAD_USHORT -; SI-DAG: BUFFER_LOAD_USHORT -; SI-DAG: BUFFER_LOAD_USHORT -; SI-DAG: BUFFER_LOAD_USHORT - -; SI-DAG: BUFFER_STORE_SHORT -; SI-DAG: BUFFER_STORE_SHORT -; SI-DAG: BUFFER_STORE_SHORT -; SI-DAG: BUFFER_STORE_SHORT -; SI-DAG: BUFFER_STORE_SHORT -; SI-DAG: BUFFER_STORE_SHORT -; SI-DAG: BUFFER_STORE_SHORT -; SI-DAG: BUFFER_STORE_SHORT -; SI-DAG: BUFFER_STORE_SHORT -; SI-DAG: BUFFER_STORE_SHORT -; SI-DAG: BUFFER_STORE_SHORT -; SI-DAG: BUFFER_STORE_SHORT -; SI-DAG: BUFFER_STORE_SHORT -; SI-DAG: BUFFER_STORE_SHORT -; SI-DAG: BUFFER_STORE_SHORT -; SI-DAG: BUFFER_STORE_SHORT - -; SI: S_ENDPGM +; SI-DAG: buffer_load_ushort +; SI-DAG: buffer_load_ushort +; SI-DAG: buffer_load_ushort +; SI-DAG: buffer_load_ushort +; SI-DAG: buffer_load_ushort +; SI-DAG: buffer_load_ushort +; SI-DAG: buffer_load_ushort +; SI-DAG: buffer_load_ushort +; SI-DAG: buffer_load_ushort +; SI-DAG: buffer_load_ushort +; SI-DAG: buffer_load_ushort +; SI-DAG: buffer_load_ushort +; SI-DAG: buffer_load_ushort +; SI-DAG: buffer_load_ushort +; SI-DAG: buffer_load_ushort +; SI-DAG: buffer_load_ushort + +; SI-DAG: buffer_store_short +; SI-DAG: buffer_store_short +; SI-DAG: buffer_store_short +; SI-DAG: buffer_store_short +; SI-DAG: buffer_store_short +; SI-DAG: buffer_store_short +; SI-DAG: buffer_store_short +; SI-DAG: buffer_store_short +; SI-DAG: buffer_store_short +; SI-DAG: buffer_store_short +; SI-DAG: buffer_store_short +; SI-DAG: buffer_store_short +; SI-DAG: buffer_store_short +; SI-DAG: buffer_store_short +; SI-DAG: buffer_store_short +; SI-DAG: buffer_store_short + +; SI: s_endpgm define void @test_small_memcpy_i64_global_to_global_align2(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { %bcin = bitcast i64 addrspace(1)* %in to i8 addrspace(1)* %bcout = bitcast i64 addrspace(1)* %out to i8 addrspace(1)* @@ -325,11 +325,11 @@ define void @test_small_memcpy_i64_global_to_global_align2(i64 addrspace(1)* noa } ; FUNC-LABEL: {{^}}test_small_memcpy_i64_global_to_global_align4: -; SI: BUFFER_LOAD_DWORDX4 -; SI: BUFFER_LOAD_DWORDX4 -; SI: BUFFER_STORE_DWORDX4 -; SI: BUFFER_STORE_DWORDX4 -; SI: S_ENDPGM +; SI: buffer_load_dwordx4 +; SI: buffer_load_dwordx4 +; SI: buffer_store_dwordx4 +; SI: buffer_store_dwordx4 +; SI: s_endpgm define void @test_small_memcpy_i64_global_to_global_align4(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { %bcin = bitcast i64 addrspace(1)* %in to i8 addrspace(1)* %bcout = bitcast i64 addrspace(1)* %out to i8 addrspace(1)* @@ -338,11 +338,11 @@ define void @test_small_memcpy_i64_global_to_global_align4(i64 addrspace(1)* noa } ; FUNC-LABEL: {{^}}test_small_memcpy_i64_global_to_global_align8: -; SI: BUFFER_LOAD_DWORDX4 -; SI: BUFFER_LOAD_DWORDX4 -; SI: BUFFER_STORE_DWORDX4 -; SI: BUFFER_STORE_DWORDX4 -; SI: S_ENDPGM +; SI: buffer_load_dwordx4 +; SI: buffer_load_dwordx4 +; SI: buffer_store_dwordx4 +; SI: buffer_store_dwordx4 +; SI: s_endpgm define void @test_small_memcpy_i64_global_to_global_align8(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { %bcin = bitcast i64 addrspace(1)* %in to i8 addrspace(1)* %bcout = bitcast i64 addrspace(1)* %out to i8 addrspace(1)* @@ -351,11 +351,11 @@ define void @test_small_memcpy_i64_global_to_global_align8(i64 addrspace(1)* noa } ; FUNC-LABEL: {{^}}test_small_memcpy_i64_global_to_global_align16: -; SI: BUFFER_LOAD_DWORDX4 -; SI: BUFFER_LOAD_DWORDX4 -; SI: BUFFER_STORE_DWORDX4 -; SI: BUFFER_STORE_DWORDX4 -; SI: S_ENDPGM +; SI: buffer_load_dwordx4 +; SI: buffer_load_dwordx4 +; SI: buffer_store_dwordx4 +; SI: buffer_store_dwordx4 +; SI: s_endpgm define void @test_small_memcpy_i64_global_to_global_align16(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { %bcin = bitcast i64 addrspace(1)* %in to i8 addrspace(1)* %bcout = bitcast i64 addrspace(1)* %out to i8 addrspace(1)* diff --git a/test/CodeGen/R600/llvm.rint.f64.ll b/test/CodeGen/R600/llvm.rint.f64.ll index ec82c91260c..72b546eb2bf 100644 --- a/test/CodeGen/R600/llvm.rint.f64.ll +++ b/test/CodeGen/R600/llvm.rint.f64.ll @@ -2,14 +2,14 @@ ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}rint_f64: -; CI: V_RNDNE_F64_e32 +; CI: v_rndne_f64_e32 -; SI-DAG: V_ADD_F64 -; SI-DAG: V_ADD_F64 -; SI-DAG V_CMP_GT_F64_e64 -; SI: V_CNDMASK_B32 -; SI: V_CNDMASK_B32 -; SI: S_ENDPGM +; SI-DAG: v_add_f64 +; SI-DAG: v_add_f64 +; SI-DAG v_cmp_gt_f64_e64 +; SI: v_cndmask_b32 +; SI: v_cndmask_b32 +; SI: s_endpgm define void @rint_f64(double addrspace(1)* %out, double %in) { entry: %0 = call double @llvm.rint.f64(double %in) @@ -18,8 +18,8 @@ entry: } ; FUNC-LABEL: {{^}}rint_v2f64: -; CI: V_RNDNE_F64_e32 -; CI: V_RNDNE_F64_e32 +; CI: v_rndne_f64_e32 +; CI: v_rndne_f64_e32 define void @rint_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) { entry: %0 = call <2 x double> @llvm.rint.v2f64(<2 x double> %in) @@ -28,10 +28,10 @@ entry: } ; FUNC-LABEL: {{^}}rint_v4f64: -; CI: V_RNDNE_F64_e32 -; CI: V_RNDNE_F64_e32 -; CI: V_RNDNE_F64_e32 -; CI: V_RNDNE_F64_e32 +; CI: v_rndne_f64_e32 +; CI: v_rndne_f64_e32 +; CI: v_rndne_f64_e32 +; CI: v_rndne_f64_e32 define void @rint_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) { entry: %0 = call <4 x double> @llvm.rint.v4f64(<4 x double> %in) diff --git a/test/CodeGen/R600/llvm.rint.ll b/test/CodeGen/R600/llvm.rint.ll index ddad5c8dbc0..2e059642995 100644 --- a/test/CodeGen/R600/llvm.rint.ll +++ b/test/CodeGen/R600/llvm.rint.ll @@ -4,7 +4,7 @@ ; FUNC-LABEL: {{^}}rint_f32: ; R600: RNDNE -; SI: V_RNDNE_F32_e32 +; SI: v_rndne_f32_e32 define void @rint_f32(float addrspace(1)* %out, float %in) { entry: %0 = call float @llvm.rint.f32(float %in) #0 @@ -16,8 +16,8 @@ entry: ; R600: RNDNE ; R600: RNDNE -; SI: V_RNDNE_F32_e32 -; SI: V_RNDNE_F32_e32 +; SI: v_rndne_f32_e32 +; SI: v_rndne_f32_e32 define void @rint_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { entry: %0 = call <2 x float> @llvm.rint.v2f32(<2 x float> %in) #0 @@ -31,10 +31,10 @@ entry: ; R600: RNDNE ; R600: RNDNE -; SI: V_RNDNE_F32_e32 -; SI: V_RNDNE_F32_e32 -; SI: V_RNDNE_F32_e32 -; SI: V_RNDNE_F32_e32 +; SI: v_rndne_f32_e32 +; SI: v_rndne_f32_e32 +; SI: v_rndne_f32_e32 +; SI: v_rndne_f32_e32 define void @rint_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { entry: %0 = call <4 x float> @llvm.rint.v4f32(<4 x float> %in) #0 @@ -45,7 +45,7 @@ entry: ; FUNC-LABEL: {{^}}legacy_amdil_round_nearest_f32: ; R600: RNDNE -; SI: V_RNDNE_F32_e32 +; SI: v_rndne_f32_e32 define void @legacy_amdil_round_nearest_f32(float addrspace(1)* %out, float %in) { entry: %0 = call float @llvm.AMDIL.round.nearest.f32(float %in) #0 diff --git a/test/CodeGen/R600/llvm.sin.ll b/test/CodeGen/R600/llvm.sin.ll index a365ecb0ccb..7e45710842f 100644 --- a/test/CodeGen/R600/llvm.sin.ll +++ b/test/CodeGen/R600/llvm.sin.ll @@ -8,10 +8,10 @@ ; EG: ADD * ; EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG-NOT: SIN -; SI: V_MUL_F32 -; SI: V_FRACT_F32 -; SI: V_SIN_F32 -; SI-NOT: V_SIN_F32 +; SI: v_mul_f32 +; SI: v_fract_f32 +; SI: v_sin_f32 +; SI-NOT: v_sin_f32 define void @sin_f32(float addrspace(1)* %out, float %x) #1 { %sin = call float @llvm.sin.f32(float %x) @@ -20,14 +20,14 @@ define void @sin_f32(float addrspace(1)* %out, float %x) #1 { } ; FUNC-LABEL: {{^}}sin_3x_f32: -; SI-UNSAFE-NOT: V_ADD_F32 +; SI-UNSAFE-NOT: v_add_f32 ; SI-UNSAFE: 0x3ef47644 -; SI-UNSAFE: V_MUL_F32 -; SI-SAFE: V_MUL_F32 -; SI-SAFE: V_MUL_F32 -; SI: V_FRACT_F32 -; SI: V_SIN_F32 -; SI-NOT: V_SIN_F32 +; SI-UNSAFE: v_mul_f32 +; SI-SAFE: v_mul_f32 +; SI-SAFE: v_mul_f32 +; SI: v_fract_f32 +; SI: v_sin_f32 +; SI-NOT: v_sin_f32 define void @sin_3x_f32(float addrspace(1)* %out, float %x) #1 { %y = fmul float 3.0, %x %sin = call float @llvm.sin.f32(float %y) @@ -36,14 +36,14 @@ define void @sin_3x_f32(float addrspace(1)* %out, float %x) #1 { } ; FUNC-LABEL: {{^}}sin_2x_f32: -; SI-UNSAFE-NOT: V_ADD_F32 +; SI-UNSAFE-NOT: v_add_f32 ; SI-UNSAFE: 0x3ea2f983 -; SI-UNSAFE: V_MUL_F32 -; SI-SAFE: V_ADD_F32 -; SI-SAFE: V_MUL_F32 -; SI: V_FRACT_F32 -; SI: V_SIN_F32 -; SI-NOT: V_SIN_F32 +; SI-UNSAFE: v_mul_f32 +; SI-SAFE: v_add_f32 +; SI-SAFE: v_mul_f32 +; SI: v_fract_f32 +; SI: v_sin_f32 +; SI-NOT: v_sin_f32 define void @sin_2x_f32(float addrspace(1)* %out, float %x) #1 { %y = fmul float 2.0, %x %sin = call float @llvm.sin.f32(float %y) @@ -53,12 +53,12 @@ define void @sin_2x_f32(float addrspace(1)* %out, float %x) #1 { ; FUNC-LABEL: {{^}}test_2sin_f32: ; SI-UNSAFE: 0x3ea2f983 -; SI-UNSAFE: V_MUL_F32 -; SI-SAFE: V_ADD_F32 -; SI-SAFE: V_MUL_F32 -; SI: V_FRACT_F32 -; SI: V_SIN_F32 -; SI-NOT: V_SIN_F32 +; SI-UNSAFE: v_mul_f32 +; SI-SAFE: v_add_f32 +; SI-SAFE: v_mul_f32 +; SI: v_fract_f32 +; SI: v_sin_f32 +; SI-NOT: v_sin_f32 define void @test_2sin_f32(float addrspace(1)* %out, float %x) #1 { %y = fmul float 2.0, %x %sin = call float @llvm.sin.f32(float %y) @@ -72,11 +72,11 @@ define void @test_2sin_f32(float addrspace(1)* %out, float %x) #1 { ; EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG-NOT: SIN -; SI: V_SIN_F32 -; SI: V_SIN_F32 -; SI: V_SIN_F32 -; SI: V_SIN_F32 -; SI-NOT: V_SIN_F32 +; SI: v_sin_f32 +; SI: v_sin_f32 +; SI: v_sin_f32 +; SI: v_sin_f32 +; SI-NOT: v_sin_f32 define void @sin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %vx) #1 { %sin = call <4 x float> @llvm.sin.v4f32( <4 x float> %vx) diff --git a/test/CodeGen/R600/llvm.sqrt.ll b/test/CodeGen/R600/llvm.sqrt.ll index 40d6b460e7b..c0392256c20 100644 --- a/test/CodeGen/R600/llvm.sqrt.ll +++ b/test/CodeGen/R600/llvm.sqrt.ll @@ -5,7 +5,7 @@ ; R600-CHECK: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].Z ; R600-CHECK: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].Z, PS ; SI-CHECK-LABEL: {{^}}sqrt_f32: -; SI-CHECK: V_SQRT_F32_e32 +; SI-CHECK: v_sqrt_f32_e32 define void @sqrt_f32(float addrspace(1)* %out, float %in) { entry: %0 = call float @llvm.sqrt.f32(float %in) @@ -19,8 +19,8 @@ entry: ; R600-CHECK-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].X ; R600-CHECK-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].X, PS ; SI-CHECK-LABEL: {{^}}sqrt_v2f32: -; SI-CHECK: V_SQRT_F32_e32 -; SI-CHECK: V_SQRT_F32_e32 +; SI-CHECK: v_sqrt_f32_e32 +; SI-CHECK: v_sqrt_f32_e32 define void @sqrt_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { entry: %0 = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in) @@ -38,10 +38,10 @@ entry: ; R600-CHECK-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[4].X ; R600-CHECK-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[4].X, PS ; SI-CHECK-LABEL: {{^}}sqrt_v4f32: -; SI-CHECK: V_SQRT_F32_e32 -; SI-CHECK: V_SQRT_F32_e32 -; SI-CHECK: V_SQRT_F32_e32 -; SI-CHECK: V_SQRT_F32_e32 +; SI-CHECK: v_sqrt_f32_e32 +; SI-CHECK: v_sqrt_f32_e32 +; SI-CHECK: v_sqrt_f32_e32 +; SI-CHECK: v_sqrt_f32_e32 define void @sqrt_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { entry: %0 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %in) diff --git a/test/CodeGen/R600/load-i1.ll b/test/CodeGen/R600/load-i1.ll index 2408f70cff2..d85e16f5248 100644 --- a/test/CodeGen/R600/load-i1.ll +++ b/test/CodeGen/R600/load-i1.ll @@ -2,10 +2,10 @@ ; SI-LABEL: {{^}}global_copy_i1_to_i1: -; SI: BUFFER_LOAD_UBYTE -; SI: V_AND_B32_e32 v{{[0-9]+}}, 1 -; SI: BUFFER_STORE_BYTE -; SI: S_ENDPGM +; SI: buffer_load_ubyte +; SI: v_and_b32_e32 v{{[0-9]+}}, 1 +; SI: buffer_store_byte +; SI: s_endpgm define void @global_copy_i1_to_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { %load = load i1 addrspace(1)* %in store i1 %load, i1 addrspace(1)* %out, align 1 @@ -14,8 +14,8 @@ define void @global_copy_i1_to_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) n ; SI-LABEL: {{^}}global_sextload_i1_to_i32: ; XSI: BUFFER_LOAD_BYTE -; SI: BUFFER_STORE_DWORD -; SI: S_ENDPGM +; SI: buffer_store_dword +; SI: s_endpgm define void @global_sextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { %load = load i1 addrspace(1)* %in %ext = sext i1 %load to i32 @@ -24,9 +24,9 @@ define void @global_sextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* } ; SI-LABEL: {{^}}global_zextload_i1_to_i32: -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_STORE_DWORD -; SI: S_ENDPGM +; SI: buffer_load_ubyte +; SI: buffer_store_dword +; SI: s_endpgm define void @global_zextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { %load = load i1 addrspace(1)* %in %ext = zext i1 %load to i32 @@ -36,8 +36,8 @@ define void @global_zextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* ; SI-LABEL: {{^}}global_sextload_i1_to_i64: ; XSI: BUFFER_LOAD_BYTE -; SI: BUFFER_STORE_DWORDX2 -; SI: S_ENDPGM +; SI: buffer_store_dwordx2 +; SI: s_endpgm define void @global_sextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { %load = load i1 addrspace(1)* %in %ext = sext i1 %load to i64 @@ -46,9 +46,9 @@ define void @global_sextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* } ; SI-LABEL: {{^}}global_zextload_i1_to_i64: -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_STORE_DWORDX2 -; SI: S_ENDPGM +; SI: buffer_load_ubyte +; SI: buffer_store_dwordx2 +; SI: s_endpgm define void @global_zextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { %load = load i1 addrspace(1)* %in %ext = zext i1 %load to i64 @@ -57,19 +57,19 @@ define void @global_zextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* } ; SI-LABEL: {{^}}i1_arg: -; SI: BUFFER_LOAD_UBYTE -; SI: V_AND_B32_e32 -; SI: BUFFER_STORE_BYTE -; SI: S_ENDPGM +; SI: buffer_load_ubyte +; SI: v_and_b32_e32 +; SI: buffer_store_byte +; SI: s_endpgm define void @i1_arg(i1 addrspace(1)* %out, i1 %x) nounwind { store i1 %x, i1 addrspace(1)* %out, align 1 ret void } ; SI-LABEL: {{^}}i1_arg_zext_i32: -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_STORE_DWORD -; SI: S_ENDPGM +; SI: buffer_load_ubyte +; SI: buffer_store_dword +; SI: s_endpgm define void @i1_arg_zext_i32(i32 addrspace(1)* %out, i1 %x) nounwind { %ext = zext i1 %x to i32 store i32 %ext, i32 addrspace(1)* %out, align 4 @@ -77,9 +77,9 @@ define void @i1_arg_zext_i32(i32 addrspace(1)* %out, i1 %x) nounwind { } ; SI-LABEL: {{^}}i1_arg_zext_i64: -; SI: BUFFER_LOAD_UBYTE -; SI: BUFFER_STORE_DWORDX2 -; SI: S_ENDPGM +; SI: buffer_load_ubyte +; SI: buffer_store_dwordx2 +; SI: s_endpgm define void @i1_arg_zext_i64(i64 addrspace(1)* %out, i1 %x) nounwind { %ext = zext i1 %x to i64 store i64 %ext, i64 addrspace(1)* %out, align 8 @@ -88,8 +88,8 @@ define void @i1_arg_zext_i64(i64 addrspace(1)* %out, i1 %x) nounwind { ; SI-LABEL: {{^}}i1_arg_sext_i32: ; XSI: BUFFER_LOAD_BYTE -; SI: BUFFER_STORE_DWORD -; SI: S_ENDPGM +; SI: buffer_store_dword +; SI: s_endpgm define void @i1_arg_sext_i32(i32 addrspace(1)* %out, i1 %x) nounwind { %ext = sext i1 %x to i32 store i32 %ext, i32addrspace(1)* %out, align 4 @@ -98,8 +98,8 @@ define void @i1_arg_sext_i32(i32 addrspace(1)* %out, i1 %x) nounwind { ; SI-LABEL: {{^}}i1_arg_sext_i64: ; XSI: BUFFER_LOAD_BYTE -; SI: BUFFER_STORE_DWORDX2 -; SI: S_ENDPGM +; SI: buffer_store_dwordx2 +; SI: s_endpgm define void @i1_arg_sext_i64(i64 addrspace(1)* %out, i1 %x) nounwind { %ext = sext i1 %x to i64 store i64 %ext, i64 addrspace(1)* %out, align 8 diff --git a/test/CodeGen/R600/load.ll b/test/CodeGen/R600/load.ll index 882976b6d2a..c228c191766 100644 --- a/test/CodeGen/R600/load.ll +++ b/test/CodeGen/R600/load.ll @@ -10,7 +10,7 @@ ; FUNC-LABEL: {{^}}load_i8: ; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-CHECK: BUFFER_LOAD_UBYTE v{{[0-9]+}}, +; SI-CHECK: buffer_load_ubyte v{{[0-9]+}}, define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { %1 = load i8 addrspace(1)* %in %2 = zext i8 %1 to i32 @@ -24,7 +24,7 @@ define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { ; R600-CHECK: 24 ; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] ; R600-CHECK: 24 -; SI-CHECK: BUFFER_LOAD_SBYTE +; SI-CHECK: buffer_load_sbyte define void @load_i8_sext(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { entry: %0 = load i8 addrspace(1)* %in @@ -36,8 +36,8 @@ entry: ; FUNC-LABEL: {{^}}load_v2i8: ; R600-CHECK: VTX_READ_8 ; R600-CHECK: VTX_READ_8 -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte define void @load_v2i8(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) { entry: %0 = load <2 x i8> addrspace(1)* %in @@ -57,8 +57,8 @@ entry: ; R600-CHECK-DAG: 24 ; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]] ; R600-CHECK-DAG: 24 -; SI-CHECK: BUFFER_LOAD_SBYTE -; SI-CHECK: BUFFER_LOAD_SBYTE +; SI-CHECK: buffer_load_sbyte +; SI-CHECK: buffer_load_sbyte define void @load_v2i8_sext(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) { entry: %0 = load <2 x i8> addrspace(1)* %in @@ -72,10 +72,10 @@ entry: ; R600-CHECK: VTX_READ_8 ; R600-CHECK: VTX_READ_8 ; R600-CHECK: VTX_READ_8 -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE -; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte +; SI-CHECK: buffer_load_ubyte define void @load_v4i8(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) { entry: %0 = load <4 x i8> addrspace(1)* %in @@ -105,10 +105,10 @@ entry: ; R600-CHECK-DAG: 24 ; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_W_CHAN]] ; R600-CHECK-DAG: 24 -; SI-CHECK: BUFFER_LOAD_SBYTE -; SI-CHECK: BUFFER_LOAD_SBYTE -; SI-CHECK: BUFFER_LOAD_SBYTE -; SI-CHECK: BUFFER_LOAD_SBYTE +; SI-CHECK: buffer_load_sbyte +; SI-CHECK: buffer_load_sbyte +; SI-CHECK: buffer_load_sbyte +; SI-CHECK: buffer_load_sbyte define void @load_v4i8_sext(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) { entry: %0 = load <4 x i8> addrspace(1)* %in @@ -120,7 +120,7 @@ entry: ; Load an i16 value from the global address space. ; FUNC-LABEL: {{^}}load_i16: ; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: buffer_load_ushort define void @load_i16(i32 addrspace(1)* %out, i16 addrspace(1)* %in) { entry: %0 = load i16 addrspace(1)* %in @@ -135,7 +135,7 @@ entry: ; R600-CHECK: 16 ; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] ; R600-CHECK: 16 -; SI-CHECK: BUFFER_LOAD_SSHORT +; SI-CHECK: buffer_load_sshort define void @load_i16_sext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) { entry: %0 = load i16 addrspace(1)* %in @@ -147,8 +147,8 @@ entry: ; FUNC-LABEL: {{^}}load_v2i16: ; R600-CHECK: VTX_READ_16 ; R600-CHECK: VTX_READ_16 -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort define void @load_v2i16(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) { entry: %0 = load <2 x i16> addrspace(1)* %in @@ -168,8 +168,8 @@ entry: ; R600-CHECK-DAG: 16 ; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]] ; R600-CHECK-DAG: 16 -; SI-CHECK: BUFFER_LOAD_SSHORT -; SI-CHECK: BUFFER_LOAD_SSHORT +; SI-CHECK: buffer_load_sshort +; SI-CHECK: buffer_load_sshort define void @load_v2i16_sext(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) { entry: %0 = load <2 x i16> addrspace(1)* %in @@ -183,10 +183,10 @@ entry: ; R600-CHECK: VTX_READ_16 ; R600-CHECK: VTX_READ_16 ; R600-CHECK: VTX_READ_16 -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT -; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort +; SI-CHECK: buffer_load_ushort define void @load_v4i16(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) { entry: %0 = load <4 x i16> addrspace(1)* %in @@ -216,10 +216,10 @@ entry: ; R600-CHECK-DAG: 16 ; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_W_CHAN]] ; R600-CHECK-DAG: 16 -; SI-CHECK: BUFFER_LOAD_SSHORT -; SI-CHECK: BUFFER_LOAD_SSHORT -; SI-CHECK: BUFFER_LOAD_SSHORT -; SI-CHECK: BUFFER_LOAD_SSHORT +; SI-CHECK: buffer_load_sshort +; SI-CHECK: buffer_load_sshort +; SI-CHECK: buffer_load_sshort +; SI-CHECK: buffer_load_sshort define void @load_v4i16_sext(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) { entry: %0 = load <4 x i16> addrspace(1)* %in @@ -232,7 +232,7 @@ entry: ; FUNC-LABEL: {{^}}load_i32: ; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 -; SI-CHECK: BUFFER_LOAD_DWORD v{{[0-9]+}} +; SI-CHECK: buffer_load_dword v{{[0-9]+}} define void @load_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { entry: %0 = load i32 addrspace(1)* %in @@ -244,7 +244,7 @@ entry: ; FUNC-LABEL: {{^}}load_f32: ; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 -; SI-CHECK: BUFFER_LOAD_DWORD v{{[0-9]+}} +; SI-CHECK: buffer_load_dword v{{[0-9]+}} define void @load_f32(float addrspace(1)* %out, float addrspace(1)* %in) { entry: %0 = load float addrspace(1)* %in @@ -256,7 +256,7 @@ entry: ; FUNC-LABEL: {{^}}load_v2f32: ; R600-CHECK: MEM_RAT ; R600-CHECK: VTX_READ_64 -; SI-CHECK: BUFFER_LOAD_DWORDX2 +; SI-CHECK: buffer_load_dwordx2 define void @load_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) { entry: %0 = load <2 x float> addrspace(1)* %in @@ -266,7 +266,7 @@ entry: ; FUNC-LABEL: {{^}}load_i64: ; R600-CHECK: VTX_READ_64 -; SI-CHECK: BUFFER_LOAD_DWORDX2 +; SI-CHECK: buffer_load_dwordx2 define void @load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { entry: %0 = load i64 addrspace(1)* %in @@ -279,7 +279,7 @@ entry: ; R600-CHECK: MEM_RAT ; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal.x ; R600-CHECK: 31 -; SI-CHECK: BUFFER_LOAD_DWORD +; SI-CHECK: buffer_load_dword define void @load_i64_sext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) { entry: @@ -304,14 +304,14 @@ entry: ; R600-CHECK: VTX_READ_128 ; R600-CHECK: VTX_READ_128 ; XXX: We should be using DWORDX4 instructions on SI. -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword define void @load_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) { entry: %0 = load <8 x i32> addrspace(1)* %in @@ -325,22 +325,22 @@ entry: ; R600-CHECK: VTX_READ_128 ; R600-CHECK: VTX_READ_128 ; XXX: We should be using DWORDX4 instructions on SI. -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD -; SI-CHECK: BUFFER_LOAD_DWORD +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword +; SI-CHECK: buffer_load_dword define void @load_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(1)* %in) { entry: %0 = load <16 x i32> addrspace(1)* %in @@ -359,7 +359,7 @@ entry: ; R600-CHECK: 24 ; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] ; R600-CHECK: 24 -; SI-CHECK: BUFFER_LOAD_SBYTE v{{[0-9]+}}, +; SI-CHECK: buffer_load_sbyte v{{[0-9]+}}, define void @load_const_i8_sext(i32 addrspace(1)* %out, i8 addrspace(2)* %in) { entry: %0 = load i8 addrspace(2)* %in @@ -371,7 +371,7 @@ entry: ; Load an aligned i8 value ; FUNC-LABEL: {{^}}load_const_i8_aligned: ; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-CHECK: BUFFER_LOAD_UBYTE v{{[0-9]+}}, +; SI-CHECK: buffer_load_ubyte v{{[0-9]+}}, define void @load_const_i8_aligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) { entry: %0 = load i8 addrspace(2)* %in @@ -383,7 +383,7 @@ entry: ; Load an un-aligned i8 value ; FUNC-LABEL: {{^}}load_const_i8_unaligned: ; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-CHECK: BUFFER_LOAD_UBYTE v{{[0-9]+}}, +; SI-CHECK: buffer_load_ubyte v{{[0-9]+}}, define void @load_const_i8_unaligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) { entry: %0 = getelementptr i8 addrspace(2)* %in, i32 1 @@ -400,7 +400,7 @@ entry: ; R600-CHECK: 16 ; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] ; R600-CHECK: 16 -; SI-CHECK: BUFFER_LOAD_SSHORT +; SI-CHECK: buffer_load_sshort define void @load_const_i16_sext(i32 addrspace(1)* %out, i16 addrspace(2)* %in) { entry: %0 = load i16 addrspace(2)* %in @@ -412,7 +412,7 @@ entry: ; Load an aligned i16 value ; FUNC-LABEL: {{^}}load_const_i16_aligned: ; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: buffer_load_ushort define void @load_const_i16_aligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) { entry: %0 = load i16 addrspace(2)* %in @@ -424,7 +424,7 @@ entry: ; Load an un-aligned i16 value ; FUNC-LABEL: {{^}}load_const_i16_unaligned: ; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: buffer_load_ushort define void @load_const_i16_unaligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) { entry: %0 = getelementptr i16 addrspace(2)* %in, i32 1 @@ -438,7 +438,7 @@ entry: ; FUNC-LABEL: {{^}}load_const_addrspace_i32: ; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 -; SI-CHECK: S_LOAD_DWORD s{{[0-9]+}} +; SI-CHECK: s_load_dword s{{[0-9]+}} define void @load_const_addrspace_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { entry: %0 = load i32 addrspace(2)* %in @@ -450,7 +450,7 @@ entry: ; FUNC-LABEL: {{^}}load_const_addrspace_f32: ; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 -; SI-CHECK: S_LOAD_DWORD s{{[0-9]+}} +; SI-CHECK: s_load_dword s{{[0-9]+}} define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(2)* %in) { %1 = load float addrspace(2)* %in store float %1, float addrspace(1)* %out @@ -464,9 +464,9 @@ define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace( ; Load an i8 value from the local address space. ; FUNC-LABEL: {{^}}load_i8_local: ; R600-CHECK: LDS_UBYTE_READ_RET -; SI-CHECK-NOT: S_WQM_B64 -; SI-CHECK: S_MOV_B32 m0 -; SI-CHECK: DS_READ_U8 +; SI-CHECK-NOT: s_wqm_b64 +; SI-CHECK: s_mov_b32 m0 +; SI-CHECK: ds_read_u8 define void @load_i8_local(i32 addrspace(1)* %out, i8 addrspace(3)* %in) { %1 = load i8 addrspace(3)* %in %2 = zext i8 %1 to i32 @@ -477,9 +477,9 @@ define void @load_i8_local(i32 addrspace(1)* %out, i8 addrspace(3)* %in) { ; FUNC-LABEL: {{^}}load_i8_sext_local: ; R600-CHECK: LDS_UBYTE_READ_RET ; R600-CHECK: ASHR -; SI-CHECK-NOT: S_WQM_B64 -; SI-CHECK: S_MOV_B32 m0 -; SI-CHECK: DS_READ_I8 +; SI-CHECK-NOT: s_wqm_b64 +; SI-CHECK: s_mov_b32 m0 +; SI-CHECK: ds_read_i8 define void @load_i8_sext_local(i32 addrspace(1)* %out, i8 addrspace(3)* %in) { entry: %0 = load i8 addrspace(3)* %in @@ -491,10 +491,10 @@ entry: ; FUNC-LABEL: {{^}}load_v2i8_local: ; R600-CHECK: LDS_UBYTE_READ_RET ; R600-CHECK: LDS_UBYTE_READ_RET -; SI-CHECK-NOT: S_WQM_B64 -; SI-CHECK: S_MOV_B32 m0 -; SI-CHECK: DS_READ_U8 -; SI-CHECK: DS_READ_U8 +; SI-CHECK-NOT: s_wqm_b64 +; SI-CHECK: s_mov_b32 m0 +; SI-CHECK: ds_read_u8 +; SI-CHECK: ds_read_u8 define void @load_v2i8_local(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(3)* %in) { entry: %0 = load <2 x i8> addrspace(3)* %in @@ -508,10 +508,10 @@ entry: ; R600-CHECK-DAG: LDS_UBYTE_READ_RET ; R600-CHECK-DAG: ASHR ; R600-CHECK-DAG: ASHR -; SI-CHECK-NOT: S_WQM_B64 -; SI-CHECK: S_MOV_B32 m0 -; SI-CHECK: DS_READ_I8 -; SI-CHECK: DS_READ_I8 +; SI-CHECK-NOT: s_wqm_b64 +; SI-CHECK: s_mov_b32 m0 +; SI-CHECK: ds_read_i8 +; SI-CHECK: ds_read_i8 define void @load_v2i8_sext_local(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(3)* %in) { entry: %0 = load <2 x i8> addrspace(3)* %in @@ -525,12 +525,12 @@ entry: ; R600-CHECK: LDS_UBYTE_READ_RET ; R600-CHECK: LDS_UBYTE_READ_RET ; R600-CHECK: LDS_UBYTE_READ_RET -; SI-CHECK-NOT: S_WQM_B64 -; SI-CHECK: S_MOV_B32 m0 -; SI-CHECK: DS_READ_U8 -; SI-CHECK: DS_READ_U8 -; SI-CHECK: DS_READ_U8 -; SI-CHECK: DS_READ_U8 +; SI-CHECK-NOT: s_wqm_b64 +; SI-CHECK: s_mov_b32 m0 +; SI-CHECK: ds_read_u8 +; SI-CHECK: ds_read_u8 +; SI-CHECK: ds_read_u8 +; SI-CHECK: ds_read_u8 define void @load_v4i8_local(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(3)* %in) { entry: %0 = load <4 x i8> addrspace(3)* %in @@ -548,12 +548,12 @@ entry: ; R600-CHECK-DAG: ASHR ; R600-CHECK-DAG: ASHR ; R600-CHECK-DAG: ASHR -; SI-CHECK-NOT: S_WQM_B64 -; SI-CHECK: S_MOV_B32 m0 -; SI-CHECK: DS_READ_I8 -; SI-CHECK: DS_READ_I8 -; SI-CHECK: DS_READ_I8 -; SI-CHECK: DS_READ_I8 +; SI-CHECK-NOT: s_wqm_b64 +; SI-CHECK: s_mov_b32 m0 +; SI-CHECK: ds_read_i8 +; SI-CHECK: ds_read_i8 +; SI-CHECK: ds_read_i8 +; SI-CHECK: ds_read_i8 define void @load_v4i8_sext_local(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(3)* %in) { entry: %0 = load <4 x i8> addrspace(3)* %in @@ -565,9 +565,9 @@ entry: ; Load an i16 value from the local address space. ; FUNC-LABEL: {{^}}load_i16_local: ; R600-CHECK: LDS_USHORT_READ_RET -; SI-CHECK-NOT: S_WQM_B64 -; SI-CHECK: S_MOV_B32 m0 -; SI-CHECK: DS_READ_U16 +; SI-CHECK-NOT: s_wqm_b64 +; SI-CHECK: s_mov_b32 m0 +; SI-CHECK: ds_read_u16 define void @load_i16_local(i32 addrspace(1)* %out, i16 addrspace(3)* %in) { entry: %0 = load i16 addrspace(3)* %in @@ -579,9 +579,9 @@ entry: ; FUNC-LABEL: {{^}}load_i16_sext_local: ; R600-CHECK: LDS_USHORT_READ_RET ; R600-CHECK: ASHR -; SI-CHECK-NOT: S_WQM_B64 -; SI-CHECK: S_MOV_B32 m0 -; SI-CHECK: DS_READ_I16 +; SI-CHECK-NOT: s_wqm_b64 +; SI-CHECK: s_mov_b32 m0 +; SI-CHECK: ds_read_i16 define void @load_i16_sext_local(i32 addrspace(1)* %out, i16 addrspace(3)* %in) { entry: %0 = load i16 addrspace(3)* %in @@ -593,10 +593,10 @@ entry: ; FUNC-LABEL: {{^}}load_v2i16_local: ; R600-CHECK: LDS_USHORT_READ_RET ; R600-CHECK: LDS_USHORT_READ_RET -; SI-CHECK-NOT: S_WQM_B64 -; SI-CHECK: S_MOV_B32 m0 -; SI-CHECK: DS_READ_U16 -; SI-CHECK: DS_READ_U16 +; SI-CHECK-NOT: s_wqm_b64 +; SI-CHECK: s_mov_b32 m0 +; SI-CHECK: ds_read_u16 +; SI-CHECK: ds_read_u16 define void @load_v2i16_local(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(3)* %in) { entry: %0 = load <2 x i16> addrspace(3)* %in @@ -610,10 +610,10 @@ entry: ; R600-CHECK-DAG: LDS_USHORT_READ_RET ; R600-CHECK-DAG: ASHR ; R600-CHECK-DAG: ASHR -; SI-CHECK-NOT: S_WQM_B64 -; SI-CHECK: S_MOV_B32 m0 -; SI-CHECK: DS_READ_I16 -; SI-CHECK: DS_READ_I16 +; SI-CHECK-NOT: s_wqm_b64 +; SI-CHECK: s_mov_b32 m0 +; SI-CHECK: ds_read_i16 +; SI-CHECK: ds_read_i16 define void @load_v2i16_sext_local(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(3)* %in) { entry: %0 = load <2 x i16> addrspace(3)* %in @@ -627,12 +627,12 @@ entry: ; R600-CHECK: LDS_USHORT_READ_RET ; R600-CHECK: LDS_USHORT_READ_RET ; R600-CHECK: LDS_USHORT_READ_RET -; SI-CHECK-NOT: S_WQM_B64 -; SI-CHECK: S_MOV_B32 m0 -; SI-CHECK: DS_READ_U16 -; SI-CHECK: DS_READ_U16 -; SI-CHECK: DS_READ_U16 -; SI-CHECK: DS_READ_U16 +; SI-CHECK-NOT: s_wqm_b64 +; SI-CHECK: s_mov_b32 m0 +; SI-CHECK: ds_read_u16 +; SI-CHECK: ds_read_u16 +; SI-CHECK: ds_read_u16 +; SI-CHECK: ds_read_u16 define void @load_v4i16_local(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(3)* %in) { entry: %0 = load <4 x i16> addrspace(3)* %in @@ -650,12 +650,12 @@ entry: ; R600-CHECK-DAG: ASHR ; R600-CHECK-DAG: ASHR ; R600-CHECK-DAG: ASHR -; SI-CHECK-NOT: S_WQM_B64 -; SI-CHECK: S_MOV_B32 m0 -; SI-CHECK: DS_READ_I16 -; SI-CHECK: DS_READ_I16 -; SI-CHECK: DS_READ_I16 -; SI-CHECK: DS_READ_I16 +; SI-CHECK-NOT: s_wqm_b64 +; SI-CHECK: s_mov_b32 m0 +; SI-CHECK: ds_read_i16 +; SI-CHECK: ds_read_i16 +; SI-CHECK: ds_read_i16 +; SI-CHECK: ds_read_i16 define void @load_v4i16_sext_local(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(3)* %in) { entry: %0 = load <4 x i16> addrspace(3)* %in @@ -667,9 +667,9 @@ entry: ; load an i32 value from the local address space. ; FUNC-LABEL: {{^}}load_i32_local: ; R600-CHECK: LDS_READ_RET -; SI-CHECK-NOT: S_WQM_B64 -; SI-CHECK: S_MOV_B32 m0 -; SI-CHECK: DS_READ_B32 +; SI-CHECK-NOT: s_wqm_b64 +; SI-CHECK: s_mov_b32 m0 +; SI-CHECK: ds_read_b32 define void @load_i32_local(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { entry: %0 = load i32 addrspace(3)* %in @@ -680,8 +680,8 @@ entry: ; load a f32 value from the local address space. ; FUNC-LABEL: {{^}}load_f32_local: ; R600-CHECK: LDS_READ_RET -; SI-CHECK: S_MOV_B32 m0 -; SI-CHECK: DS_READ_B32 +; SI-CHECK: s_mov_b32 m0 +; SI-CHECK: ds_read_b32 define void @load_f32_local(float addrspace(1)* %out, float addrspace(3)* %in) { entry: %0 = load float addrspace(3)* %in @@ -693,8 +693,8 @@ entry: ; FUNC-LABEL: {{^}}load_v2f32_local: ; R600-CHECK: LDS_READ_RET ; R600-CHECK: LDS_READ_RET -; SI-CHECK: S_MOV_B32 m0 -; SI-CHECK: DS_READ_B64 +; SI-CHECK: s_mov_b32 m0 +; SI-CHECK: ds_read_b64 define void @load_v2f32_local(<2 x float> addrspace(1)* %out, <2 x float> addrspace(3)* %in) { entry: %0 = load <2 x float> addrspace(3)* %in @@ -707,8 +707,8 @@ entry: ; R600-CHECK: LDS_READ_RET ; R600-CHECK: LDS_READ_RET ; R600-CHECK: LDS_READ_RET -; SI-CHECK-DAG: DS_READ_B32 -; SI-CHECK-DAG: DS_READ2_B32 +; SI-CHECK-DAG: ds_read_b32 +; SI-CHECK-DAG: ds_read2_b32 define void @load_i32_v2i32_local(<2 x i32> addrspace(1)* %out, i32 addrspace(3)* %in) { %scalar = load i32 addrspace(3)* %in %tmp0 = bitcast i32 addrspace(3)* %in to <2 x i32> addrspace(3)* @@ -726,8 +726,8 @@ define void @load_i32_v2i32_local(<2 x i32> addrspace(1)* %out, i32 addrspace(3) ; On SI we need to make sure that the base offset is a register and not ; an immediate. ; FUNC-LABEL: {{^}}load_i32_local_const_ptr: -; SI-CHECK: V_MOV_B32_e32 v[[ZERO:[0-9]+]], 0 -; SI-CHECK: DS_READ_B32 v0, v[[ZERO]] offset:4 +; SI-CHECK: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0 +; SI-CHECK: ds_read_b32 v0, v[[ZERO]] offset:4 ; R600-CHECK: LDS_READ_RET define void @load_i32_local_const_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { entry: diff --git a/test/CodeGen/R600/load.vec.ll b/test/CodeGen/R600/load.vec.ll index 5776d45f56c..0d6e21383c9 100644 --- a/test/CodeGen/R600/load.vec.ll +++ b/test/CodeGen/R600/load.vec.ll @@ -5,7 +5,7 @@ ; EG-CHECK: {{^}}load_v2i32: ; EG-CHECK: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0 ; SI-CHECK: {{^}}load_v2i32: -; SI-CHECK: BUFFER_LOAD_DWORDX2 v[{{[0-9]+:[0-9]+}}] +; SI-CHECK: buffer_load_dwordx2 v[{{[0-9]+:[0-9]+}}] define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %a = load <2 x i32> addrspace(1) * %in store <2 x i32> %a, <2 x i32> addrspace(1)* %out @@ -16,7 +16,7 @@ define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %i ; EG-CHECK: {{^}}load_v4i32: ; EG-CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0 ; SI-CHECK: {{^}}load_v4i32: -; SI-CHECK: BUFFER_LOAD_DWORDX4 v[{{[0-9]+:[0-9]+}}] +; SI-CHECK: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}] define void @load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %a = load <4 x i32> addrspace(1) * %in store <4 x i32> %a, <4 x i32> addrspace(1)* %out diff --git a/test/CodeGen/R600/load64.ll b/test/CodeGen/R600/load64.ll index 1668db2128f..a60c4eb1a52 100644 --- a/test/CodeGen/R600/load64.ll +++ b/test/CodeGen/R600/load64.ll @@ -2,8 +2,8 @@ ; load a f64 value from the global address space. ; CHECK-LABEL: {{^}}load_f64: -; CHECK: BUFFER_LOAD_DWORDX2 v[{{[0-9]+:[0-9]+}}] -; CHECK: BUFFER_STORE_DWORDX2 v[{{[0-9]+:[0-9]+}}] +; CHECK: buffer_load_dwordx2 v[{{[0-9]+:[0-9]+}}] +; CHECK: buffer_store_dwordx2 v[{{[0-9]+:[0-9]+}}] define void @load_f64(double addrspace(1)* %out, double addrspace(1)* %in) { %1 = load double addrspace(1)* %in store double %1, double addrspace(1)* %out @@ -11,8 +11,8 @@ define void @load_f64(double addrspace(1)* %out, double addrspace(1)* %in) { } ; CHECK-LABEL: {{^}}load_i64: -; CHECK: BUFFER_LOAD_DWORDX2 v[{{[0-9]+:[0-9]+}}] -; CHECK: BUFFER_STORE_DWORDX2 v[{{[0-9]+:[0-9]+}}] +; CHECK: buffer_load_dwordx2 v[{{[0-9]+:[0-9]+}}] +; CHECK: buffer_store_dwordx2 v[{{[0-9]+:[0-9]+}}] define void @load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { %tmp = load i64 addrspace(1)* %in store i64 %tmp, i64 addrspace(1)* %out, align 8 @@ -21,8 +21,8 @@ define void @load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { ; Load a f64 value from the constant address space. ; CHECK-LABEL: {{^}}load_const_addrspace_f64: -; CHECK: S_LOAD_DWORDX2 s[{{[0-9]+:[0-9]+}}] -; CHECK: BUFFER_STORE_DWORDX2 v[{{[0-9]+:[0-9]+}}] +; CHECK: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}] +; CHECK: buffer_store_dwordx2 v[{{[0-9]+:[0-9]+}}] define void @load_const_addrspace_f64(double addrspace(1)* %out, double addrspace(2)* %in) { %1 = load double addrspace(2)* %in store double %1, double addrspace(1)* %out diff --git a/test/CodeGen/R600/local-64.ll b/test/CodeGen/R600/local-64.ll index 9bf899b92d0..eb14b5f9af9 100644 --- a/test/CodeGen/R600/local-64.ll +++ b/test/CodeGen/R600/local-64.ll @@ -2,8 +2,8 @@ ; RUN: llc -march=r600 -mcpu=bonaire -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=BOTH %s ; BOTH-LABEL: {{^}}local_i32_load -; BOTH: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}} offset:28 [M0] -; BOTH: BUFFER_STORE_DWORD [[REG]], +; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} offset:28 [M0] +; BOTH: buffer_store_dword [[REG]], define void @local_i32_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind { %gep = getelementptr i32 addrspace(3)* %in, i32 7 %val = load i32 addrspace(3)* %gep, align 4 @@ -12,8 +12,8 @@ define void @local_i32_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounw } ; BOTH-LABEL: {{^}}local_i32_load_0_offset -; BOTH: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}} [M0] -; BOTH: BUFFER_STORE_DWORD [[REG]], +; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} [M0] +; BOTH: buffer_store_dword [[REG]], define void @local_i32_load_0_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind { %val = load i32 addrspace(3)* %in, align 4 store i32 %val, i32 addrspace(1)* %out, align 4 @@ -22,8 +22,8 @@ define void @local_i32_load_0_offset(i32 addrspace(1)* %out, i32 addrspace(3)* % ; BOTH-LABEL: {{^}}local_i8_load_i16_max_offset: ; BOTH-NOT: ADD -; BOTH: DS_READ_U8 [[REG:v[0-9]+]], {{v[0-9]+}} offset:65535 [M0] -; BOTH: BUFFER_STORE_BYTE [[REG]], +; BOTH: ds_read_u8 [[REG:v[0-9]+]], {{v[0-9]+}} offset:65535 [M0] +; BOTH: buffer_store_byte [[REG]], define void @local_i8_load_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind { %gep = getelementptr i8 addrspace(3)* %in, i32 65535 %val = load i8 addrspace(3)* %gep, align 4 @@ -34,11 +34,11 @@ define void @local_i8_load_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3) ; BOTH-LABEL: {{^}}local_i8_load_over_i16_max_offset: ; The LDS offset will be 65536 bytes, which is larger than the size of LDS on ; SI, which is why it is being OR'd with the base pointer. -; SI: S_OR_B32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000 -; CI: S_ADD_I32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000 -; BOTH: V_MOV_B32_e32 [[VREGADDR:v[0-9]+]], [[ADDR]] -; BOTH: DS_READ_U8 [[REG:v[0-9]+]], [[VREGADDR]] [M0] -; BOTH: BUFFER_STORE_BYTE [[REG]], +; SI: s_or_b32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000 +; CI: s_add_i32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000 +; BOTH: v_mov_b32_e32 [[VREGADDR:v[0-9]+]], [[ADDR]] +; BOTH: ds_read_u8 [[REG:v[0-9]+]], [[VREGADDR]] [M0] +; BOTH: buffer_store_byte [[REG]], define void @local_i8_load_over_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind { %gep = getelementptr i8 addrspace(3)* %in, i32 65536 %val = load i8 addrspace(3)* %gep, align 4 @@ -48,8 +48,8 @@ define void @local_i8_load_over_i16_max_offset(i8 addrspace(1)* %out, i8 addrspa ; BOTH-LABEL: {{^}}local_i64_load: ; BOTH-NOT: ADD -; BOTH: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56 [M0] -; BOTH: BUFFER_STORE_DWORDX2 [[REG]], +; BOTH: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56 [M0] +; BOTH: buffer_store_dwordx2 [[REG]], define void @local_i64_load(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind { %gep = getelementptr i64 addrspace(3)* %in, i32 7 %val = load i64 addrspace(3)* %gep, align 8 @@ -58,8 +58,8 @@ define void @local_i64_load(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounw } ; BOTH-LABEL: {{^}}local_i64_load_0_offset -; BOTH: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} [M0] -; BOTH: BUFFER_STORE_DWORDX2 [[REG]], +; BOTH: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} [M0] +; BOTH: buffer_store_dwordx2 [[REG]], define void @local_i64_load_0_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind { %val = load i64 addrspace(3)* %in, align 8 store i64 %val, i64 addrspace(1)* %out, align 8 @@ -68,8 +68,8 @@ define void @local_i64_load_0_offset(i64 addrspace(1)* %out, i64 addrspace(3)* % ; BOTH-LABEL: {{^}}local_f64_load: ; BOTH-NOT: ADD -; BOTH: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56 [M0] -; BOTH: BUFFER_STORE_DWORDX2 [[REG]], +; BOTH: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56 [M0] +; BOTH: buffer_store_dwordx2 [[REG]], define void @local_f64_load(double addrspace(1)* %out, double addrspace(3)* %in) nounwind { %gep = getelementptr double addrspace(3)* %in, i32 7 %val = load double addrspace(3)* %gep, align 8 @@ -78,8 +78,8 @@ define void @local_f64_load(double addrspace(1)* %out, double addrspace(3)* %in) } ; BOTH-LABEL: {{^}}local_f64_load_0_offset -; BOTH: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} [M0] -; BOTH: BUFFER_STORE_DWORDX2 [[REG]], +; BOTH: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} [M0] +; BOTH: buffer_store_dwordx2 [[REG]], define void @local_f64_load_0_offset(double addrspace(1)* %out, double addrspace(3)* %in) nounwind { %val = load double addrspace(3)* %in, align 8 store double %val, double addrspace(1)* %out, align 8 @@ -88,7 +88,7 @@ define void @local_f64_load_0_offset(double addrspace(1)* %out, double addrspace ; BOTH-LABEL: {{^}}local_i64_store: ; BOTH-NOT: ADD -; BOTH: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56 [M0] +; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56 [M0] define void @local_i64_store(i64 addrspace(3)* %out) nounwind { %gep = getelementptr i64 addrspace(3)* %out, i32 7 store i64 5678, i64 addrspace(3)* %gep, align 8 @@ -97,7 +97,7 @@ define void @local_i64_store(i64 addrspace(3)* %out) nounwind { ; BOTH-LABEL: {{^}}local_i64_store_0_offset: ; BOTH-NOT: ADD -; BOTH: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0] +; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0] define void @local_i64_store_0_offset(i64 addrspace(3)* %out) nounwind { store i64 1234, i64 addrspace(3)* %out, align 8 ret void @@ -105,7 +105,7 @@ define void @local_i64_store_0_offset(i64 addrspace(3)* %out) nounwind { ; BOTH-LABEL: {{^}}local_f64_store: ; BOTH-NOT: ADD -; BOTH: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56 [M0] +; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56 [M0] define void @local_f64_store(double addrspace(3)* %out) nounwind { %gep = getelementptr double addrspace(3)* %out, i32 7 store double 16.0, double addrspace(3)* %gep, align 8 @@ -113,7 +113,7 @@ define void @local_f64_store(double addrspace(3)* %out) nounwind { } ; BOTH-LABEL: {{^}}local_f64_store_0_offset -; BOTH: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0] +; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0] define void @local_f64_store_0_offset(double addrspace(3)* %out) nounwind { store double 20.0, double addrspace(3)* %out, align 8 ret void @@ -121,9 +121,9 @@ define void @local_f64_store_0_offset(double addrspace(3)* %out) nounwind { ; BOTH-LABEL: {{^}}local_v2i64_store: ; BOTH-NOT: ADD -; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:112 [M0] -; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:120 [M0] -; BOTH: S_ENDPGM +; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:112 [M0] +; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:120 [M0] +; BOTH: s_endpgm define void @local_v2i64_store(<2 x i64> addrspace(3)* %out) nounwind { %gep = getelementptr <2 x i64> addrspace(3)* %out, i32 7 store <2 x i64> , <2 x i64> addrspace(3)* %gep, align 16 @@ -132,9 +132,9 @@ define void @local_v2i64_store(<2 x i64> addrspace(3)* %out) nounwind { ; BOTH-LABEL: {{^}}local_v2i64_store_0_offset: ; BOTH-NOT: ADD -; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0] -; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8 [M0] -; BOTH: S_ENDPGM +; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0] +; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8 [M0] +; BOTH: s_endpgm define void @local_v2i64_store_0_offset(<2 x i64> addrspace(3)* %out) nounwind { store <2 x i64> , <2 x i64> addrspace(3)* %out, align 16 ret void @@ -142,11 +142,11 @@ define void @local_v2i64_store_0_offset(<2 x i64> addrspace(3)* %out) nounwind { ; BOTH-LABEL: {{^}}local_v4i64_store: ; BOTH-NOT: ADD -; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:224 [M0] -; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:232 [M0] -; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:240 [M0] -; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:248 [M0] -; BOTH: S_ENDPGM +; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:224 [M0] +; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:232 [M0] +; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:240 [M0] +; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:248 [M0] +; BOTH: s_endpgm define void @local_v4i64_store(<4 x i64> addrspace(3)* %out) nounwind { %gep = getelementptr <4 x i64> addrspace(3)* %out, i32 7 store <4 x i64> , <4 x i64> addrspace(3)* %gep, align 16 @@ -155,11 +155,11 @@ define void @local_v4i64_store(<4 x i64> addrspace(3)* %out) nounwind { ; BOTH-LABEL: {{^}}local_v4i64_store_0_offset: ; BOTH-NOT: ADD -; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0] -; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8 [M0] -; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16 [M0] -; BOTH-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24 [M0] -; BOTH: S_ENDPGM +; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0] +; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8 [M0] +; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16 [M0] +; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24 [M0] +; BOTH: s_endpgm define void @local_v4i64_store_0_offset(<4 x i64> addrspace(3)* %out) nounwind { store <4 x i64> , <4 x i64> addrspace(3)* %out, align 16 ret void diff --git a/test/CodeGen/R600/local-atomics.ll b/test/CodeGen/R600/local-atomics.ll index 354566a983f..2ac811f26d8 100644 --- a/test/CodeGen/R600/local-atomics.ll +++ b/test/CodeGen/R600/local-atomics.ll @@ -4,12 +4,12 @@ ; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_i32: ; EG: LDS_WRXCHG_RET * -; SI: S_LOAD_DWORD [[SPTR:s[0-9]+]], -; SI: V_MOV_B32_e32 [[DATA:v[0-9]+]], 4 -; SI: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]] -; SI: DS_WRXCHG_RTN_B32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: s_load_dword [[SPTR:s[0-9]+]], +; SI: v_mov_b32_e32 [[DATA:v[0-9]+]], 4 +; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] +; SI: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm define void @lds_atomic_xchg_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw xchg i32 addrspace(3)* %ptr, i32 4 seq_cst store i32 %result, i32 addrspace(1)* %out, align 4 @@ -18,8 +18,8 @@ define void @lds_atomic_xchg_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* % ; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_i32_offset: ; EG: LDS_WRXCHG_RET * -; SI: DS_WRXCHG_RTN_B32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_wrxchg_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_xchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw xchg i32 addrspace(3)* %gep, i32 4 seq_cst @@ -30,12 +30,12 @@ define void @lds_atomic_xchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspac ; XXX - Is it really necessary to load 4 into VGPR? ; FUNC-LABEL: {{^}}lds_atomic_add_ret_i32: ; EG: LDS_ADD_RET * -; SI: S_LOAD_DWORD [[SPTR:s[0-9]+]], -; SI: V_MOV_B32_e32 [[DATA:v[0-9]+]], 4 -; SI: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]] -; SI: DS_ADD_RTN_U32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: s_load_dword [[SPTR:s[0-9]+]], +; SI: v_mov_b32_e32 [[DATA:v[0-9]+]], 4 +; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] +; SI: ds_add_rtn_u32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm define void @lds_atomic_add_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw add i32 addrspace(3)* %ptr, i32 4 seq_cst store i32 %result, i32 addrspace(1)* %out, align 4 @@ -44,8 +44,8 @@ define void @lds_atomic_add_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %p ; FUNC-LABEL: {{^}}lds_atomic_add_ret_i32_offset: ; EG: LDS_ADD_RET * -; SI: DS_ADD_RTN_U32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_add_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw add i32 addrspace(3)* %gep, i32 4 seq_cst @@ -55,9 +55,9 @@ define void @lds_atomic_add_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace ; FUNC-LABEL: {{^}}lds_atomic_add_ret_i32_bad_si_offset: ; EG: LDS_ADD_RET * -; SI: DS_ADD_RTN_U32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} [M0] -; CI: DS_ADD_RTN_U32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} [M0] +; CI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_add_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind { %sub = sub i32 %a, %b %add = add i32 %sub, 4 @@ -69,10 +69,10 @@ define void @lds_atomic_add_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 ad ; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i32: ; EG: LDS_ADD_RET * -; SI: S_MOV_B32 [[SNEGONE:s[0-9]+]], -1 -; SI: V_MOV_B32_e32 [[NEGONE:v[0-9]+]], [[SNEGONE]] -; SI: DS_INC_RTN_U32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] [M0] -; SI: S_ENDPGM +; SI: s_mov_b32 [[SNEGONE:s[0-9]+]], -1 +; SI: v_mov_b32_e32 [[NEGONE:v[0-9]+]], [[SNEGONE]] +; SI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] [M0] +; SI: s_endpgm define void @lds_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw add i32 addrspace(3)* %ptr, i32 1 seq_cst store i32 %result, i32 addrspace(1)* %out, align 4 @@ -81,10 +81,10 @@ define void @lds_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %p ; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i32_offset: ; EG: LDS_ADD_RET * -; SI: S_MOV_B32 [[SNEGONE:s[0-9]+]], -1 -; SI: V_MOV_B32_e32 [[NEGONE:v[0-9]+]], [[SNEGONE]] -; SI: DS_INC_RTN_U32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] offset:16 -; SI: S_ENDPGM +; SI: s_mov_b32 [[SNEGONE:s[0-9]+]], -1 +; SI: v_mov_b32_e32 [[NEGONE:v[0-9]+]], [[SNEGONE]] +; SI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] offset:16 +; SI: s_endpgm define void @lds_atomic_inc_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw add i32 addrspace(3)* %gep, i32 1 seq_cst @@ -94,9 +94,9 @@ define void @lds_atomic_inc_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace ; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i32_bad_si_offset: ; EG: LDS_ADD_RET * -; SI: DS_INC_RTN_U32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} [M0] -; CI: DS_INC_RTN_U32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} [M0] +; CI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_inc_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind { %sub = sub i32 %a, %b %add = add i32 %sub, 4 @@ -108,8 +108,8 @@ define void @lds_atomic_inc_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 ad ; FUNC-LABEL: {{^}}lds_atomic_sub_ret_i32: ; EG: LDS_SUB_RET * -; SI: DS_SUB_RTN_U32 -; SI: S_ENDPGM +; SI: ds_sub_rtn_u32 +; SI: s_endpgm define void @lds_atomic_sub_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw sub i32 addrspace(3)* %ptr, i32 4 seq_cst store i32 %result, i32 addrspace(1)* %out, align 4 @@ -118,8 +118,8 @@ define void @lds_atomic_sub_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %p ; FUNC-LABEL: {{^}}lds_atomic_sub_ret_i32_offset: ; EG: LDS_SUB_RET * -; SI: DS_SUB_RTN_U32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_sub_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw sub i32 addrspace(3)* %gep, i32 4 seq_cst @@ -129,10 +129,10 @@ define void @lds_atomic_sub_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace ; FUNC-LABEL: {{^}}lds_atomic_dec_ret_i32: ; EG: LDS_SUB_RET * -; SI: S_MOV_B32 [[SNEGONE:s[0-9]+]], -1 -; SI: V_MOV_B32_e32 [[NEGONE:v[0-9]+]], [[SNEGONE]] -; SI: DS_DEC_RTN_U32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] [M0] -; SI: S_ENDPGM +; SI: s_mov_b32 [[SNEGONE:s[0-9]+]], -1 +; SI: v_mov_b32_e32 [[NEGONE:v[0-9]+]], [[SNEGONE]] +; SI: ds_dec_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] [M0] +; SI: s_endpgm define void @lds_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw sub i32 addrspace(3)* %ptr, i32 1 seq_cst store i32 %result, i32 addrspace(1)* %out, align 4 @@ -141,10 +141,10 @@ define void @lds_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %p ; FUNC-LABEL: {{^}}lds_atomic_dec_ret_i32_offset: ; EG: LDS_SUB_RET * -; SI: S_MOV_B32 [[SNEGONE:s[0-9]+]], -1 -; SI: V_MOV_B32_e32 [[NEGONE:v[0-9]+]], [[SNEGONE]] -; SI: DS_DEC_RTN_U32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] offset:16 -; SI: S_ENDPGM +; SI: s_mov_b32 [[SNEGONE:s[0-9]+]], -1 +; SI: v_mov_b32_e32 [[NEGONE:v[0-9]+]], [[SNEGONE]] +; SI: ds_dec_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] offset:16 +; SI: s_endpgm define void @lds_atomic_dec_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw sub i32 addrspace(3)* %gep, i32 1 seq_cst @@ -154,8 +154,8 @@ define void @lds_atomic_dec_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace ; FUNC-LABEL: {{^}}lds_atomic_and_ret_i32: ; EG: LDS_AND_RET * -; SI: DS_AND_RTN_B32 -; SI: S_ENDPGM +; SI: ds_and_rtn_b32 +; SI: s_endpgm define void @lds_atomic_and_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw and i32 addrspace(3)* %ptr, i32 4 seq_cst store i32 %result, i32 addrspace(1)* %out, align 4 @@ -164,8 +164,8 @@ define void @lds_atomic_and_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %p ; FUNC-LABEL: {{^}}lds_atomic_and_ret_i32_offset: ; EG: LDS_AND_RET * -; SI: DS_AND_RTN_B32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_and_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_and_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw and i32 addrspace(3)* %gep, i32 4 seq_cst @@ -175,8 +175,8 @@ define void @lds_atomic_and_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace ; FUNC-LABEL: {{^}}lds_atomic_or_ret_i32: ; EG: LDS_OR_RET * -; SI: DS_OR_RTN_B32 -; SI: S_ENDPGM +; SI: ds_or_rtn_b32 +; SI: s_endpgm define void @lds_atomic_or_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw or i32 addrspace(3)* %ptr, i32 4 seq_cst store i32 %result, i32 addrspace(1)* %out, align 4 @@ -185,8 +185,8 @@ define void @lds_atomic_or_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %pt ; FUNC-LABEL: {{^}}lds_atomic_or_ret_i32_offset: ; EG: LDS_OR_RET * -; SI: DS_OR_RTN_B32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_or_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_or_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw or i32 addrspace(3)* %gep, i32 4 seq_cst @@ -196,8 +196,8 @@ define void @lds_atomic_or_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace( ; FUNC-LABEL: {{^}}lds_atomic_xor_ret_i32: ; EG: LDS_XOR_RET * -; SI: DS_XOR_RTN_B32 -; SI: S_ENDPGM +; SI: ds_xor_rtn_b32 +; SI: s_endpgm define void @lds_atomic_xor_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw xor i32 addrspace(3)* %ptr, i32 4 seq_cst store i32 %result, i32 addrspace(1)* %out, align 4 @@ -206,8 +206,8 @@ define void @lds_atomic_xor_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %p ; FUNC-LABEL: {{^}}lds_atomic_xor_ret_i32_offset: ; EG: LDS_XOR_RET * -; SI: DS_XOR_RTN_B32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_xor_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_xor_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw xor i32 addrspace(3)* %gep, i32 4 seq_cst @@ -225,8 +225,8 @@ define void @lds_atomic_xor_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace ; FUNC-LABEL: {{^}}lds_atomic_min_ret_i32: ; EG: LDS_MIN_INT_RET * -; SI: DS_MIN_RTN_I32 -; SI: S_ENDPGM +; SI: ds_min_rtn_i32 +; SI: s_endpgm define void @lds_atomic_min_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw min i32 addrspace(3)* %ptr, i32 4 seq_cst store i32 %result, i32 addrspace(1)* %out, align 4 @@ -235,8 +235,8 @@ define void @lds_atomic_min_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %p ; FUNC-LABEL: {{^}}lds_atomic_min_ret_i32_offset: ; EG: LDS_MIN_INT_RET * -; SI: DS_MIN_RTN_I32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_min_rtn_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_min_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw min i32 addrspace(3)* %gep, i32 4 seq_cst @@ -246,8 +246,8 @@ define void @lds_atomic_min_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace ; FUNC-LABEL: {{^}}lds_atomic_max_ret_i32: ; EG: LDS_MAX_INT_RET * -; SI: DS_MAX_RTN_I32 -; SI: S_ENDPGM +; SI: ds_max_rtn_i32 +; SI: s_endpgm define void @lds_atomic_max_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw max i32 addrspace(3)* %ptr, i32 4 seq_cst store i32 %result, i32 addrspace(1)* %out, align 4 @@ -256,8 +256,8 @@ define void @lds_atomic_max_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %p ; FUNC-LABEL: {{^}}lds_atomic_max_ret_i32_offset: ; EG: LDS_MAX_INT_RET * -; SI: DS_MAX_RTN_I32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_max_rtn_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_max_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw max i32 addrspace(3)* %gep, i32 4 seq_cst @@ -267,8 +267,8 @@ define void @lds_atomic_max_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace ; FUNC-LABEL: {{^}}lds_atomic_umin_ret_i32: ; EG: LDS_MIN_UINT_RET * -; SI: DS_MIN_RTN_U32 -; SI: S_ENDPGM +; SI: ds_min_rtn_u32 +; SI: s_endpgm define void @lds_atomic_umin_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw umin i32 addrspace(3)* %ptr, i32 4 seq_cst store i32 %result, i32 addrspace(1)* %out, align 4 @@ -277,8 +277,8 @@ define void @lds_atomic_umin_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* % ; FUNC-LABEL: {{^}}lds_atomic_umin_ret_i32_offset: ; EG: LDS_MIN_UINT_RET * -; SI: DS_MIN_RTN_U32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_min_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_umin_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw umin i32 addrspace(3)* %gep, i32 4 seq_cst @@ -288,8 +288,8 @@ define void @lds_atomic_umin_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspac ; FUNC-LABEL: {{^}}lds_atomic_umax_ret_i32: ; EG: LDS_MAX_UINT_RET * -; SI: DS_MAX_RTN_U32 -; SI: S_ENDPGM +; SI: ds_max_rtn_u32 +; SI: s_endpgm define void @lds_atomic_umax_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw umax i32 addrspace(3)* %ptr, i32 4 seq_cst store i32 %result, i32 addrspace(1)* %out, align 4 @@ -298,8 +298,8 @@ define void @lds_atomic_umax_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* % ; FUNC-LABEL: {{^}}lds_atomic_umax_ret_i32_offset: ; EG: LDS_MAX_UINT_RET * -; SI: DS_MAX_RTN_U32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_max_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_umax_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw umax i32 addrspace(3)* %gep, i32 4 seq_cst @@ -308,19 +308,19 @@ define void @lds_atomic_umax_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspac } ; FUNC-LABEL: {{^}}lds_atomic_xchg_noret_i32: -; SI: S_LOAD_DWORD [[SPTR:s[0-9]+]], -; SI: V_MOV_B32_e32 [[DATA:v[0-9]+]], 4 -; SI: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]] -; SI: DS_WRXCHG_RTN_B32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0] -; SI: S_ENDPGM +; SI: s_load_dword [[SPTR:s[0-9]+]], +; SI: v_mov_b32_e32 [[DATA:v[0-9]+]], 4 +; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] +; SI: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0] +; SI: s_endpgm define void @lds_atomic_xchg_noret_i32(i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw xchg i32 addrspace(3)* %ptr, i32 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_xchg_noret_i32_offset: -; SI: DS_WRXCHG_RTN_B32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_wrxchg_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_xchg_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw xchg i32 addrspace(3)* %gep, i32 4 seq_cst @@ -329,19 +329,19 @@ define void @lds_atomic_xchg_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { ; XXX - Is it really necessary to load 4 into VGPR? ; FUNC-LABEL: {{^}}lds_atomic_add_noret_i32: -; SI: S_LOAD_DWORD [[SPTR:s[0-9]+]], -; SI: V_MOV_B32_e32 [[DATA:v[0-9]+]], 4 -; SI: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]] -; SI: DS_ADD_U32 [[VPTR]], [[DATA]] [M0] -; SI: S_ENDPGM +; SI: s_load_dword [[SPTR:s[0-9]+]], +; SI: v_mov_b32_e32 [[DATA:v[0-9]+]], 4 +; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] +; SI: ds_add_u32 [[VPTR]], [[DATA]] [M0] +; SI: s_endpgm define void @lds_atomic_add_noret_i32(i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw add i32 addrspace(3)* %ptr, i32 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_add_noret_i32_offset: -; SI: DS_ADD_U32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_add_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw add i32 addrspace(3)* %gep, i32 4 seq_cst @@ -349,9 +349,9 @@ define void @lds_atomic_add_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_add_noret_i32_bad_si_offset -; SI: DS_ADD_U32 v{{[0-9]+}}, v{{[0-9]+}} [M0] -; CI: DS_ADD_U32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 [M0] -; SI: S_ENDPGM +; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} [M0] +; CI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 [M0] +; SI: s_endpgm define void @lds_atomic_add_noret_i32_bad_si_offset(i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind { %sub = sub i32 %a, %b %add = add i32 %sub, 4 @@ -361,20 +361,20 @@ define void @lds_atomic_add_noret_i32_bad_si_offset(i32 addrspace(3)* %ptr, i32 } ; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i32: -; SI: S_MOV_B32 [[SNEGONE:s[0-9]+]], -1 -; SI: V_MOV_B32_e32 [[NEGONE:v[0-9]+]], [[SNEGONE]] -; SI: DS_INC_U32 v{{[0-9]+}}, [[NEGONE]] [M0] -; SI: S_ENDPGM +; SI: s_mov_b32 [[SNEGONE:s[0-9]+]], -1 +; SI: v_mov_b32_e32 [[NEGONE:v[0-9]+]], [[SNEGONE]] +; SI: ds_inc_u32 v{{[0-9]+}}, [[NEGONE]] [M0] +; SI: s_endpgm define void @lds_atomic_inc_noret_i32(i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw add i32 addrspace(3)* %ptr, i32 1 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i32_offset: -; SI: S_MOV_B32 [[SNEGONE:s[0-9]+]], -1 -; SI: V_MOV_B32_e32 [[NEGONE:v[0-9]+]], [[SNEGONE]] -; SI: DS_INC_U32 v{{[0-9]+}}, [[NEGONE]] offset:16 -; SI: S_ENDPGM +; SI: s_mov_b32 [[SNEGONE:s[0-9]+]], -1 +; SI: v_mov_b32_e32 [[NEGONE:v[0-9]+]], [[SNEGONE]] +; SI: ds_inc_u32 v{{[0-9]+}}, [[NEGONE]] offset:16 +; SI: s_endpgm define void @lds_atomic_inc_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw add i32 addrspace(3)* %gep, i32 1 seq_cst @@ -382,9 +382,9 @@ define void @lds_atomic_inc_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i32_bad_si_offset: -; SI: DS_INC_U32 v{{[0-9]+}}, v{{[0-9]+}} -; CI: DS_INC_U32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_inc_u32 v{{[0-9]+}}, v{{[0-9]+}} +; CI: ds_inc_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_inc_noret_i32_bad_si_offset(i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind { %sub = sub i32 %a, %b %add = add i32 %sub, 4 @@ -394,16 +394,16 @@ define void @lds_atomic_inc_noret_i32_bad_si_offset(i32 addrspace(3)* %ptr, i32 } ; FUNC-LABEL: {{^}}lds_atomic_sub_noret_i32: -; SI: DS_SUB_U32 -; SI: S_ENDPGM +; SI: ds_sub_u32 +; SI: s_endpgm define void @lds_atomic_sub_noret_i32(i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw sub i32 addrspace(3)* %ptr, i32 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_sub_noret_i32_offset: -; SI: DS_SUB_U32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_sub_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_sub_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw sub i32 addrspace(3)* %gep, i32 4 seq_cst @@ -411,20 +411,20 @@ define void @lds_atomic_sub_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_dec_noret_i32: -; SI: S_MOV_B32 [[SNEGONE:s[0-9]+]], -1 -; SI: V_MOV_B32_e32 [[NEGONE:v[0-9]+]], [[SNEGONE]] -; SI: DS_DEC_U32 v{{[0-9]+}}, [[NEGONE]] -; SI: S_ENDPGM +; SI: s_mov_b32 [[SNEGONE:s[0-9]+]], -1 +; SI: v_mov_b32_e32 [[NEGONE:v[0-9]+]], [[SNEGONE]] +; SI: ds_dec_u32 v{{[0-9]+}}, [[NEGONE]] +; SI: s_endpgm define void @lds_atomic_dec_noret_i32(i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw sub i32 addrspace(3)* %ptr, i32 1 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_dec_noret_i32_offset: -; SI: S_MOV_B32 [[SNEGONE:s[0-9]+]], -1 -; SI: V_MOV_B32_e32 [[NEGONE:v[0-9]+]], [[SNEGONE]] -; SI: DS_DEC_U32 v{{[0-9]+}}, [[NEGONE]] offset:16 -; SI: S_ENDPGM +; SI: s_mov_b32 [[SNEGONE:s[0-9]+]], -1 +; SI: v_mov_b32_e32 [[NEGONE:v[0-9]+]], [[SNEGONE]] +; SI: ds_dec_u32 v{{[0-9]+}}, [[NEGONE]] offset:16 +; SI: s_endpgm define void @lds_atomic_dec_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw sub i32 addrspace(3)* %gep, i32 1 seq_cst @@ -432,16 +432,16 @@ define void @lds_atomic_dec_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_and_noret_i32: -; SI: DS_AND_B32 -; SI: S_ENDPGM +; SI: ds_and_b32 +; SI: s_endpgm define void @lds_atomic_and_noret_i32(i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw and i32 addrspace(3)* %ptr, i32 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_and_noret_i32_offset: -; SI: DS_AND_B32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_and_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_and_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw and i32 addrspace(3)* %gep, i32 4 seq_cst @@ -449,16 +449,16 @@ define void @lds_atomic_and_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_or_noret_i32: -; SI: DS_OR_B32 -; SI: S_ENDPGM +; SI: ds_or_b32 +; SI: s_endpgm define void @lds_atomic_or_noret_i32(i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw or i32 addrspace(3)* %ptr, i32 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_or_noret_i32_offset: -; SI: DS_OR_B32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_or_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_or_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw or i32 addrspace(3)* %gep, i32 4 seq_cst @@ -466,16 +466,16 @@ define void @lds_atomic_or_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_xor_noret_i32: -; SI: DS_XOR_B32 -; SI: S_ENDPGM +; SI: ds_xor_b32 +; SI: s_endpgm define void @lds_atomic_xor_noret_i32(i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw xor i32 addrspace(3)* %ptr, i32 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_xor_noret_i32_offset: -; SI: DS_XOR_B32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_xor_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_xor_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw xor i32 addrspace(3)* %gep, i32 4 seq_cst @@ -490,16 +490,16 @@ define void @lds_atomic_xor_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { ; } ; FUNC-LABEL: {{^}}lds_atomic_min_noret_i32: -; SI: DS_MIN_I32 -; SI: S_ENDPGM +; SI: ds_min_i32 +; SI: s_endpgm define void @lds_atomic_min_noret_i32(i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw min i32 addrspace(3)* %ptr, i32 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_min_noret_i32_offset: -; SI: DS_MIN_I32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_min_i32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_min_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw min i32 addrspace(3)* %gep, i32 4 seq_cst @@ -507,16 +507,16 @@ define void @lds_atomic_min_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_max_noret_i32: -; SI: DS_MAX_I32 -; SI: S_ENDPGM +; SI: ds_max_i32 +; SI: s_endpgm define void @lds_atomic_max_noret_i32(i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw max i32 addrspace(3)* %ptr, i32 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_max_noret_i32_offset: -; SI: DS_MAX_I32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_max_i32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_max_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw max i32 addrspace(3)* %gep, i32 4 seq_cst @@ -524,16 +524,16 @@ define void @lds_atomic_max_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_umin_noret_i32: -; SI: DS_MIN_U32 -; SI: S_ENDPGM +; SI: ds_min_u32 +; SI: s_endpgm define void @lds_atomic_umin_noret_i32(i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw umin i32 addrspace(3)* %ptr, i32 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_umin_noret_i32_offset: -; SI: DS_MIN_U32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_min_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_umin_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw umin i32 addrspace(3)* %gep, i32 4 seq_cst @@ -541,16 +541,16 @@ define void @lds_atomic_umin_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_umax_noret_i32: -; SI: DS_MAX_U32 -; SI: S_ENDPGM +; SI: ds_max_u32 +; SI: s_endpgm define void @lds_atomic_umax_noret_i32(i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw umax i32 addrspace(3)* %ptr, i32 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_umax_noret_i32_offset: -; SI: DS_MAX_U32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 -; SI: S_ENDPGM +; SI: ds_max_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: s_endpgm define void @lds_atomic_umax_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw umax i32 addrspace(3)* %gep, i32 4 seq_cst diff --git a/test/CodeGen/R600/local-atomics64.ll b/test/CodeGen/R600/local-atomics64.ll index 0870d6e1bca..ce0cf598bb3 100644 --- a/test/CodeGen/R600/local-atomics64.ll +++ b/test/CodeGen/R600/local-atomics64.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s ; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_i64: -; SI: DS_WRXCHG_RTN_B64 -; SI: S_ENDPGM +; SI: ds_wrxchg_rtn_b64 +; SI: s_endpgm define void @lds_atomic_xchg_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw xchg i64 addrspace(3)* %ptr, i64 4 seq_cst store i64 %result, i64 addrspace(1)* %out, align 8 @@ -10,8 +10,8 @@ define void @lds_atomic_xchg_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* % } ; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_i64_offset: -; SI: DS_WRXCHG_RTN_B64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_wrxchg_rtn_b64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_xchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw xchg i64 addrspace(3)* %gep, i64 4 seq_cst @@ -20,8 +20,8 @@ define void @lds_atomic_xchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspac } ; FUNC-LABEL: {{^}}lds_atomic_add_ret_i64: -; SI: DS_ADD_RTN_U64 -; SI: S_ENDPGM +; SI: ds_add_rtn_u64 +; SI: s_endpgm define void @lds_atomic_add_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw add i64 addrspace(3)* %ptr, i64 4 seq_cst store i64 %result, i64 addrspace(1)* %out, align 8 @@ -29,14 +29,14 @@ define void @lds_atomic_add_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p } ; FUNC-LABEL: {{^}}lds_atomic_add_ret_i64_offset: -; SI: S_LOAD_DWORD [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI: S_MOV_B64 s{{\[}}[[LOSDATA:[0-9]+]]:[[HISDATA:[0-9]+]]{{\]}}, 9 -; SI-DAG: V_MOV_B32_e32 v[[LOVDATA:[0-9]+]], s[[LOSDATA]] -; SI-DAG: V_MOV_B32_e32 v[[HIVDATA:[0-9]+]], s[[HISDATA]] -; SI-DAG: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[PTR]] -; SI: DS_ADD_RTN_U64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32 [M0] -; SI: BUFFER_STORE_DWORDX2 [[RESULT]], -; SI: S_ENDPGM +; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI: s_mov_b64 s{{\[}}[[LOSDATA:[0-9]+]]:[[HISDATA:[0-9]+]]{{\]}}, 9 +; SI-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], s[[LOSDATA]] +; SI-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], s[[HISDATA]] +; SI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] +; SI: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32 [M0] +; SI: buffer_store_dwordx2 [[RESULT]], +; SI: s_endpgm define void @lds_atomic_add_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i64 4 %result = atomicrmw add i64 addrspace(3)* %gep, i64 9 seq_cst @@ -45,12 +45,12 @@ define void @lds_atomic_add_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace } ; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i64: -; SI: S_MOV_B64 s{{\[}}[[LOSDATA:[0-9]+]]:[[HISDATA:[0-9]+]]{{\]}}, -1 -; SI-DAG: V_MOV_B32_e32 v[[LOVDATA:[0-9]+]], s[[LOSDATA]] -; SI-DAG: V_MOV_B32_e32 v[[HIVDATA:[0-9]+]], s[[HISDATA]] -; SI: DS_INC_RTN_U64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} -; SI: BUFFER_STORE_DWORDX2 [[RESULT]], -; SI: S_ENDPGM +; SI: s_mov_b64 s{{\[}}[[LOSDATA:[0-9]+]]:[[HISDATA:[0-9]+]]{{\]}}, -1 +; SI-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], s[[LOSDATA]] +; SI-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], s[[HISDATA]] +; SI: ds_inc_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} +; SI: buffer_store_dwordx2 [[RESULT]], +; SI: s_endpgm define void @lds_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw add i64 addrspace(3)* %ptr, i64 1 seq_cst store i64 %result, i64 addrspace(1)* %out, align 8 @@ -58,8 +58,8 @@ define void @lds_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p } ; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i64_offset: -; SI: DS_INC_RTN_U64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_inc_rtn_u64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw add i64 addrspace(3)* %gep, i64 1 seq_cst @@ -68,8 +68,8 @@ define void @lds_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace } ; FUNC-LABEL: {{^}}lds_atomic_sub_ret_i64: -; SI: DS_SUB_RTN_U64 -; SI: S_ENDPGM +; SI: ds_sub_rtn_u64 +; SI: s_endpgm define void @lds_atomic_sub_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw sub i64 addrspace(3)* %ptr, i64 4 seq_cst store i64 %result, i64 addrspace(1)* %out, align 8 @@ -77,8 +77,8 @@ define void @lds_atomic_sub_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p } ; FUNC-LABEL: {{^}}lds_atomic_sub_ret_i64_offset: -; SI: DS_SUB_RTN_U64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_sub_rtn_u64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_sub_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw sub i64 addrspace(3)* %gep, i64 4 seq_cst @@ -87,12 +87,12 @@ define void @lds_atomic_sub_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace } ; FUNC-LABEL: {{^}}lds_atomic_dec_ret_i64: -; SI: S_MOV_B64 s{{\[}}[[LOSDATA:[0-9]+]]:[[HISDATA:[0-9]+]]{{\]}}, -1 -; SI-DAG: V_MOV_B32_e32 v[[LOVDATA:[0-9]+]], s[[LOSDATA]] -; SI-DAG: V_MOV_B32_e32 v[[HIVDATA:[0-9]+]], s[[HISDATA]] -; SI: DS_DEC_RTN_U64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} -; SI: BUFFER_STORE_DWORDX2 [[RESULT]], -; SI: S_ENDPGM +; SI: s_mov_b64 s{{\[}}[[LOSDATA:[0-9]+]]:[[HISDATA:[0-9]+]]{{\]}}, -1 +; SI-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], s[[LOSDATA]] +; SI-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], s[[HISDATA]] +; SI: ds_dec_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} +; SI: buffer_store_dwordx2 [[RESULT]], +; SI: s_endpgm define void @lds_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw sub i64 addrspace(3)* %ptr, i64 1 seq_cst store i64 %result, i64 addrspace(1)* %out, align 8 @@ -100,8 +100,8 @@ define void @lds_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p } ; FUNC-LABEL: {{^}}lds_atomic_dec_ret_i64_offset: -; SI: DS_DEC_RTN_U64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_dec_rtn_u64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_dec_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw sub i64 addrspace(3)* %gep, i64 1 seq_cst @@ -110,8 +110,8 @@ define void @lds_atomic_dec_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace } ; FUNC-LABEL: {{^}}lds_atomic_and_ret_i64: -; SI: DS_AND_RTN_B64 -; SI: S_ENDPGM +; SI: ds_and_rtn_b64 +; SI: s_endpgm define void @lds_atomic_and_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw and i64 addrspace(3)* %ptr, i64 4 seq_cst store i64 %result, i64 addrspace(1)* %out, align 8 @@ -119,8 +119,8 @@ define void @lds_atomic_and_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p } ; FUNC-LABEL: {{^}}lds_atomic_and_ret_i64_offset: -; SI: DS_AND_RTN_B64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_and_rtn_b64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_and_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw and i64 addrspace(3)* %gep, i64 4 seq_cst @@ -129,8 +129,8 @@ define void @lds_atomic_and_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace } ; FUNC-LABEL: {{^}}lds_atomic_or_ret_i64: -; SI: DS_OR_RTN_B64 -; SI: S_ENDPGM +; SI: ds_or_rtn_b64 +; SI: s_endpgm define void @lds_atomic_or_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw or i64 addrspace(3)* %ptr, i64 4 seq_cst store i64 %result, i64 addrspace(1)* %out, align 8 @@ -138,8 +138,8 @@ define void @lds_atomic_or_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %pt } ; FUNC-LABEL: {{^}}lds_atomic_or_ret_i64_offset: -; SI: DS_OR_RTN_B64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_or_rtn_b64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_or_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw or i64 addrspace(3)* %gep, i64 4 seq_cst @@ -148,8 +148,8 @@ define void @lds_atomic_or_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace( } ; FUNC-LABEL: {{^}}lds_atomic_xor_ret_i64: -; SI: DS_XOR_RTN_B64 -; SI: S_ENDPGM +; SI: ds_xor_rtn_b64 +; SI: s_endpgm define void @lds_atomic_xor_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw xor i64 addrspace(3)* %ptr, i64 4 seq_cst store i64 %result, i64 addrspace(1)* %out, align 8 @@ -157,8 +157,8 @@ define void @lds_atomic_xor_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p } ; FUNC-LABEL: {{^}}lds_atomic_xor_ret_i64_offset: -; SI: DS_XOR_RTN_B64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_xor_rtn_b64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_xor_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw xor i64 addrspace(3)* %gep, i64 4 seq_cst @@ -175,8 +175,8 @@ define void @lds_atomic_xor_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace ; } ; FUNC-LABEL: {{^}}lds_atomic_min_ret_i64: -; SI: DS_MIN_RTN_I64 -; SI: S_ENDPGM +; SI: ds_min_rtn_i64 +; SI: s_endpgm define void @lds_atomic_min_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw min i64 addrspace(3)* %ptr, i64 4 seq_cst store i64 %result, i64 addrspace(1)* %out, align 8 @@ -184,8 +184,8 @@ define void @lds_atomic_min_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p } ; FUNC-LABEL: {{^}}lds_atomic_min_ret_i64_offset: -; SI: DS_MIN_RTN_I64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_min_rtn_i64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_min_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw min i64 addrspace(3)* %gep, i64 4 seq_cst @@ -194,8 +194,8 @@ define void @lds_atomic_min_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace } ; FUNC-LABEL: {{^}}lds_atomic_max_ret_i64: -; SI: DS_MAX_RTN_I64 -; SI: S_ENDPGM +; SI: ds_max_rtn_i64 +; SI: s_endpgm define void @lds_atomic_max_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw max i64 addrspace(3)* %ptr, i64 4 seq_cst store i64 %result, i64 addrspace(1)* %out, align 8 @@ -203,8 +203,8 @@ define void @lds_atomic_max_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p } ; FUNC-LABEL: {{^}}lds_atomic_max_ret_i64_offset: -; SI: DS_MAX_RTN_I64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_max_rtn_i64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_max_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw max i64 addrspace(3)* %gep, i64 4 seq_cst @@ -213,8 +213,8 @@ define void @lds_atomic_max_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace } ; FUNC-LABEL: {{^}}lds_atomic_umin_ret_i64: -; SI: DS_MIN_RTN_U64 -; SI: S_ENDPGM +; SI: ds_min_rtn_u64 +; SI: s_endpgm define void @lds_atomic_umin_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw umin i64 addrspace(3)* %ptr, i64 4 seq_cst store i64 %result, i64 addrspace(1)* %out, align 8 @@ -222,8 +222,8 @@ define void @lds_atomic_umin_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* % } ; FUNC-LABEL: {{^}}lds_atomic_umin_ret_i64_offset: -; SI: DS_MIN_RTN_U64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_min_rtn_u64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_umin_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw umin i64 addrspace(3)* %gep, i64 4 seq_cst @@ -232,8 +232,8 @@ define void @lds_atomic_umin_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspac } ; FUNC-LABEL: {{^}}lds_atomic_umax_ret_i64: -; SI: DS_MAX_RTN_U64 -; SI: S_ENDPGM +; SI: ds_max_rtn_u64 +; SI: s_endpgm define void @lds_atomic_umax_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw umax i64 addrspace(3)* %ptr, i64 4 seq_cst store i64 %result, i64 addrspace(1)* %out, align 8 @@ -241,8 +241,8 @@ define void @lds_atomic_umax_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* % } ; FUNC-LABEL: {{^}}lds_atomic_umax_ret_i64_offset: -; SI: DS_MAX_RTN_U64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_max_rtn_u64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_umax_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw umax i64 addrspace(3)* %gep, i64 4 seq_cst @@ -251,16 +251,16 @@ define void @lds_atomic_umax_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspac } ; FUNC-LABEL: {{^}}lds_atomic_xchg_noret_i64: -; SI: DS_WRXCHG_RTN_B64 -; SI: S_ENDPGM +; SI: ds_wrxchg_rtn_b64 +; SI: s_endpgm define void @lds_atomic_xchg_noret_i64(i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw xchg i64 addrspace(3)* %ptr, i64 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_xchg_noret_i64_offset: -; SI: DS_WRXCHG_RTN_B64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_wrxchg_rtn_b64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_xchg_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw xchg i64 addrspace(3)* %gep, i64 4 seq_cst @@ -268,21 +268,21 @@ define void @lds_atomic_xchg_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_add_noret_i64: -; SI: DS_ADD_U64 -; SI: S_ENDPGM +; SI: ds_add_u64 +; SI: s_endpgm define void @lds_atomic_add_noret_i64(i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw add i64 addrspace(3)* %ptr, i64 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_add_noret_i64_offset: -; SI: S_LOAD_DWORD [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9 -; SI: S_MOV_B64 s{{\[}}[[LOSDATA:[0-9]+]]:[[HISDATA:[0-9]+]]{{\]}}, 9 -; SI-DAG: V_MOV_B32_e32 v[[LOVDATA:[0-9]+]], s[[LOSDATA]] -; SI-DAG: V_MOV_B32_e32 v[[HIVDATA:[0-9]+]], s[[HISDATA]] -; SI-DAG: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[PTR]] -; SI: DS_ADD_U64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32 [M0] -; SI: S_ENDPGM +; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9 +; SI: s_mov_b64 s{{\[}}[[LOSDATA:[0-9]+]]:[[HISDATA:[0-9]+]]{{\]}}, 9 +; SI-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], s[[LOSDATA]] +; SI-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], s[[HISDATA]] +; SI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] +; SI: ds_add_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32 [M0] +; SI: s_endpgm define void @lds_atomic_add_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i64 4 %result = atomicrmw add i64 addrspace(3)* %gep, i64 9 seq_cst @@ -290,19 +290,19 @@ define void @lds_atomic_add_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i64: -; SI: S_MOV_B64 s{{\[}}[[LOSDATA:[0-9]+]]:[[HISDATA:[0-9]+]]{{\]}}, -1 -; SI-DAG: V_MOV_B32_e32 v[[LOVDATA:[0-9]+]], s[[LOSDATA]] -; SI-DAG: V_MOV_B32_e32 v[[HIVDATA:[0-9]+]], s[[HISDATA]] -; SI: DS_INC_U64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} -; SI: S_ENDPGM +; SI: s_mov_b64 s{{\[}}[[LOSDATA:[0-9]+]]:[[HISDATA:[0-9]+]]{{\]}}, -1 +; SI-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], s[[LOSDATA]] +; SI-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], s[[HISDATA]] +; SI: ds_inc_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} +; SI: s_endpgm define void @lds_atomic_inc_noret_i64(i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw add i64 addrspace(3)* %ptr, i64 1 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i64_offset: -; SI: DS_INC_U64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_inc_u64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_inc_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw add i64 addrspace(3)* %gep, i64 1 seq_cst @@ -310,16 +310,16 @@ define void @lds_atomic_inc_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_sub_noret_i64: -; SI: DS_SUB_U64 -; SI: S_ENDPGM +; SI: ds_sub_u64 +; SI: s_endpgm define void @lds_atomic_sub_noret_i64(i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw sub i64 addrspace(3)* %ptr, i64 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_sub_noret_i64_offset: -; SI: DS_SUB_U64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_sub_u64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_sub_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw sub i64 addrspace(3)* %gep, i64 4 seq_cst @@ -327,19 +327,19 @@ define void @lds_atomic_sub_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_dec_noret_i64: -; SI: S_MOV_B64 s{{\[}}[[LOSDATA:[0-9]+]]:[[HISDATA:[0-9]+]]{{\]}}, -1 -; SI-DAG: V_MOV_B32_e32 v[[LOVDATA:[0-9]+]], s[[LOSDATA]] -; SI-DAG: V_MOV_B32_e32 v[[HIVDATA:[0-9]+]], s[[HISDATA]] -; SI: DS_DEC_U64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} -; SI: S_ENDPGM +; SI: s_mov_b64 s{{\[}}[[LOSDATA:[0-9]+]]:[[HISDATA:[0-9]+]]{{\]}}, -1 +; SI-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], s[[LOSDATA]] +; SI-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], s[[HISDATA]] +; SI: ds_dec_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} +; SI: s_endpgm define void @lds_atomic_dec_noret_i64(i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw sub i64 addrspace(3)* %ptr, i64 1 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_dec_noret_i64_offset: -; SI: DS_DEC_U64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_dec_u64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_dec_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw sub i64 addrspace(3)* %gep, i64 1 seq_cst @@ -347,16 +347,16 @@ define void @lds_atomic_dec_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_and_noret_i64: -; SI: DS_AND_B64 -; SI: S_ENDPGM +; SI: ds_and_b64 +; SI: s_endpgm define void @lds_atomic_and_noret_i64(i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw and i64 addrspace(3)* %ptr, i64 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_and_noret_i64_offset: -; SI: DS_AND_B64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_and_b64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_and_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw and i64 addrspace(3)* %gep, i64 4 seq_cst @@ -364,16 +364,16 @@ define void @lds_atomic_and_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_or_noret_i64: -; SI: DS_OR_B64 -; SI: S_ENDPGM +; SI: ds_or_b64 +; SI: s_endpgm define void @lds_atomic_or_noret_i64(i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw or i64 addrspace(3)* %ptr, i64 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_or_noret_i64_offset: -; SI: DS_OR_B64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_or_b64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_or_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw or i64 addrspace(3)* %gep, i64 4 seq_cst @@ -381,16 +381,16 @@ define void @lds_atomic_or_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_xor_noret_i64: -; SI: DS_XOR_B64 -; SI: S_ENDPGM +; SI: ds_xor_b64 +; SI: s_endpgm define void @lds_atomic_xor_noret_i64(i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw xor i64 addrspace(3)* %ptr, i64 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_xor_noret_i64_offset: -; SI: DS_XOR_B64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_xor_b64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_xor_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw xor i64 addrspace(3)* %gep, i64 4 seq_cst @@ -405,16 +405,16 @@ define void @lds_atomic_xor_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { ; } ; FUNC-LABEL: {{^}}lds_atomic_min_noret_i64: -; SI: DS_MIN_I64 -; SI: S_ENDPGM +; SI: ds_min_i64 +; SI: s_endpgm define void @lds_atomic_min_noret_i64(i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw min i64 addrspace(3)* %ptr, i64 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_min_noret_i64_offset: -; SI: DS_MIN_I64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_min_i64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_min_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw min i64 addrspace(3)* %gep, i64 4 seq_cst @@ -422,16 +422,16 @@ define void @lds_atomic_min_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_max_noret_i64: -; SI: DS_MAX_I64 -; SI: S_ENDPGM +; SI: ds_max_i64 +; SI: s_endpgm define void @lds_atomic_max_noret_i64(i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw max i64 addrspace(3)* %ptr, i64 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_max_noret_i64_offset: -; SI: DS_MAX_I64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_max_i64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_max_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw max i64 addrspace(3)* %gep, i64 4 seq_cst @@ -439,16 +439,16 @@ define void @lds_atomic_max_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_umin_noret_i64: -; SI: DS_MIN_U64 -; SI: S_ENDPGM +; SI: ds_min_u64 +; SI: s_endpgm define void @lds_atomic_umin_noret_i64(i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw umin i64 addrspace(3)* %ptr, i64 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_umin_noret_i64_offset: -; SI: DS_MIN_U64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_min_u64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_umin_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw umin i64 addrspace(3)* %gep, i64 4 seq_cst @@ -456,16 +456,16 @@ define void @lds_atomic_umin_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { } ; FUNC-LABEL: {{^}}lds_atomic_umax_noret_i64: -; SI: DS_MAX_U64 -; SI: S_ENDPGM +; SI: ds_max_u64 +; SI: s_endpgm define void @lds_atomic_umax_noret_i64(i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw umax i64 addrspace(3)* %ptr, i64 4 seq_cst ret void } ; FUNC-LABEL: {{^}}lds_atomic_umax_noret_i64_offset: -; SI: DS_MAX_U64 {{.*}} offset:32 -; SI: S_ENDPGM +; SI: ds_max_u64 {{.*}} offset:32 +; SI: s_endpgm define void @lds_atomic_umax_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw umax i64 addrspace(3)* %gep, i64 4 seq_cst diff --git a/test/CodeGen/R600/local-memory-two-objects.ll b/test/CodeGen/R600/local-memory-two-objects.ll index c61c65c42ab..4121d60df25 100644 --- a/test/CodeGen/R600/local-memory-two-objects.ll +++ b/test/CodeGen/R600/local-memory-two-objects.ll @@ -18,8 +18,8 @@ ; this consistently on evergreen GPUs. ; EG-CHECK: LDS_WRITE ; EG-CHECK: LDS_WRITE -; SI-CHECK: DS_WRITE_B32 {{v[0-9]*}}, v[[ADDRW:[0-9]*]] -; SI-CHECK-NOT: DS_WRITE_B32 {{v[0-9]*}}, v[[ADDRW]] +; SI-CHECK: ds_write_b32 {{v[0-9]*}}, v[[ADDRW:[0-9]*]] +; SI-CHECK-NOT: ds_write_b32 {{v[0-9]*}}, v[[ADDRW]] ; GROUP_BARRIER must be the last instruction in a clause ; EG-CHECK: GROUP_BARRIER @@ -29,10 +29,10 @@ ; constant offsets. ; EG-CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]] ; EG-CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]] -; SI: V_ADD_I32_e32 [[SIPTR:v[0-9]+]], 16, v{{[0-9]+}} -; SI: DS_READ_B32 {{v[0-9]+}}, [[SIPTR]] [M0] -; CI: DS_READ_B32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]] offset:16 [M0] -; CI: DS_READ_B32 {{v[0-9]+}}, [[ADDRR]] [M0] +; SI: v_add_i32_e32 [[SIPTR:v[0-9]+]], 16, v{{[0-9]+}} +; SI: ds_read_b32 {{v[0-9]+}}, [[SIPTR]] [M0] +; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]] offset:16 [M0] +; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR]] [M0] define void @local_memory_two_objects(i32 addrspace(1)* %out) { entry: diff --git a/test/CodeGen/R600/local-memory.ll b/test/CodeGen/R600/local-memory.ll index 279be38df19..b7565277fd3 100644 --- a/test/CodeGen/R600/local-memory.ll +++ b/test/CodeGen/R600/local-memory.ll @@ -15,16 +15,16 @@ ; CI-NEXT: .long 32768 ; EG: LDS_WRITE -; SI-NOT: S_WQM_B64 -; SI: DS_WRITE_B32 +; SI-NOT: s_wqm_b64 +; SI: ds_write_b32 ; GROUP_BARRIER must be the last instruction in a clause ; EG: GROUP_BARRIER ; EG-NEXT: ALU clause -; SI: S_BARRIER +; SI: s_barrier ; EG: LDS_READ_RET -; SI: DS_READ_B32 {{v[0-9]+}}, +; SI: ds_read_b32 {{v[0-9]+}}, define void @local_memory(i32 addrspace(1)* %out) { entry: diff --git a/test/CodeGen/R600/lshl.ll b/test/CodeGen/R600/lshl.ll index 21628391000..97858664747 100644 --- a/test/CodeGen/R600/lshl.ll +++ b/test/CodeGen/R600/lshl.ll @@ -1,6 +1,6 @@ ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s -;CHECK: S_LSHL_B32 s{{[0-9]}}, s{{[0-9]}}, 1 +;CHECK: s_lshl_b32 s{{[0-9]}}, s{{[0-9]}}, 1 define void @test(i32 %p) { %i = mul i32 %p, 2 diff --git a/test/CodeGen/R600/lshr.ll b/test/CodeGen/R600/lshr.ll index 886d1c4854d..acfc1fd63a2 100644 --- a/test/CodeGen/R600/lshr.ll +++ b/test/CodeGen/R600/lshr.ll @@ -1,6 +1,6 @@ ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s -;CHECK: S_LSHR_B32 s{{[0-9]}}, s{{[0-9]}}, 1 +;CHECK: s_lshr_b32 s{{[0-9]}}, s{{[0-9]}}, 1 define void @test(i32 %p) { %i = udiv i32 %p, 2 diff --git a/test/CodeGen/R600/mad-sub.ll b/test/CodeGen/R600/mad-sub.ll index 95a402149e8..240abd0dba3 100644 --- a/test/CodeGen/R600/mad-sub.ll +++ b/test/CodeGen/R600/mad-sub.ll @@ -4,11 +4,11 @@ declare i32 @llvm.r600.read.tidig.x() #0 declare float @llvm.fabs.f32(float) #0 ; FUNC-LABEL: {{^}}mad_sub_f32: -; SI: BUFFER_LOAD_DWORD [[REGA:v[0-9]+]] -; SI: BUFFER_LOAD_DWORD [[REGB:v[0-9]+]] -; SI: BUFFER_LOAD_DWORD [[REGC:v[0-9]+]] -; SI: V_MAD_F32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -[[REGC]] -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI: buffer_load_dword [[REGA:v[0-9]+]] +; SI: buffer_load_dword [[REGB:v[0-9]+]] +; SI: buffer_load_dword [[REGC:v[0-9]+]] +; SI: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -[[REGC]] +; SI: buffer_store_dword [[RESULT]] define void @mad_sub_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 { %tid = tail call i32 @llvm.r600.read.tidig.x() #0 %tid.ext = sext i32 %tid to i64 @@ -28,11 +28,11 @@ define void @mad_sub_f32(float addrspace(1)* noalias nocapture %out, float addrs } ; FUNC-LABEL: {{^}}mad_sub_inv_f32: -; SI: BUFFER_LOAD_DWORD [[REGA:v[0-9]+]] -; SI: BUFFER_LOAD_DWORD [[REGB:v[0-9]+]] -; SI: BUFFER_LOAD_DWORD [[REGC:v[0-9]+]] -; SI: V_MAD_F32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], [[REGC]] -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI: buffer_load_dword [[REGA:v[0-9]+]] +; SI: buffer_load_dword [[REGB:v[0-9]+]] +; SI: buffer_load_dword [[REGC:v[0-9]+]] +; SI: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], [[REGC]] +; SI: buffer_store_dword [[RESULT]] define void @mad_sub_inv_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 { %tid = tail call i32 @llvm.r600.read.tidig.x() #0 %tid.ext = sext i32 %tid to i64 @@ -52,8 +52,8 @@ define void @mad_sub_inv_f32(float addrspace(1)* noalias nocapture %out, float a } ; FUNC-LABEL: {{^}}mad_sub_f64: -; SI: V_MUL_F64 -; SI: V_ADD_F64 +; SI: v_mul_f64 +; SI: v_add_f64 define void @mad_sub_f64(double addrspace(1)* noalias nocapture %out, double addrspace(1)* noalias nocapture readonly %ptr) #1 { %tid = tail call i32 @llvm.r600.read.tidig.x() #0 %tid.ext = sext i32 %tid to i64 @@ -73,11 +73,11 @@ define void @mad_sub_f64(double addrspace(1)* noalias nocapture %out, double add } ; FUNC-LABEL: {{^}}mad_sub_fabs_f32: -; SI: BUFFER_LOAD_DWORD [[REGA:v[0-9]+]] -; SI: BUFFER_LOAD_DWORD [[REGB:v[0-9]+]] -; SI: BUFFER_LOAD_DWORD [[REGC:v[0-9]+]] -; SI: V_MAD_F32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -|[[REGC]]| -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI: buffer_load_dword [[REGA:v[0-9]+]] +; SI: buffer_load_dword [[REGB:v[0-9]+]] +; SI: buffer_load_dword [[REGC:v[0-9]+]] +; SI: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -|[[REGC]]| +; SI: buffer_store_dword [[RESULT]] define void @mad_sub_fabs_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 { %tid = tail call i32 @llvm.r600.read.tidig.x() #0 %tid.ext = sext i32 %tid to i64 @@ -98,11 +98,11 @@ define void @mad_sub_fabs_f32(float addrspace(1)* noalias nocapture %out, float } ; FUNC-LABEL: {{^}}mad_sub_fabs_inv_f32: -; SI: BUFFER_LOAD_DWORD [[REGA:v[0-9]+]] -; SI: BUFFER_LOAD_DWORD [[REGB:v[0-9]+]] -; SI: BUFFER_LOAD_DWORD [[REGC:v[0-9]+]] -; SI: V_MAD_F32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]| -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI: buffer_load_dword [[REGA:v[0-9]+]] +; SI: buffer_load_dword [[REGB:v[0-9]+]] +; SI: buffer_load_dword [[REGC:v[0-9]+]] +; SI: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]| +; SI: buffer_store_dword [[RESULT]] define void @mad_sub_fabs_inv_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 { %tid = tail call i32 @llvm.r600.read.tidig.x() #0 %tid.ext = sext i32 %tid to i64 @@ -123,7 +123,7 @@ define void @mad_sub_fabs_inv_f32(float addrspace(1)* noalias nocapture %out, fl } ; FUNC-LABEL: {{^}}neg_neg_mad_f32: -; SI: V_MAD_F32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; SI: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} define void @neg_neg_mad_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 { %tid = tail call i32 @llvm.r600.read.tidig.x() #0 %tid.ext = sext i32 %tid to i64 @@ -145,11 +145,11 @@ define void @neg_neg_mad_f32(float addrspace(1)* noalias nocapture %out, float a } ; FUNC-LABEL: {{^}}mad_fabs_sub_f32: -; SI: BUFFER_LOAD_DWORD [[REGA:v[0-9]+]] -; SI: BUFFER_LOAD_DWORD [[REGB:v[0-9]+]] -; SI: BUFFER_LOAD_DWORD [[REGC:v[0-9]+]] -; SI: V_MAD_F32 [[RESULT:v[0-9]+]], [[REGA]], |[[REGB]]|, -[[REGC]] -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI: buffer_load_dword [[REGA:v[0-9]+]] +; SI: buffer_load_dword [[REGB:v[0-9]+]] +; SI: buffer_load_dword [[REGC:v[0-9]+]] +; SI: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], |[[REGB]]|, -[[REGC]] +; SI: buffer_store_dword [[RESULT]] define void @mad_fabs_sub_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 { %tid = tail call i32 @llvm.r600.read.tidig.x() #0 %tid.ext = sext i32 %tid to i64 @@ -170,10 +170,10 @@ define void @mad_fabs_sub_f32(float addrspace(1)* noalias nocapture %out, float } ; FUNC-LABEL: {{^}}fsub_c_fadd_a_a: -; SI-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; SI-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 -; SI: V_MAD_F32 [[RESULT:v[0-9]+]], -2.0, [[R1]], [[R2]] -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; SI-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 +; SI: v_mad_f32 [[RESULT:v[0-9]+]], -2.0, [[R1]], [[R2]] +; SI: buffer_store_dword [[RESULT]] define void @fsub_c_fadd_a_a(float addrspace(1)* %out, float addrspace(1)* %in) { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid @@ -191,10 +191,10 @@ define void @fsub_c_fadd_a_a(float addrspace(1)* %out, float addrspace(1)* %in) } ; FUNC-LABEL: {{^}}fsub_fadd_a_a_c: -; SI-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; SI-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 -; SI: V_MAD_F32 [[RESULT:v[0-9]+]], 2.0, [[R1]], -[[R2]] -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; SI-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4 +; SI: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], -[[R2]] +; SI: buffer_store_dword [[RESULT]] define void @fsub_fadd_a_a_c(float addrspace(1)* %out, float addrspace(1)* %in) { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep.0 = getelementptr float addrspace(1)* %out, i32 %tid diff --git a/test/CodeGen/R600/mad_int24.ll b/test/CodeGen/R600/mad_int24.ll index 9b91a055dfe..2b854aba312 100644 --- a/test/CodeGen/R600/mad_int24.ll +++ b/test/CodeGen/R600/mad_int24.ll @@ -8,8 +8,8 @@ ; Make sure we aren't masking the inputs. ; CM-NOT: AND ; CM: MULADD_INT24 -; SI-NOT: AND -; SI: V_MAD_I32_I24 +; SI-NOT: and +; SI: v_mad_i32_i24 define void @i32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { entry: %0 = shl i32 %a, 8 diff --git a/test/CodeGen/R600/mad_uint24.ll b/test/CodeGen/R600/mad_uint24.ll index 103b65cb4d0..b7b32fe55cf 100644 --- a/test/CodeGen/R600/mad_uint24.ll +++ b/test/CodeGen/R600/mad_uint24.ll @@ -4,7 +4,7 @@ ; FUNC-LABEL: {{^}}u32_mad24: ; EG: MULADD_UINT24 -; SI: V_MAD_U32_U24 +; SI: v_mad_u32_u24 define void @u32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { entry: @@ -24,8 +24,8 @@ entry: ; The result must be sign-extended ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x ; EG: 16 -; SI: V_MAD_U32_U24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; SI: V_BFE_I32 v{{[0-9]}}, [[MAD]], 0, 16 +; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} +; SI: v_bfe_i32 v{{[0-9]}}, [[MAD]], 0, 16 define void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) { entry: @@ -41,8 +41,8 @@ entry: ; The result must be sign-extended ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x ; EG: 8 -; SI: V_MAD_U32_U24 [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; SI: V_BFE_I32 v{{[0-9]}}, [[MUL]], 0, 8 +; SI: v_mad_u32_u24 [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}} +; SI: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 8 define void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) { entry: @@ -62,7 +62,7 @@ entry: ; Check that the select instruction is not deleted. ; FUNC-LABEL: {{^}}i24_i32_i32_mad: ; EG: CNDE_INT -; SI: V_CNDMASK +; SI: v_cndmask define void @i24_i32_i32_mad(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) { entry: %0 = ashr i32 %a, 8 diff --git a/test/CodeGen/R600/missing-store.ll b/test/CodeGen/R600/missing-store.ll index aa34380a157..fa912083d95 100644 --- a/test/CodeGen/R600/missing-store.ll +++ b/test/CodeGen/R600/missing-store.ll @@ -6,11 +6,11 @@ ; resulting in losing the store to gptr ; FUNC-LABEL: {{^}}missing_store_reduced: -; SI: DS_READ_B64 -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_LOAD_DWORD -; SI: BUFFER_STORE_DWORD -; SI: S_ENDPGM +; SI: ds_read_b64 +; SI: buffer_store_dword +; SI: buffer_load_dword +; SI: buffer_store_dword +; SI: s_endpgm define void @missing_store_reduced(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 { %ptr0 = load i32 addrspace(2)* addrspace(3)* @ptr_load, align 8 %ptr2 = getelementptr inbounds i32 addrspace(2)* %ptr0, i64 2 diff --git a/test/CodeGen/R600/mubuf.ll b/test/CodeGen/R600/mubuf.ll index 062006e6543..c2efda4c8e8 100644 --- a/test/CodeGen/R600/mubuf.ll +++ b/test/CodeGen/R600/mubuf.ll @@ -8,7 +8,7 @@ declare i32 @llvm.r600.read.tidig.x() readnone ; MUBUF load with an immediate byte offset that fits into 12-bits ; CHECK-LABEL: {{^}}mubuf_load0: -; CHECK: BUFFER_LOAD_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:0x4 ; encoding: [0x04,0x00,0x30,0xe0 +; CHECK: buffer_load_dword v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:0x4 ; encoding: [0x04,0x00,0x30,0xe0 define void @mubuf_load0(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { entry: %0 = getelementptr i32 addrspace(1)* %in, i64 1 @@ -19,7 +19,7 @@ entry: ; MUBUF load with the largest possible immediate offset ; CHECK-LABEL: {{^}}mubuf_load1: -; CHECK: BUFFER_LOAD_UBYTE v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:0xfff ; encoding: [0xff,0x0f,0x20,0xe0 +; CHECK: buffer_load_ubyte v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:0xfff ; encoding: [0xff,0x0f,0x20,0xe0 define void @mubuf_load1(i8 addrspace(1)* %out, i8 addrspace(1)* %in) { entry: %0 = getelementptr i8 addrspace(1)* %in, i64 4095 @@ -30,7 +30,7 @@ entry: ; MUBUF load with an immediate byte offset that doesn't fit into 12-bits ; CHECK-LABEL: {{^}}mubuf_load2: -; CHECK: BUFFER_LOAD_DWORD v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 ; encoding: [0x00,0x80,0x30,0xe0 +; CHECK: buffer_load_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 ; encoding: [0x00,0x80,0x30,0xe0 define void @mubuf_load2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { entry: %0 = getelementptr i32 addrspace(1)* %in, i64 1024 @@ -42,7 +42,7 @@ entry: ; MUBUF load with a 12-bit immediate offset and a register offset ; CHECK-LABEL: {{^}}mubuf_load3: ; CHECK-NOT: ADD -; CHECK: BUFFER_LOAD_DWORD v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:0x4 ; encoding: [0x04,0x80,0x30,0xe0 +; CHECK: buffer_load_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:0x4 ; encoding: [0x04,0x80,0x30,0xe0 define void @mubuf_load3(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i64 %offset) { entry: %0 = getelementptr i32 addrspace(1)* %in, i64 %offset @@ -58,7 +58,7 @@ entry: ; MUBUF store with an immediate byte offset that fits into 12-bits ; CHECK-LABEL: {{^}}mubuf_store0: -; CHECK: BUFFER_STORE_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:0x4 ; encoding: [0x04,0x00,0x70,0xe0 +; CHECK: buffer_store_dword v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:0x4 ; encoding: [0x04,0x00,0x70,0xe0 define void @mubuf_store0(i32 addrspace(1)* %out) { entry: %0 = getelementptr i32 addrspace(1)* %out, i64 1 @@ -68,7 +68,7 @@ entry: ; MUBUF store with the largest possible immediate offset ; CHECK-LABEL: {{^}}mubuf_store1: -; CHECK: BUFFER_STORE_BYTE v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:0xfff ; encoding: [0xff,0x0f,0x60,0xe0 +; CHECK: buffer_store_byte v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:0xfff ; encoding: [0xff,0x0f,0x60,0xe0 define void @mubuf_store1(i8 addrspace(1)* %out) { entry: @@ -79,7 +79,7 @@ entry: ; MUBUF store with an immediate byte offset that doesn't fit into 12-bits ; CHECK-LABEL: {{^}}mubuf_store2: -; CHECK: BUFFER_STORE_DWORD v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0 addr64 ; encoding: [0x00,0x80,0x70,0xe0 +; CHECK: buffer_store_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0 addr64 ; encoding: [0x00,0x80,0x70,0xe0 define void @mubuf_store2(i32 addrspace(1)* %out) { entry: %0 = getelementptr i32 addrspace(1)* %out, i64 1024 @@ -90,7 +90,7 @@ entry: ; MUBUF store with a 12-bit immediate offset and a register offset ; CHECK-LABEL: {{^}}mubuf_store3: ; CHECK-NOT: ADD -; CHECK: BUFFER_STORE_DWORD v{{[0-9]}}, v[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0 addr64 offset:0x4 ; encoding: [0x04,0x80,0x70,0xe0 +; CHECK: buffer_store_dword v{{[0-9]}}, v[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0 addr64 offset:0x4 ; encoding: [0x04,0x80,0x70,0xe0 define void @mubuf_store3(i32 addrspace(1)* %out, i64 %offset) { entry: %0 = getelementptr i32 addrspace(1)* %out, i64 %offset @@ -100,14 +100,14 @@ entry: } ; CHECK-LABEL: {{^}}store_sgpr_ptr: -; CHECK: BUFFER_STORE_DWORD v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 +; CHECK: buffer_store_dword v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 define void @store_sgpr_ptr(i32 addrspace(1)* %out) #0 { store i32 99, i32 addrspace(1)* %out, align 4 ret void } ; CHECK-LABEL: {{^}}store_sgpr_ptr_offset: -; CHECK: BUFFER_STORE_DWORD v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:0x28 +; CHECK: buffer_store_dword v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:0x28 define void @store_sgpr_ptr_offset(i32 addrspace(1)* %out) #0 { %out.gep = getelementptr i32 addrspace(1)* %out, i32 10 store i32 99, i32 addrspace(1)* %out.gep, align 4 @@ -115,7 +115,7 @@ define void @store_sgpr_ptr_offset(i32 addrspace(1)* %out) #0 { } ; CHECK-LABEL: {{^}}store_sgpr_ptr_large_offset: -; CHECK: BUFFER_STORE_DWORD v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 +; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 define void @store_sgpr_ptr_large_offset(i32 addrspace(1)* %out) #0 { %out.gep = getelementptr i32 addrspace(1)* %out, i32 32768 store i32 99, i32 addrspace(1)* %out.gep, align 4 @@ -123,7 +123,7 @@ define void @store_sgpr_ptr_large_offset(i32 addrspace(1)* %out) #0 { } ; CHECK-LABEL: {{^}}store_vgpr_ptr: -; CHECK: BUFFER_STORE_DWORD v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 +; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 define void @store_vgpr_ptr(i32 addrspace(1)* %out) #0 { %tid = call i32 @llvm.r600.read.tidig.x() readnone %out.gep = getelementptr i32 addrspace(1)* %out, i32 %tid diff --git a/test/CodeGen/R600/mul.ll b/test/CodeGen/R600/mul.ll index bf1a1e1ffef..be5d6a0a2ba 100644 --- a/test/CodeGen/R600/mul.ll +++ b/test/CodeGen/R600/mul.ll @@ -7,8 +7,8 @@ ; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; SI: V_MUL_LO_I32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; SI: V_MUL_LO_I32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @test_mul_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -25,10 +25,10 @@ define void @test_mul_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1) ; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; SI: V_MUL_LO_I32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; SI: V_MUL_LO_I32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; SI: V_MUL_LO_I32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; SI: V_MUL_LO_I32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @v_mul_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 @@ -40,10 +40,10 @@ define void @v_mul_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* % } ; FUNC-LABEL: {{^}}s_trunc_i64_mul_to_i32: -; SI: S_LOAD_DWORD -; SI: S_LOAD_DWORD -; SI: S_MUL_I32 -; SI: BUFFER_STORE_DWORD +; SI: s_load_dword +; SI: s_load_dword +; SI: s_mul_i32 +; SI: buffer_store_dword define void @s_trunc_i64_mul_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) { %mul = mul i64 %b, %a %trunc = trunc i64 %mul to i32 @@ -52,10 +52,10 @@ define void @s_trunc_i64_mul_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) { } ; FUNC-LABEL: {{^}}v_trunc_i64_mul_to_i32: -; SI: S_LOAD_DWORD -; SI: S_LOAD_DWORD -; SI: V_MUL_LO_I32 -; SI: BUFFER_STORE_DWORD +; SI: s_load_dword +; SI: s_load_dword +; SI: v_mul_lo_i32 +; SI: buffer_store_dword define void @v_trunc_i64_mul_to_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind { %a = load i64 addrspace(1)* %aptr, align 8 %b = load i64 addrspace(1)* %bptr, align 8 @@ -70,8 +70,8 @@ define void @v_trunc_i64_mul_to_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %a ; FUNC-LABEL: {{^}}mul64_sext_c: ; EG-DAG: MULLO_INT ; EG-DAG: MULHI_INT -; SI-DAG: S_MUL_I32 -; SI-DAG: V_MUL_HI_I32 +; SI-DAG: s_mul_i32 +; SI-DAG: v_mul_hi_i32 define void @mul64_sext_c(i64 addrspace(1)* %out, i32 %in) { entry: %0 = sext i32 %in to i64 @@ -83,9 +83,9 @@ entry: ; FUNC-LABEL: {{^}}v_mul64_sext_c: ; EG-DAG: MULLO_INT ; EG-DAG: MULHI_INT -; SI-DAG: V_MUL_LO_I32 -; SI-DAG: V_MUL_HI_I32 -; SI: S_ENDPGM +; SI-DAG: v_mul_lo_i32 +; SI-DAG: v_mul_hi_i32 +; SI: s_endpgm define void @v_mul64_sext_c(i64 addrspace(1)* %out, i32 addrspace(1)* %in) { %val = load i32 addrspace(1)* %in, align 4 %ext = sext i32 %val to i64 @@ -95,9 +95,9 @@ define void @v_mul64_sext_c(i64 addrspace(1)* %out, i32 addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}v_mul64_sext_inline_imm: -; SI-DAG: V_MUL_LO_I32 v{{[0-9]+}}, 9, v{{[0-9]+}} -; SI-DAG: V_MUL_HI_I32 v{{[0-9]+}}, 9, v{{[0-9]+}} -; SI: S_ENDPGM +; SI-DAG: v_mul_lo_i32 v{{[0-9]+}}, 9, v{{[0-9]+}} +; SI-DAG: v_mul_hi_i32 v{{[0-9]+}}, 9, v{{[0-9]+}} +; SI: s_endpgm define void @v_mul64_sext_inline_imm(i64 addrspace(1)* %out, i32 addrspace(1)* %in) { %val = load i32 addrspace(1)* %in, align 4 %ext = sext i32 %val to i64 @@ -107,12 +107,12 @@ define void @v_mul64_sext_inline_imm(i64 addrspace(1)* %out, i32 addrspace(1)* % } ; FUNC-LABEL: {{^}}s_mul_i32: -; SI: S_LOAD_DWORD [[SRC0:s[0-9]+]], -; SI: S_LOAD_DWORD [[SRC1:s[0-9]+]], -; SI: S_MUL_I32 [[SRESULT:s[0-9]+]], [[SRC0]], [[SRC1]] -; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] -; SI: BUFFER_STORE_DWORD [[VRESULT]], -; SI: S_ENDPGM +; SI: s_load_dword [[SRC0:s[0-9]+]], +; SI: s_load_dword [[SRC1:s[0-9]+]], +; SI: s_mul_i32 [[SRESULT:s[0-9]+]], [[SRC0]], [[SRC1]] +; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] +; SI: buffer_store_dword [[VRESULT]], +; SI: s_endpgm define void @s_mul_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %mul = mul i32 %a, %b store i32 %mul, i32 addrspace(1)* %out, align 4 @@ -120,7 +120,7 @@ define void @s_mul_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { } ; FUNC-LABEL: {{^}}v_mul_i32: -; SI: V_MUL_LO_I32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; SI: v_mul_lo_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} define void @v_mul_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1 %a = load i32 addrspace(1)* %in @@ -145,7 +145,7 @@ define void @s_mul_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { } ; FUNC-LABEL: {{^}}v_mul_i64: -; SI: V_MUL_LO_I32 +; SI: v_mul_lo_i32 define void @v_mul_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) { %a = load i64 addrspace(1)* %aptr, align 8 %b = load i64 addrspace(1)* %bptr, align 8 @@ -155,7 +155,7 @@ define void @v_mul_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addr } ; FUNC-LABEL: {{^}}mul32_in_branch: -; SI: S_MUL_I32 +; SI: s_mul_i32 define void @mul32_in_branch(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b, i32 %c) { entry: %0 = icmp eq i32 %a, 0 @@ -176,9 +176,9 @@ endif: } ; FUNC-LABEL: {{^}}mul64_in_branch: -; SI-DAG: S_MUL_I32 -; SI-DAG: V_MUL_HI_U32 -; SI: S_ENDPGM +; SI-DAG: s_mul_i32 +; SI-DAG: v_mul_hi_u32 +; SI: s_endpgm define void @mul64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) { entry: %0 = icmp eq i64 %a, 0 diff --git a/test/CodeGen/R600/mul_int24.ll b/test/CodeGen/R600/mul_int24.ll index 177505cb5bf..be58f7e8f71 100644 --- a/test/CodeGen/R600/mul_int24.ll +++ b/test/CodeGen/R600/mul_int24.ll @@ -8,8 +8,8 @@ ; Make sure we are not masking the inputs ; CM-NOT: AND ; CM: MUL_INT24 -; SI-NOT: AND -; SI: V_MUL_I32_I24 +; SI-NOT: and +; SI: v_mul_i32_i24 define void @i32_mul24(i32 addrspace(1)* %out, i32 %a, i32 %b) { entry: %0 = shl i32 %a, 8 diff --git a/test/CodeGen/R600/mul_uint24.ll b/test/CodeGen/R600/mul_uint24.ll index 3904fac6397..8d1cda83f19 100644 --- a/test/CodeGen/R600/mul_uint24.ll +++ b/test/CodeGen/R600/mul_uint24.ll @@ -4,7 +4,7 @@ ; FUNC-LABEL: {{^}}u32_mul24: ; EG: MUL_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W -; SI: V_MUL_U32_U24 +; SI: v_mul_u32_u24 define void @u32_mul24(i32 addrspace(1)* %out, i32 %a, i32 %b) { entry: @@ -22,8 +22,8 @@ entry: ; The result must be sign-extended ; EG: BFE_INT {{[* ]*}}T{{[0-9]}}.{{[XYZW]}}, PV.[[MUL_CHAN]], 0.0, literal.x ; EG: 16 -; SI: V_MUL_U32_U24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; SI: V_BFE_I32 v{{[0-9]}}, [[MUL]], 0, 16 +; SI: v_mul_u32_u24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}} +; SI: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 16 define void @i16_mul24(i32 addrspace(1)* %out, i16 %a, i16 %b) { entry: %0 = mul i16 %a, %b @@ -36,8 +36,8 @@ entry: ; EG: MUL_UINT24 {{[* ]*}}T{{[0-9]}}.[[MUL_CHAN:[XYZW]]] ; The result must be sign-extended ; EG: BFE_INT {{[* ]*}}T{{[0-9]}}.{{[XYZW]}}, PV.[[MUL_CHAN]], 0.0, literal.x -; SI: V_MUL_U32_U24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; SI: V_BFE_I32 v{{[0-9]}}, [[MUL]], 0, 8 +; SI: v_mul_u32_u24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}} +; SI: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 8 define void @i8_mul24(i32 addrspace(1)* %out, i8 %a, i8 %b) { entry: @@ -51,9 +51,9 @@ entry: ; FUNC_LABEL: {{^}}mul24_i64: ; EG; MUL_UINT24 ; EG: MULHI -; SI: V_MUL_U32_U24 +; SI: v_mul_u32_u24 ; FIXME: SI support 24-bit mulhi -; SI: V_MUL_HI_U32 +; SI: v_mul_hi_u32 define void @mul24_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { entry: %0 = shl i64 %a, 40 diff --git a/test/CodeGen/R600/mulhu.ll b/test/CodeGen/R600/mulhu.ll index 86401274811..82a0783b7cf 100644 --- a/test/CodeGen/R600/mulhu.ll +++ b/test/CodeGen/R600/mulhu.ll @@ -1,8 +1,8 @@ ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s -;CHECK: V_MOV_B32_e32 v{{[0-9]+}}, 0xaaaaaaab -;CHECK: V_MUL_HI_U32 v0, {{[sv][0-9]+}}, {{v[0-9]+}} -;CHECK-NEXT: V_LSHRREV_B32_e32 v0, 1, v0 +;CHECK: v_mov_b32_e32 v{{[0-9]+}}, 0xaaaaaaab +;CHECK: v_mul_hi_u32 v0, {{[sv][0-9]+}}, {{v[0-9]+}} +;CHECK-NEXT: v_lshrrev_b32_e32 v0, 1, v0 define void @test(i32 %p) { %i = udiv i32 %p, 3 diff --git a/test/CodeGen/R600/operand-spacing.ll b/test/CodeGen/R600/operand-spacing.ll index bd80414ba6d..f0d228df43b 100644 --- a/test/CodeGen/R600/operand-spacing.ll +++ b/test/CodeGen/R600/operand-spacing.ll @@ -3,11 +3,11 @@ ; Make sure there isn't an extra space between the instruction name and first operands. ; SI-LABEL: {{^}}add_f32: -; SI-DAG: S_LOAD_DWORD [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: S_LOAD_DWORD [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI: V_MOV_B32_e32 [[VREGB:v[0-9]+]], [[SREGB]] -; SI: V_ADD_F32_e32 [[RESULT:v[0-9]+]], [[SREGA]], [[VREGB]] -; SI: BUFFER_STORE_DWORD [[RESULT]], +; SI-DAG: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI: v_mov_b32_e32 [[VREGB:v[0-9]+]], [[SREGB]] +; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], [[SREGA]], [[VREGB]] +; SI: buffer_store_dword [[RESULT]], define void @add_f32(float addrspace(1)* %out, float %a, float %b) { %result = fadd float %a, %b store float %result, float addrspace(1)* %out diff --git a/test/CodeGen/R600/or.ll b/test/CodeGen/R600/or.ll index dbe3326fb24..99dedac809e 100644 --- a/test/CodeGen/R600/or.ll +++ b/test/CodeGen/R600/or.ll @@ -6,8 +6,8 @@ ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; SI-LABEL: {{^}}or_v2i32: -; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -25,10 +25,10 @@ define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; SI-LABEL: {{^}}or_v4i32: -; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 @@ -40,7 +40,7 @@ define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) } ; SI-LABEL: {{^}}scalar_or_i32: -; SI: S_OR_B32 +; SI: s_or_b32 define void @scalar_or_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { %or = or i32 %a, %b store i32 %or, i32 addrspace(1)* %out @@ -48,7 +48,7 @@ define void @scalar_or_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { } ; SI-LABEL: {{^}}vector_or_i32: -; SI: V_OR_B32_e32 v{{[0-9]}} +; SI: v_or_b32_e32 v{{[0-9]}} define void @vector_or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 %b) { %loada = load i32 addrspace(1)* %a %or = or i32 %loada, %b @@ -57,7 +57,7 @@ define void @vector_or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 %b) } ; SI-LABEL: {{^}}scalar_or_literal_i32: -; SI: S_OR_B32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1869f +; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1869f define void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) { %or = or i32 %a, 99999 store i32 %or, i32 addrspace(1)* %out, align 4 @@ -65,7 +65,7 @@ define void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) { } ; SI-LABEL: {{^}}vector_or_literal_i32: -; SI: V_OR_B32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}} define void @vector_or_literal_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) { %loada = load i32 addrspace(1)* %a, align 4 %or = or i32 %loada, 65535 @@ -74,7 +74,7 @@ define void @vector_or_literal_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, } ; SI-LABEL: {{^}}vector_or_inline_immediate_i32: -; SI: V_OR_B32_e32 v{{[0-9]+}}, 4, v{{[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+}}, 4, v{{[0-9]+}} define void @vector_or_inline_immediate_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) { %loada = load i32 addrspace(1)* %a, align 4 %or = or i32 %loada, 4 @@ -86,7 +86,7 @@ define void @vector_or_inline_immediate_i32(i32 addrspace(1)* %out, i32 addrspac ; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y ; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z ; SI-LABEL: {{^}}scalar_or_i64: -; SI: S_OR_B64 +; SI: s_or_b64 define void @scalar_or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { %or = or i64 %a, %b store i64 %or, i64 addrspace(1)* %out @@ -94,8 +94,8 @@ define void @scalar_or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { } ; SI-LABEL: {{^}}vector_or_i64: -; SI: V_OR_B32_e32 v{{[0-9]}} -; SI: V_OR_B32_e32 v{{[0-9]}} +; SI: v_or_b32_e32 v{{[0-9]}} +; SI: v_or_b32_e32 v{{[0-9]}} define void @vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { %loada = load i64 addrspace(1)* %a, align 8 %loadb = load i64 addrspace(1)* %a, align 8 @@ -105,8 +105,8 @@ define void @vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 add } ; SI-LABEL: {{^}}scalar_vector_or_i64: -; SI: V_OR_B32_e32 v{{[0-9]}} -; SI: V_OR_B32_e32 v{{[0-9]}} +; SI: v_or_b32_e32 v{{[0-9]}} +; SI: v_or_b32_e32 v{{[0-9]}} define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 %b) { %loada = load i64 addrspace(1)* %a %or = or i64 %loada, %b @@ -115,12 +115,12 @@ define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, } ; SI-LABEL: {{^}}vector_or_i64_loadimm: -; SI-DAG: S_MOV_B32 [[LO_S_IMM:s[0-9]+]], 0xdf77987f -; SI-DAG: S_MOV_B32 [[HI_S_IMM:s[0-9]+]], 0x146f -; SI-DAG: BUFFER_LOAD_DWORDX2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, -; SI-DAG: V_OR_B32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] -; SI-DAG: V_OR_B32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]] -; SI: S_ENDPGM +; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xdf77987f +; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x146f +; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, +; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] +; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]] +; SI: s_endpgm define void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { %loada = load i64 addrspace(1)* %a, align 8 %or = or i64 %loada, 22470723082367 @@ -130,10 +130,10 @@ define void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, ; FIXME: The or 0 should really be removed. ; SI-LABEL: {{^}}vector_or_i64_imm: -; SI: BUFFER_LOAD_DWORDX2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, -; SI: V_OR_B32_e32 {{v[0-9]+}}, 8, v[[LO_VREG]] -; SI: V_OR_B32_e32 {{v[0-9]+}}, 0, {{.*}} -; SI: S_ENDPGM +; SI: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, +; SI: v_or_b32_e32 {{v[0-9]+}}, 8, v[[LO_VREG]] +; SI: v_or_b32_e32 {{v[0-9]+}}, 0, {{.*}} +; SI: s_endpgm define void @vector_or_i64_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { %loada = load i64 addrspace(1)* %a, align 8 %or = or i64 %loada, 8 @@ -142,11 +142,11 @@ define void @vector_or_i64_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 } ; SI-LABEL: {{^}}trunc_i64_or_to_i32: -; SI: S_LOAD_DWORD s[[SREG0:[0-9]+]] -; SI: S_LOAD_DWORD s[[SREG1:[0-9]+]] -; SI: S_OR_B32 s[[SRESULT:[0-9]+]], s[[SREG1]], s[[SREG0]] -; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], s[[SRESULT]] -; SI: BUFFER_STORE_DWORD [[VRESULT]], +; SI: s_load_dword s[[SREG0:[0-9]+]] +; SI: s_load_dword s[[SREG1:[0-9]+]] +; SI: s_or_b32 s[[SRESULT:[0-9]+]], s[[SREG1]], s[[SREG0]] +; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], s[[SRESULT]] +; SI: buffer_store_dword [[VRESULT]], define void @trunc_i64_or_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) { %add = or i64 %b, %a %trunc = trunc i64 %add to i32 @@ -158,7 +158,7 @@ define void @trunc_i64_or_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) { ; EG-CHECK: OR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}} ; SI-CHECK: {{^}}or_i1: -; SI-CHECK: S_OR_B64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] +; SI-CHECK: s_or_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] define void @or_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) { %a = load float addrspace(1) * %in0 %b = load float addrspace(1) * %in1 diff --git a/test/CodeGen/R600/private-memory.ll b/test/CodeGen/R600/private-memory.ll index b865e91d3f9..bfb4a6a0840 100644 --- a/test/CodeGen/R600/private-memory.ll +++ b/test/CodeGen/R600/private-memory.ll @@ -11,13 +11,13 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone ; R600: LDS_READ ; R600: LDS_READ -; SI-PROMOTE: DS_WRITE_B32 -; SI-PROMOTE: DS_WRITE_B32 -; SI-PROMOTE: DS_READ_B32 -; SI-PROMOTE: DS_READ_B32 +; SI-PROMOTE: ds_write_b32 +; SI-PROMOTE: ds_write_b32 +; SI-PROMOTE: ds_read_b32 +; SI-PROMOTE: ds_read_b32 -; SI-ALLOCA: BUFFER_STORE_DWORD v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x70,0xe0 -; SI-ALLOCA: BUFFER_STORE_DWORD v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x70,0xe0 +; SI-ALLOCA: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x70,0xe0 +; SI-ALLOCA: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x70,0xe0 define void @mova_same_clause(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) { entry: %stack = alloca [5 x i32], align 4 @@ -47,8 +47,8 @@ entry: ; FUNC-LABEL: {{^}}multiple_structs: ; R600-NOT: MOVA_INT -; SI-NOT: V_MOVREL -; SI-NOT: V_MOVREL +; SI-NOT: v_movrel +; SI-NOT: v_movrel %struct.point = type { i32, i32 } define void @multiple_structs(i32 addrspace(1)* %out) { @@ -78,7 +78,7 @@ entry: ; FUNC-LABEL: {{^}}direct_loop: ; R600-NOT: MOVA_INT -; SI-NOT: V_MOVREL +; SI-NOT: v_movrel define void @direct_loop(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { entry: @@ -116,9 +116,9 @@ for.end: ; R600: MOVA_INT -; SI-PROMOTE-DAG: BUFFER_STORE_SHORT v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x68,0xe0 -; SI-PROMOTE-DAG: BUFFER_STORE_SHORT v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:0x2 ; encoding: [0x02,0x10,0x68,0xe0 -; SI-PROMOTE: BUFFER_LOAD_SSHORT v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} +; SI-PROMOTE-DAG: buffer_store_short v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x68,0xe0 +; SI-PROMOTE-DAG: buffer_store_short v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:0x2 ; encoding: [0x02,0x10,0x68,0xe0 +; SI-PROMOTE: buffer_load_sshort v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} define void @short_array(i32 addrspace(1)* %out, i32 %index) { entry: %0 = alloca [2 x i16] @@ -137,8 +137,8 @@ entry: ; R600: MOVA_INT -; SI-DAG: BUFFER_STORE_BYTE v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x60,0xe0 -; SI-DAG: BUFFER_STORE_BYTE v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:0x1 ; encoding: [0x01,0x10,0x60,0xe0 +; SI-DAG: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x60,0xe0 +; SI-DAG: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:0x1 ; encoding: [0x01,0x10,0x60,0xe0 define void @char_array(i32 addrspace(1)* %out, i32 %index) { entry: %0 = alloca [2 x i8] @@ -161,7 +161,7 @@ entry: ; Additional check in case the move ends up in the last slot ; R600-NOT: MOV * TO.X -; SI-NOT: V_MOV_B32_e{{(32|64)}} v0 +; SI-NOT: v_mov_b32_e{{(32|64)}} v0 define void @work_item_info(i32 addrspace(1)* %out, i32 %in) { entry: %0 = alloca [2 x i32] @@ -183,7 +183,7 @@ entry: ; R600_CHECK: MOV ; R600_CHECK: [[CHAN:[XYZW]]]+ ; R600-NOT: [[CHAN]]+ -; SI: V_MOV_B32_e32 v3 +; SI: v_mov_b32_e32 v3 define void @no_overlap(i32 addrspace(1)* %out, i32 %in) { entry: %0 = alloca [3 x i8], align 1 @@ -294,9 +294,9 @@ entry: ; finds one, it should stop trying to promote. ; FUNC-LABEL: ptrtoint: -; SI-NOT: DS_WRITE -; SI: BUFFER_STORE_DWORD v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen -; SI: BUFFER_LOAD_DWORD v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:0x5 +; SI-NOT: ds_write +; SI: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen +; SI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:0x5 define void @ptrtoint(i32 addrspace(1)* %out, i32 %a, i32 %b) { %alloca = alloca [16 x i32] %tmp0 = getelementptr [16 x i32]* %alloca, i32 0, i32 %a diff --git a/test/CodeGen/R600/reorder-stores.ll b/test/CodeGen/R600/reorder-stores.ll index 77848ddd67e..30c0171a225 100644 --- a/test/CodeGen/R600/reorder-stores.ll +++ b/test/CodeGen/R600/reorder-stores.ll @@ -1,15 +1,15 @@ ; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s ; SI-LABEL: {{^}}no_reorder_v2f64_global_load_store: -; SI: BUFFER_LOAD_DWORDX2 -; SI: BUFFER_LOAD_DWORDX2 -; SI: BUFFER_LOAD_DWORDX2 -; SI: BUFFER_LOAD_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 -; SI: S_ENDPGM +; SI: buffer_load_dwordx2 +; SI: buffer_load_dwordx2 +; SI: buffer_load_dwordx2 +; SI: buffer_load_dwordx2 +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +; SI: s_endpgm define void @no_reorder_v2f64_global_load_store(<2 x double> addrspace(1)* nocapture %x, <2 x double> addrspace(1)* nocapture %y) nounwind { %tmp1 = load <2 x double> addrspace(1)* %x, align 16 %tmp4 = load <2 x double> addrspace(1)* %y, align 16 @@ -19,11 +19,11 @@ define void @no_reorder_v2f64_global_load_store(<2 x double> addrspace(1)* nocap } ; SI-LABEL: {{^}}no_reorder_scalarized_v2f64_local_load_store: -; SI: DS_READ_B64 -; SI: DS_READ_B64 -; SI: DS_WRITE_B64 -; SI: DS_WRITE_B64 -; SI: S_ENDPGM +; SI: ds_read_b64 +; SI: ds_read_b64 +; SI: ds_write_b64 +; SI: ds_write_b64 +; SI: s_endpgm define void @no_reorder_scalarized_v2f64_local_load_store(<2 x double> addrspace(3)* nocapture %x, <2 x double> addrspace(3)* nocapture %y) nounwind { %tmp1 = load <2 x double> addrspace(3)* %x, align 16 %tmp4 = load <2 x double> addrspace(3)* %y, align 16 @@ -33,47 +33,47 @@ define void @no_reorder_scalarized_v2f64_local_load_store(<2 x double> addrspace } ; SI-LABEL: {{^}}no_reorder_split_v8i32_global_load_store: -; SI: BUFFER_LOAD_DWORD -; SI: BUFFER_LOAD_DWORD -; SI: BUFFER_LOAD_DWORD -; SI: BUFFER_LOAD_DWORD +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword -; SI: BUFFER_LOAD_DWORD -; SI: BUFFER_LOAD_DWORD -; SI: BUFFER_LOAD_DWORD -; SI: BUFFER_LOAD_DWORD +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword -; SI: BUFFER_LOAD_DWORD -; SI: BUFFER_LOAD_DWORD -; SI: BUFFER_LOAD_DWORD -; SI: BUFFER_LOAD_DWORD +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword -; SI: BUFFER_LOAD_DWORD -; SI: BUFFER_LOAD_DWORD -; SI: BUFFER_LOAD_DWORD -; SI: BUFFER_LOAD_DWORD +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD +; SI: buffer_store_dword +; SI: buffer_store_dword +; SI: buffer_store_dword +; SI: buffer_store_dword -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD +; SI: buffer_store_dword +; SI: buffer_store_dword +; SI: buffer_store_dword +; SI: buffer_store_dword -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD +; SI: buffer_store_dword +; SI: buffer_store_dword +; SI: buffer_store_dword +; SI: buffer_store_dword -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD -; SI: BUFFER_STORE_DWORD -; SI: S_ENDPGM +; SI: buffer_store_dword +; SI: buffer_store_dword +; SI: buffer_store_dword +; SI: buffer_store_dword +; SI: s_endpgm define void @no_reorder_split_v8i32_global_load_store(<8 x i32> addrspace(1)* nocapture %x, <8 x i32> addrspace(1)* nocapture %y) nounwind { %tmp1 = load <8 x i32> addrspace(1)* %x, align 32 %tmp4 = load <8 x i32> addrspace(1)* %y, align 32 @@ -83,12 +83,12 @@ define void @no_reorder_split_v8i32_global_load_store(<8 x i32> addrspace(1)* no } ; SI-LABEL: {{^}}no_reorder_extload_64: -; SI: DS_READ_B64 -; SI: DS_READ_B64 -; SI: DS_WRITE_B64 -; SI-NOT: DS_READ -; SI: DS_WRITE_B64 -; SI: S_ENDPGM +; SI: ds_read_b64 +; SI: ds_read_b64 +; SI: ds_write_b64 +; SI-NOT: ds_read +; SI: ds_write_b64 +; SI: s_endpgm define void @no_reorder_extload_64(<2 x i32> addrspace(3)* nocapture %x, <2 x i32> addrspace(3)* nocapture %y) nounwind { %tmp1 = load <2 x i32> addrspace(3)* %x, align 8 %tmp4 = load <2 x i32> addrspace(3)* %y, align 8 diff --git a/test/CodeGen/R600/rotl.i64.ll b/test/CodeGen/R600/rotl.i64.ll index a10620f6180..84a35b65619 100644 --- a/test/CodeGen/R600/rotl.i64.ll +++ b/test/CodeGen/R600/rotl.i64.ll @@ -1,11 +1,11 @@ ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}s_rotl_i64: -; SI-DAG: S_LSHL_B64 -; SI-DAG: S_SUB_I32 -; SI-DAG: S_LSHR_B64 -; SI: S_OR_B64 -; SI: S_ENDPGM +; SI-DAG: s_lshl_b64 +; SI-DAG: s_sub_i32 +; SI-DAG: s_lshr_b64 +; SI: s_or_b64 +; SI: s_endpgm define void @s_rotl_i64(i64 addrspace(1)* %in, i64 %x, i64 %y) { entry: %0 = shl i64 %x, %y @@ -17,12 +17,12 @@ entry: } ; FUNC-LABEL: {{^}}v_rotl_i64: -; SI-DAG: V_LSHL_B64 -; SI-DAG: V_SUB_I32 -; SI: V_LSHR_B64 -; SI: V_OR_B32 -; SI: V_OR_B32 -; SI: S_ENDPGM +; SI-DAG: v_lshl_b64 +; SI-DAG: v_sub_i32 +; SI: v_lshr_b64 +; SI: v_or_b32 +; SI: v_or_b32 +; SI: s_endpgm define void @v_rotl_i64(i64 addrspace(1)* %in, i64 addrspace(1)* %xptr, i64 addrspace(1)* %yptr) { entry: %x = load i64 addrspace(1)* %xptr, align 8 diff --git a/test/CodeGen/R600/rotl.ll b/test/CodeGen/R600/rotl.ll index f54c79188d8..6c8e5032447 100644 --- a/test/CodeGen/R600/rotl.ll +++ b/test/CodeGen/R600/rotl.ll @@ -6,9 +6,9 @@ ; R600-NEXT: 32 ; R600: BIT_ALIGN_INT {{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].Z, PV.{{[XYZW]}} -; SI: S_SUB_I32 [[SDST:s[0-9]+]], 32, {{[s][0-9]+}} -; SI: V_MOV_B32_e32 [[VDST:v[0-9]+]], [[SDST]] -; SI: V_ALIGNBIT_B32 {{v[0-9]+, [s][0-9]+, s[0-9]+}}, [[VDST]] +; SI: s_sub_i32 [[SDST:s[0-9]+]], 32, {{[s][0-9]+}} +; SI: v_mov_b32_e32 [[VDST:v[0-9]+]], [[SDST]] +; SI: v_alignbit_b32 {{v[0-9]+, [s][0-9]+, s[0-9]+}}, [[VDST]] define void @rotl_i32(i32 addrspace(1)* %in, i32 %x, i32 %y) { entry: %0 = shl i32 %x, %y @@ -20,11 +20,11 @@ entry: } ; FUNC-LABEL: {{^}}rotl_v2i32: -; SI-DAG: S_SUB_I32 -; SI-DAG: S_SUB_I32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: V_ALIGNBIT_B32 -; SI: S_ENDPGM +; SI-DAG: s_sub_i32 +; SI-DAG: s_sub_i32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_alignbit_b32 +; SI: s_endpgm define void @rotl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) { entry: %0 = shl <2 x i32> %x, %y @@ -36,15 +36,15 @@ entry: } ; FUNC-LABEL: {{^}}rotl_v4i32: -; SI-DAG: S_SUB_I32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: S_SUB_I32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: S_SUB_I32 -; SI-DAG: V_ALIGNBIT_B32 -; SI-DAG: S_SUB_I32 -; SI-DAG: V_ALIGNBIT_B32 -; SI: S_ENDPGM +; SI-DAG: s_sub_i32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: s_sub_i32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: s_sub_i32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: s_sub_i32 +; SI-DAG: v_alignbit_b32 +; SI: s_endpgm define void @rotl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) { entry: %0 = shl <4 x i32> %x, %y diff --git a/test/CodeGen/R600/rotr.i64.ll b/test/CodeGen/R600/rotr.i64.ll index 56910e42b1d..9e145709ff6 100644 --- a/test/CodeGen/R600/rotr.i64.ll +++ b/test/CodeGen/R600/rotr.i64.ll @@ -1,10 +1,10 @@ ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}s_rotr_i64: -; SI-DAG: S_SUB_I32 -; SI-DAG: S_LSHR_B64 -; SI-DAG: S_LSHL_B64 -; SI: S_OR_B64 +; SI-DAG: s_sub_i32 +; SI-DAG: s_lshr_b64 +; SI-DAG: s_lshl_b64 +; SI: s_or_b64 define void @s_rotr_i64(i64 addrspace(1)* %in, i64 %x, i64 %y) { entry: %tmp0 = sub i64 64, %y @@ -16,11 +16,11 @@ entry: } ; FUNC-LABEL: {{^}}v_rotr_i64: -; SI-DAG: V_SUB_I32 -; SI-DAG: V_LSHR_B64 -; SI-DAG: V_LSHL_B64 -; SI: V_OR_B32 -; SI: V_OR_B32 +; SI-DAG: v_sub_i32 +; SI-DAG: v_lshr_b64 +; SI-DAG: v_lshl_b64 +; SI: v_or_b32 +; SI: v_or_b32 define void @v_rotr_i64(i64 addrspace(1)* %in, i64 addrspace(1)* %xptr, i64 addrspace(1)* %yptr) { entry: %x = load i64 addrspace(1)* %xptr, align 8 diff --git a/test/CodeGen/R600/rotr.ll b/test/CodeGen/R600/rotr.ll index 0dd0da08c82..a1add117d8e 100644 --- a/test/CodeGen/R600/rotr.ll +++ b/test/CodeGen/R600/rotr.ll @@ -4,7 +4,7 @@ ; FUNC-LABEL: {{^}}rotr_i32: ; R600: BIT_ALIGN_INT -; SI: V_ALIGNBIT_B32 +; SI: v_alignbit_b32 define void @rotr_i32(i32 addrspace(1)* %in, i32 %x, i32 %y) { entry: %tmp0 = sub i32 32, %y @@ -19,8 +19,8 @@ entry: ; R600: BIT_ALIGN_INT ; R600: BIT_ALIGN_INT -; SI: V_ALIGNBIT_B32 -; SI: V_ALIGNBIT_B32 +; SI: v_alignbit_b32 +; SI: v_alignbit_b32 define void @rotr_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) { entry: %tmp0 = sub <2 x i32> , %y @@ -37,10 +37,10 @@ entry: ; R600: BIT_ALIGN_INT ; R600: BIT_ALIGN_INT -; SI: V_ALIGNBIT_B32 -; SI: V_ALIGNBIT_B32 -; SI: V_ALIGNBIT_B32 -; SI: V_ALIGNBIT_B32 +; SI: v_alignbit_b32 +; SI: v_alignbit_b32 +; SI: v_alignbit_b32 +; SI: v_alignbit_b32 define void @rotr_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) { entry: %tmp0 = sub <4 x i32> , %y diff --git a/test/CodeGen/R600/rsq.ll b/test/CodeGen/R600/rsq.ll index 6b583094787..d792c9fabf4 100644 --- a/test/CodeGen/R600/rsq.ll +++ b/test/CodeGen/R600/rsq.ll @@ -5,8 +5,8 @@ declare float @llvm.sqrt.f32(float) nounwind readnone declare double @llvm.sqrt.f64(double) nounwind readnone ; SI-LABEL: {{^}}rsq_f32: -; SI: V_RSQ_F32_e32 -; SI: S_ENDPGM +; SI: v_rsq_f32_e32 +; SI: s_endpgm define void @rsq_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind { %val = load float addrspace(1)* %in, align 4 %sqrt = call float @llvm.sqrt.f32(float %val) nounwind readnone @@ -16,9 +16,9 @@ define void @rsq_f32(float addrspace(1)* noalias %out, float addrspace(1)* noali } ; SI-LABEL: {{^}}rsq_f64: -; SI-UNSAFE: V_RSQ_F64_e32 -; SI-SAFE: V_SQRT_F64_e32 -; SI: S_ENDPGM +; SI-UNSAFE: v_rsq_f64_e32 +; SI-SAFE: v_sqrt_f64_e32 +; SI: s_endpgm define void @rsq_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) nounwind { %val = load double addrspace(1)* %in, align 4 %sqrt = call double @llvm.sqrt.f64(double %val) nounwind readnone @@ -28,8 +28,8 @@ define void @rsq_f64(double addrspace(1)* noalias %out, double addrspace(1)* noa } ; SI-LABEL: {{^}}rsq_f32_sgpr: -; SI: V_RSQ_F32_e32 {{v[0-9]+}}, {{s[0-9]+}} -; SI: S_ENDPGM +; SI: v_rsq_f32_e32 {{v[0-9]+}}, {{s[0-9]+}} +; SI: s_endpgm define void @rsq_f32_sgpr(float addrspace(1)* noalias %out, float %val) nounwind { %sqrt = call float @llvm.sqrt.f32(float %val) nounwind readnone %div = fdiv float 1.0, %sqrt diff --git a/test/CodeGen/R600/saddo.ll b/test/CodeGen/R600/saddo.ll index 93f3c74d4e3..654967cc178 100644 --- a/test/CodeGen/R600/saddo.ll +++ b/test/CodeGen/R600/saddo.ll @@ -48,8 +48,8 @@ define void @s_saddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 } ; FUNC-LABEL: {{^}}v_saddo_i64: -; SI: V_ADD_I32 -; SI: V_ADDC_U32 +; SI: v_add_i32 +; SI: v_addc_u32 define void @v_saddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind { %a = load i64 addrspace(1)* %aptr, align 4 %b = load i64 addrspace(1)* %bptr, align 4 diff --git a/test/CodeGen/R600/salu-to-valu.ll b/test/CodeGen/R600/salu-to-valu.ll index ba983196968..23af3e4b87e 100644 --- a/test/CodeGen/R600/salu-to-valu.ll +++ b/test/CodeGen/R600/salu-to-valu.ll @@ -9,13 +9,13 @@ ; CHECK-LABEL: {{^}}mubuf: -; Make sure we aren't using VGPRs for the source operand of S_MOV_B64 -; CHECK-NOT: S_MOV_B64 s[{{[0-9]+:[0-9]+}}], v +; Make sure we aren't using VGPRs for the source operand of s_mov_b64 +; CHECK-NOT: s_mov_b64 s[{{[0-9]+:[0-9]+}}], v ; Make sure we aren't using VGPR's for the srsrc operand of BUFFER_LOAD_* ; instructions -; CHECK: BUFFER_LOAD_UBYTE v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 -; CHECK: BUFFER_LOAD_UBYTE v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 +; CHECK: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 +; CHECK: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 define void @mubuf(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { entry: %0 = call i32 @llvm.r600.read.tidig.x() #1 @@ -50,8 +50,8 @@ attributes #1 = { nounwind readnone } ; Test moving an SMRD instruction to the VALU ; CHECK-LABEL: {{^}}smrd_valu: -; CHECK: BUFFER_LOAD_DWORD [[OUT:v[0-9]+]] -; CHECK: BUFFER_STORE_DWORD [[OUT]] +; CHECK: buffer_load_dword [[OUT:v[0-9]+]] +; CHECK: buffer_store_dword [[OUT]] define void @smrd_valu(i32 addrspace(2)* addrspace(1)* %in, i32 %a, i32 addrspace(1)* %out) { entry: @@ -78,7 +78,7 @@ endif: ; Test moving ann SMRD with an immediate offset to the VALU ; CHECK-LABEL: {{^}}smrd_valu2: -; CHECK: BUFFER_LOAD_DWORD +; CHECK: buffer_load_dword define void @smrd_valu2(i32 addrspace(1)* %out, [8 x i32] addrspace(2)* %in) { entry: %0 = call i32 @llvm.r600.read.tidig.x() nounwind readnone @@ -90,8 +90,8 @@ entry: } ; CHECK-LABEL: {{^}}s_load_imm_v8i32: -; CHECK: BUFFER_LOAD_DWORDX4 -; CHECK: BUFFER_LOAD_DWORDX4 +; CHECK: buffer_load_dwordx4 +; CHECK: buffer_load_dwordx4 define void @s_load_imm_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) { entry: %tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1 @@ -103,10 +103,10 @@ entry: } ; CHECK-LABEL: {{^}}s_load_imm_v16i32: -; CHECK: BUFFER_LOAD_DWORDX4 -; CHECK: BUFFER_LOAD_DWORDX4 -; CHECK: BUFFER_LOAD_DWORDX4 -; CHECK: BUFFER_LOAD_DWORDX4 +; CHECK: buffer_load_dwordx4 +; CHECK: buffer_load_dwordx4 +; CHECK: buffer_load_dwordx4 +; CHECK: buffer_load_dwordx4 define void @s_load_imm_v16i32(<16 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) { entry: %tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1 diff --git a/test/CodeGen/R600/scalar_to_vector.ll b/test/CodeGen/R600/scalar_to_vector.ll index d67cbaf1fed..dc9ebe0d327 100644 --- a/test/CodeGen/R600/scalar_to_vector.ll +++ b/test/CodeGen/R600/scalar_to_vector.ll @@ -2,13 +2,13 @@ ; FUNC-LABEL: {{^}}scalar_to_vector_v2i32: -; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]], -; SI: V_LSHRREV_B32_e32 [[RESULT:v[0-9]+]], 16, [[VAL]] -; SI: BUFFER_STORE_SHORT [[RESULT]] -; SI: BUFFER_STORE_SHORT [[RESULT]] -; SI: BUFFER_STORE_SHORT [[RESULT]] -; SI: BUFFER_STORE_SHORT [[RESULT]] -; SI: S_ENDPGM +; SI: buffer_load_dword [[VAL:v[0-9]+]], +; SI: v_lshrrev_b32_e32 [[RESULT:v[0-9]+]], 16, [[VAL]] +; SI: buffer_store_short [[RESULT]] +; SI: buffer_store_short [[RESULT]] +; SI: buffer_store_short [[RESULT]] +; SI: buffer_store_short [[RESULT]] +; SI: s_endpgm define void @scalar_to_vector_v2i32(<4 x i16> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %tmp1 = load i32 addrspace(1)* %in, align 4 %bc = bitcast i32 %tmp1 to <2 x i16> @@ -18,13 +18,13 @@ define void @scalar_to_vector_v2i32(<4 x i16> addrspace(1)* %out, i32 addrspace( } ; FUNC-LABEL: {{^}}scalar_to_vector_v2f32: -; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]], -; SI: V_LSHRREV_B32_e32 [[RESULT:v[0-9]+]], 16, [[VAL]] -; SI: BUFFER_STORE_SHORT [[RESULT]] -; SI: BUFFER_STORE_SHORT [[RESULT]] -; SI: BUFFER_STORE_SHORT [[RESULT]] -; SI: BUFFER_STORE_SHORT [[RESULT]] -; SI: S_ENDPGM +; SI: buffer_load_dword [[VAL:v[0-9]+]], +; SI: v_lshrrev_b32_e32 [[RESULT:v[0-9]+]], 16, [[VAL]] +; SI: buffer_store_short [[RESULT]] +; SI: buffer_store_short [[RESULT]] +; SI: buffer_store_short [[RESULT]] +; SI: buffer_store_short [[RESULT]] +; SI: s_endpgm define void @scalar_to_vector_v2f32(<4 x i16> addrspace(1)* %out, float addrspace(1)* %in) nounwind { %tmp1 = load float addrspace(1)* %in, align 4 %bc = bitcast float %tmp1 to <2 x i16> diff --git a/test/CodeGen/R600/schedule-global-loads.ll b/test/CodeGen/R600/schedule-global-loads.ll index 5ee1e821b78..5422ca75b86 100644 --- a/test/CodeGen/R600/schedule-global-loads.ll +++ b/test/CodeGen/R600/schedule-global-loads.ll @@ -9,10 +9,10 @@ declare i32 @llvm.r600.read.tidig.x() #1 ; ordering the loads so that the lower address loads come first. ; FUNC-LABEL: {{^}}cluster_global_arg_loads: -; SI-DAG: BUFFER_LOAD_DWORD [[REG0:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} -; SI-DAG: BUFFER_LOAD_DWORD [[REG1:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:0x4 -; SI: BUFFER_STORE_DWORD [[REG0]] -; SI: BUFFER_STORE_DWORD [[REG1]] +; SI-DAG: buffer_load_dword [[REG0:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; SI-DAG: buffer_load_dword [[REG1:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:0x4 +; SI: buffer_store_dword [[REG0]] +; SI: buffer_store_dword [[REG1]] define void @cluster_global_arg_loads(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %ptr) #0 { %load0 = load i32 addrspace(1)* %ptr, align 4 %gep = getelementptr i32 addrspace(1)* %ptr, i32 1 @@ -25,8 +25,8 @@ define void @cluster_global_arg_loads(i32 addrspace(1)* %out0, i32 addrspace(1)* ; Test for a crach in SIInstrInfo::areLoadsFromSameBasePtr() when checking ; an MUBUF load which does not have a vaddr operand. ; FUNC-LABEL: {{^}}same_base_ptr_crash: -; SI: BUFFER_LOAD_DWORD -; SI: BUFFER_LOAD_DWORD +; SI: buffer_load_dword +; SI: buffer_load_dword define void @same_base_ptr_crash(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %offset) { entry: %out1 = getelementptr i32 addrspace(1)* %out, i32 %offset diff --git a/test/CodeGen/R600/schedule-kernel-arg-loads.ll b/test/CodeGen/R600/schedule-kernel-arg-loads.ll index 01bef00419c..e7741575208 100644 --- a/test/CodeGen/R600/schedule-kernel-arg-loads.ll +++ b/test/CodeGen/R600/schedule-kernel-arg-loads.ll @@ -1,10 +1,10 @@ ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s ; FUNC-LABEL: {{^}}cluster_arg_loads: -; SI: S_LOAD_DWORDX2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x9 -; SI-NEXT: S_LOAD_DWORDX2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-NEXT: S_LOAD_DWORD s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI-NEXT: S_LOAD_DWORD s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xe +; SI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x9 +; SI-NEXT: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd +; SI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xe define void @cluster_arg_loads(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 %x, i32 %y) nounwind { store i32 %x, i32 addrspace(1)* %out0, align 4 store i32 %y, i32 addrspace(1)* %out1, align 4 diff --git a/test/CodeGen/R600/sdiv.ll b/test/CodeGen/R600/sdiv.ll index d964530d688..16853e07aec 100644 --- a/test/CodeGen/R600/sdiv.ll +++ b/test/CodeGen/R600/sdiv.ll @@ -33,15 +33,15 @@ define void @sdiv_i32_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ; working. ; FUNC-LABEL: {{^}}slow_sdiv_i32_3435: -; SI: BUFFER_LOAD_DWORD [[VAL:v[0-9]+]], -; SI: V_MOV_B32_e32 [[MAGIC:v[0-9]+]], 0x98a1930b -; SI: V_MUL_HI_I32 [[TMP:v[0-9]+]], [[VAL]], [[MAGIC]] -; SI: V_ADD_I32 -; SI: V_LSHRREV_B32 -; SI: V_ASHRREV_I32 -; SI: V_ADD_I32 -; SI: BUFFER_STORE_DWORD -; SI: S_ENDPGM +; SI: buffer_load_dword [[VAL:v[0-9]+]], +; SI: v_mov_b32_e32 [[MAGIC:v[0-9]+]], 0x98a1930b +; SI: v_mul_hi_i32 [[TMP:v[0-9]+]], [[VAL]], [[MAGIC]] +; SI: v_add_i32 +; SI: v_lshrrev_b32 +; SI: v_ashrrev_i32 +; SI: v_add_i32 +; SI: buffer_store_dword +; SI: s_endpgm define void @slow_sdiv_i32_3435(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %num = load i32 addrspace(1) * %in %result = sdiv i32 %num, 3435 diff --git a/test/CodeGen/R600/sdivrem24.ll b/test/CodeGen/R600/sdivrem24.ll index 19c451c1d08..228cf762f16 100644 --- a/test/CodeGen/R600/sdivrem24.ll +++ b/test/CodeGen/R600/sdivrem24.ll @@ -2,10 +2,10 @@ ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}sdiv24_i8: -; SI: V_CVT_F32_I32 -; SI: V_CVT_F32_I32 -; SI: V_RCP_F32 -; SI: V_CVT_I32_F32 +; SI: v_cvt_f32_i32 +; SI: v_cvt_f32_i32 +; SI: v_rcp_f32 +; SI: v_cvt_i32_f32 ; EG: INT_TO_FLT ; EG-DAG: INT_TO_FLT @@ -21,10 +21,10 @@ define void @sdiv24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}sdiv24_i16: -; SI: V_CVT_F32_I32 -; SI: V_CVT_F32_I32 -; SI: V_RCP_F32 -; SI: V_CVT_I32_F32 +; SI: v_cvt_f32_i32 +; SI: v_cvt_f32_i32 +; SI: v_rcp_f32 +; SI: v_cvt_i32_f32 ; EG: INT_TO_FLT ; EG-DAG: INT_TO_FLT @@ -40,10 +40,10 @@ define void @sdiv24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}sdiv24_i32: -; SI: V_CVT_F32_I32 -; SI: V_CVT_F32_I32 -; SI: V_RCP_F32 -; SI: V_CVT_I32_F32 +; SI: v_cvt_f32_i32 +; SI: v_cvt_f32_i32 +; SI: v_rcp_f32 +; SI: v_cvt_i32_f32 ; EG: INT_TO_FLT ; EG-DAG: INT_TO_FLT @@ -63,8 +63,8 @@ define void @sdiv24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}sdiv25_i32: -; SI-NOT: V_CVT_F32_I32 -; SI-NOT: V_RCP_F32 +; SI-NOT: v_cvt_f32_i32 +; SI-NOT: v_rcp_f32 ; EG-NOT: INT_TO_FLT ; EG-NOT: RECIP_IEEE @@ -82,8 +82,8 @@ define void @sdiv25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}test_no_sdiv24_i32_1: -; SI-NOT: V_CVT_F32_I32 -; SI-NOT: V_RCP_F32 +; SI-NOT: v_cvt_f32_i32 +; SI-NOT: v_rcp_f32 ; EG-NOT: INT_TO_FLT ; EG-NOT: RECIP_IEEE @@ -101,8 +101,8 @@ define void @test_no_sdiv24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) } ; FUNC-LABEL: {{^}}test_no_sdiv24_i32_2: -; SI-NOT: V_CVT_F32_I32 -; SI-NOT: V_RCP_F32 +; SI-NOT: v_cvt_f32_i32 +; SI-NOT: v_rcp_f32 ; EG-NOT: INT_TO_FLT ; EG-NOT: RECIP_IEEE @@ -120,10 +120,10 @@ define void @test_no_sdiv24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) } ; FUNC-LABEL: {{^}}srem24_i8: -; SI: V_CVT_F32_I32 -; SI: V_CVT_F32_I32 -; SI: V_RCP_F32 -; SI: V_CVT_I32_F32 +; SI: v_cvt_f32_i32 +; SI: v_cvt_f32_i32 +; SI: v_rcp_f32 +; SI: v_cvt_i32_f32 ; EG: INT_TO_FLT ; EG-DAG: INT_TO_FLT @@ -139,10 +139,10 @@ define void @srem24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}srem24_i16: -; SI: V_CVT_F32_I32 -; SI: V_CVT_F32_I32 -; SI: V_RCP_F32 -; SI: V_CVT_I32_F32 +; SI: v_cvt_f32_i32 +; SI: v_cvt_f32_i32 +; SI: v_rcp_f32 +; SI: v_cvt_i32_f32 ; EG: INT_TO_FLT ; EG-DAG: INT_TO_FLT @@ -158,10 +158,10 @@ define void @srem24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}srem24_i32: -; SI: V_CVT_F32_I32 -; SI: V_CVT_F32_I32 -; SI: V_RCP_F32 -; SI: V_CVT_I32_F32 +; SI: v_cvt_f32_i32 +; SI: v_cvt_f32_i32 +; SI: v_rcp_f32 +; SI: v_cvt_i32_f32 ; EG: INT_TO_FLT ; EG-DAG: INT_TO_FLT @@ -181,8 +181,8 @@ define void @srem24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}srem25_i32: -; SI-NOT: V_CVT_F32_I32 -; SI-NOT: V_RCP_F32 +; SI-NOT: v_cvt_f32_i32 +; SI-NOT: v_rcp_f32 ; EG-NOT: INT_TO_FLT ; EG-NOT: RECIP_IEEE @@ -200,8 +200,8 @@ define void @srem25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}test_no_srem24_i32_1: -; SI-NOT: V_CVT_F32_I32 -; SI-NOT: V_RCP_F32 +; SI-NOT: v_cvt_f32_i32 +; SI-NOT: v_rcp_f32 ; EG-NOT: INT_TO_FLT ; EG-NOT: RECIP_IEEE @@ -219,8 +219,8 @@ define void @test_no_srem24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) } ; FUNC-LABEL: {{^}}test_no_srem24_i32_2: -; SI-NOT: V_CVT_F32_I32 -; SI-NOT: V_RCP_F32 +; SI-NOT: v_cvt_f32_i32 +; SI-NOT: v_rcp_f32 ; EG-NOT: INT_TO_FLT ; EG-NOT: RECIP_IEEE diff --git a/test/CodeGen/R600/select-i1.ll b/test/CodeGen/R600/select-i1.ll index af9534f9765..2e2d0e4ec0b 100644 --- a/test/CodeGen/R600/select-i1.ll +++ b/test/CodeGen/R600/select-i1.ll @@ -3,8 +3,8 @@ ; FIXME: This should go in existing select.ll test, except the current testcase there is broken on SI ; FUNC-LABEL: {{^}}select_i1: -; SI: V_CNDMASK_B32 -; SI-NOT: V_CNDMASK_B32 +; SI: v_cndmask_b32 +; SI-NOT: v_cndmask_b32 define void @select_i1(i1 addrspace(1)* %out, i32 %cond, i1 %a, i1 %b) nounwind { %cmp = icmp ugt i32 %cond, 5 %sel = select i1 %cmp, i1 %a, i1 %b diff --git a/test/CodeGen/R600/select-vectors.ll b/test/CodeGen/R600/select-vectors.ll index 00758399a11..7d8df2edf06 100644 --- a/test/CodeGen/R600/select-vectors.ll +++ b/test/CodeGen/R600/select-vectors.ll @@ -5,10 +5,10 @@ ; FUNC-LABEL: {{^}}select_v4i8: -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 define void @select_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, <4 x i8> %b, i8 %c) nounwind { %cmp = icmp eq i8 %c, 0 %select = select i1 %cmp, <4 x i8> %a, <4 x i8> %b @@ -17,10 +17,10 @@ define void @select_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, <4 x i8> %b, } ; FUNC-LABEL: {{^}}select_v4i16: -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 define void @select_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %a, <4 x i16> %b, i32 %c) nounwind { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <4 x i16> %a, <4 x i16> %b @@ -29,9 +29,9 @@ define void @select_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %a, <4 x i16> } ; FUNC-LABEL: {{^}}select_v2i32: -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: BUFFER_STORE_DWORDX2 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: buffer_store_dwordx2 define void @select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b, i32 %c) nounwind { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <2 x i32> %a, <2 x i32> %b @@ -40,11 +40,11 @@ define void @select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> } ; FUNC-LABEL: {{^}}select_v4i32: -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: BUFFER_STORE_DWORDX4 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: buffer_store_dwordx4 define void @select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, i32 %c) nounwind { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <4 x i32> %a, <4 x i32> %b @@ -53,14 +53,14 @@ define void @select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> } ; FUNC-LABEL: {{^}}select_v8i32: -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 define void @select_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b, i32 %c) nounwind { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <8 x i32> %a, <8 x i32> %b @@ -69,7 +69,7 @@ define void @select_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> } ; FUNC-LABEL: {{^}}select_v2f32: -; SI: BUFFER_STORE_DWORDX2 +; SI: buffer_store_dwordx2 define void @select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) nounwind { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <2 x float> %a, <2 x float> %b @@ -78,7 +78,7 @@ define void @select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x f } ; FUNC-LABEL: {{^}}select_v4f32: -; SI: BUFFER_STORE_DWORDX4 +; SI: buffer_store_dwordx4 define void @select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b, i32 %c) nounwind { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <4 x float> %a, <4 x float> %b @@ -87,14 +87,14 @@ define void @select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x f } ; FUNC-LABEL: {{^}}select_v8f32: -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 define void @select_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b, i32 %c) nounwind { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <8 x float> %a, <8 x float> %b @@ -103,10 +103,10 @@ define void @select_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x f } ; FUNC-LABEL: {{^}}select_v2f64: -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 define void @select_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b, i32 %c) nounwind { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <2 x double> %a, <2 x double> %b @@ -115,14 +115,14 @@ define void @select_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x } ; FUNC-LABEL: {{^}}select_v4f64: -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 define void @select_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b, i32 %c) nounwind { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <4 x double> %a, <4 x double> %b @@ -131,22 +131,22 @@ define void @select_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, <4 x } ; FUNC-LABEL: {{^}}select_v8f64: -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 define void @select_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b, i32 %c) nounwind { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <8 x double> %a, <8 x double> %b diff --git a/test/CodeGen/R600/select64.ll b/test/CodeGen/R600/select64.ll index 1bc01daee1c..8de34d521a5 100644 --- a/test/CodeGen/R600/select64.ll +++ b/test/CodeGen/R600/select64.ll @@ -3,9 +3,9 @@ ; CHECK-LABEL: {{^}}select0: ; i64 select should be split into two i32 selects, and we shouldn't need ; to use a shfit to extract the hi dword of the input. -; CHECK-NOT: S_LSHR_B64 -; CHECK: V_CNDMASK -; CHECK: V_CNDMASK +; CHECK-NOT: s_lshr_b64 +; CHECK: v_cndmask +; CHECK: v_cndmask define void @select0(i64 addrspace(1)* %out, i32 %cond, i64 %in) { entry: %0 = icmp ugt i32 %cond, 5 @@ -15,8 +15,8 @@ entry: } ; CHECK-LABEL: {{^}}select_trunc_i64: -; CHECK: V_CNDMASK_B32 -; CHECK-NOT: V_CNDMASK_B32 +; CHECK: v_cndmask_b32 +; CHECK-NOT: v_cndmask_b32 define void @select_trunc_i64(i32 addrspace(1)* %out, i32 %cond, i64 %in) nounwind { %cmp = icmp ugt i32 %cond, 5 %sel = select i1 %cmp, i64 0, i64 %in @@ -26,8 +26,8 @@ define void @select_trunc_i64(i32 addrspace(1)* %out, i32 %cond, i64 %in) nounwi } ; CHECK-LABEL: {{^}}select_trunc_i64_2: -; CHECK: V_CNDMASK_B32 -; CHECK-NOT: V_CNDMASK_B32 +; CHECK: v_cndmask_b32 +; CHECK-NOT: v_cndmask_b32 define void @select_trunc_i64_2(i32 addrspace(1)* %out, i32 %cond, i64 %a, i64 %b) nounwind { %cmp = icmp ugt i32 %cond, 5 %sel = select i1 %cmp, i64 %a, i64 %b @@ -37,8 +37,8 @@ define void @select_trunc_i64_2(i32 addrspace(1)* %out, i32 %cond, i64 %a, i64 % } ; CHECK-LABEL: {{^}}v_select_trunc_i64_2: -; CHECK: V_CNDMASK_B32 -; CHECK-NOT: V_CNDMASK_B32 +; CHECK: v_cndmask_b32 +; CHECK-NOT: v_cndmask_b32 define void @v_select_trunc_i64_2(i32 addrspace(1)* %out, i32 %cond, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind { %cmp = icmp ugt i32 %cond, 5 %a = load i64 addrspace(1)* %aptr, align 8 diff --git a/test/CodeGen/R600/selectcc-opt.ll b/test/CodeGen/R600/selectcc-opt.ll index 5bcd11e9963..82577bb4289 100644 --- a/test/CodeGen/R600/selectcc-opt.ll +++ b/test/CodeGen/R600/selectcc-opt.ll @@ -67,10 +67,10 @@ entry: } ; FUNC-LABEL: {{^}}selectcc_bool: -; SI: V_CMP_NE_I32 -; SI-NEXT: V_CNDMASK_B32_e64 -; SI-NOT: CMP -; SI-NOT: CNDMASK +; SI: v_cmp_ne_i32 +; SI-NEXT: v_cndmask_b32_e64 +; SI-NOT: cmp +; SI-NOT: cndmask define void @selectcc_bool(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %icmp0 = icmp ne i32 %a, %b %ext = select i1 %icmp0, i32 -1, i32 0 diff --git a/test/CodeGen/R600/selectcc.ll b/test/CodeGen/R600/selectcc.ll index 6625691312e..5a09b5cee24 100644 --- a/test/CodeGen/R600/selectcc.ll +++ b/test/CodeGen/R600/selectcc.ll @@ -7,9 +7,9 @@ ; EG: OR_INT ; EG: CNDE_INT ; EG: CNDE_INT -; SI: V_CMP_EQ_I64 -; SI: V_CNDMASK -; SI: V_CNDMASK +; SI: v_cmp_eq_i64 +; SI: v_cndmask +; SI: v_cndmask define void @selectcc_i64(i64 addrspace(1) * %out, i64 %lhs, i64 %rhs, i64 %true, i64 %false) { entry: %0 = icmp eq i64 %lhs, %rhs diff --git a/test/CodeGen/R600/setcc-opt.ll b/test/CodeGen/R600/setcc-opt.ll index 0ed60109516..af48df88e5b 100644 --- a/test/CodeGen/R600/setcc-opt.ll +++ b/test/CodeGen/R600/setcc-opt.ll @@ -1,11 +1,11 @@ ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; SI-LABEL: {{^}}sext_bool_icmp_ne: -; SI: V_CMP_NE_I32 -; SI-NEXT: V_CNDMASK_B32 -; SI-NOT: V_CMP_NE_I32 -; SI-NOT: V_CNDMASK_B32 -; SI: S_ENDPGM +; SI: v_cmp_ne_i32 +; SI-NEXT: v_cndmask_b32 +; SI-NOT: v_cmp_ne_i32 +; SI-NOT: v_cndmask_b32 +; SI: s_endpgm define void @sext_bool_icmp_ne(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %icmp0 = icmp ne i32 %a, %b %ext = sext i1 %icmp0 to i32 diff --git a/test/CodeGen/R600/setcc.ll b/test/CodeGen/R600/setcc.ll index 351adf9185c..8dd2ce4eb4f 100644 --- a/test/CodeGen/R600/setcc.ll +++ b/test/CodeGen/R600/setcc.ll @@ -34,7 +34,7 @@ define void @setcc_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* % ; FUNC-LABEL: {{^}}f32_oeq: ; R600: SETE_DX10 -; SI: V_CMP_EQ_F32 +; SI: v_cmp_eq_f32 define void @f32_oeq(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp oeq float %a, %b @@ -45,7 +45,7 @@ entry: ; FUNC-LABEL: {{^}}f32_ogt: ; R600: SETGT_DX10 -; SI: V_CMP_GT_F32 +; SI: v_cmp_gt_f32 define void @f32_ogt(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp ogt float %a, %b @@ -56,7 +56,7 @@ entry: ; FUNC-LABEL: {{^}}f32_oge: ; R600: SETGE_DX10 -; SI: V_CMP_GE_F32 +; SI: v_cmp_ge_f32 define void @f32_oge(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp oge float %a, %b @@ -67,7 +67,7 @@ entry: ; FUNC-LABEL: {{^}}f32_olt: ; R600: SETGT_DX10 -; SI: V_CMP_LT_F32 +; SI: v_cmp_lt_f32 define void @f32_olt(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp olt float %a, %b @@ -78,7 +78,7 @@ entry: ; FUNC-LABEL: {{^}}f32_ole: ; R600: SETGE_DX10 -; SI: V_CMP_LE_F32 +; SI: v_cmp_le_f32 define void @f32_ole(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp ole float %a, %b @@ -94,11 +94,11 @@ entry: ; R600-DAG: SETNE_DX10 ; R600-DAG: AND_INT ; R600-DAG: SETNE_INT -; SI: V_CMP_O_F32 -; SI: V_CMP_NEQ_F32 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_AND_B32_e32 +; SI: v_cmp_o_f32 +; SI: v_cmp_neq_f32 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_and_b32_e32 define void @f32_one(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp one float %a, %b @@ -112,7 +112,7 @@ entry: ; R600-DAG: SETE_DX10 ; R600-DAG: AND_INT ; R600-DAG: SETNE_INT -; SI: V_CMP_O_F32 +; SI: v_cmp_o_f32 define void @f32_ord(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp ord float %a, %b @@ -128,11 +128,11 @@ entry: ; R600-DAG: SETE_DX10 ; R600-DAG: OR_INT ; R600-DAG: SETNE_INT -; SI: V_CMP_U_F32 -; SI: V_CMP_EQ_F32 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_OR_B32_e32 +; SI: v_cmp_u_f32 +; SI: v_cmp_eq_f32 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_or_b32_e32 define void @f32_ueq(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp ueq float %a, %b @@ -144,11 +144,11 @@ entry: ; FUNC-LABEL: {{^}}f32_ugt: ; R600: SETGE ; R600: SETE_DX10 -; SI: V_CMP_U_F32 -; SI: V_CMP_GT_F32 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_OR_B32_e32 +; SI: v_cmp_u_f32 +; SI: v_cmp_gt_f32 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_or_b32_e32 define void @f32_ugt(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp ugt float %a, %b @@ -160,11 +160,11 @@ entry: ; FUNC-LABEL: {{^}}f32_uge: ; R600: SETGT ; R600: SETE_DX10 -; SI: V_CMP_U_F32 -; SI: V_CMP_GE_F32 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_OR_B32_e32 +; SI: v_cmp_u_f32 +; SI: v_cmp_ge_f32 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_or_b32_e32 define void @f32_uge(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp uge float %a, %b @@ -176,11 +176,11 @@ entry: ; FUNC-LABEL: {{^}}f32_ult: ; R600: SETGE ; R600: SETE_DX10 -; SI: V_CMP_U_F32 -; SI: V_CMP_LT_F32 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_OR_B32_e32 +; SI: v_cmp_u_f32 +; SI: v_cmp_lt_f32 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_or_b32_e32 define void @f32_ult(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp ult float %a, %b @@ -192,11 +192,11 @@ entry: ; FUNC-LABEL: {{^}}f32_ule: ; R600: SETGT ; R600: SETE_DX10 -; SI: V_CMP_U_F32 -; SI: V_CMP_LE_F32 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_OR_B32_e32 +; SI: v_cmp_u_f32 +; SI: v_cmp_le_f32 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_or_b32_e32 define void @f32_ule(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp ule float %a, %b @@ -207,7 +207,7 @@ entry: ; FUNC-LABEL: {{^}}f32_une: ; R600: SETNE_DX10 -; SI: V_CMP_NEQ_F32 +; SI: v_cmp_neq_f32 define void @f32_une(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp une float %a, %b @@ -221,7 +221,7 @@ entry: ; R600: SETNE_DX10 ; R600: OR_INT ; R600: SETNE_INT -; SI: V_CMP_U_F32 +; SI: v_cmp_u_f32 define void @f32_uno(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp uno float %a, %b @@ -236,7 +236,7 @@ entry: ; FUNC-LABEL: {{^}}i32_eq: ; R600: SETE_INT -; SI: V_CMP_EQ_I32 +; SI: v_cmp_eq_i32 define void @i32_eq(i32 addrspace(1)* %out, i32 %a, i32 %b) { entry: %0 = icmp eq i32 %a, %b @@ -247,7 +247,7 @@ entry: ; FUNC-LABEL: {{^}}i32_ne: ; R600: SETNE_INT -; SI: V_CMP_NE_I32 +; SI: v_cmp_ne_i32 define void @i32_ne(i32 addrspace(1)* %out, i32 %a, i32 %b) { entry: %0 = icmp ne i32 %a, %b @@ -258,7 +258,7 @@ entry: ; FUNC-LABEL: {{^}}i32_ugt: ; R600: SETGT_UINT -; SI: V_CMP_GT_U32 +; SI: v_cmp_gt_u32 define void @i32_ugt(i32 addrspace(1)* %out, i32 %a, i32 %b) { entry: %0 = icmp ugt i32 %a, %b @@ -269,7 +269,7 @@ entry: ; FUNC-LABEL: {{^}}i32_uge: ; R600: SETGE_UINT -; SI: V_CMP_GE_U32 +; SI: v_cmp_ge_u32 define void @i32_uge(i32 addrspace(1)* %out, i32 %a, i32 %b) { entry: %0 = icmp uge i32 %a, %b @@ -280,7 +280,7 @@ entry: ; FUNC-LABEL: {{^}}i32_ult: ; R600: SETGT_UINT -; SI: V_CMP_LT_U32 +; SI: v_cmp_lt_u32 define void @i32_ult(i32 addrspace(1)* %out, i32 %a, i32 %b) { entry: %0 = icmp ult i32 %a, %b @@ -291,7 +291,7 @@ entry: ; FUNC-LABEL: {{^}}i32_ule: ; R600: SETGE_UINT -; SI: V_CMP_LE_U32 +; SI: v_cmp_le_u32 define void @i32_ule(i32 addrspace(1)* %out, i32 %a, i32 %b) { entry: %0 = icmp ule i32 %a, %b @@ -302,7 +302,7 @@ entry: ; FUNC-LABEL: {{^}}i32_sgt: ; R600: SETGT_INT -; SI: V_CMP_GT_I32 +; SI: v_cmp_gt_i32 define void @i32_sgt(i32 addrspace(1)* %out, i32 %a, i32 %b) { entry: %0 = icmp sgt i32 %a, %b @@ -313,7 +313,7 @@ entry: ; FUNC-LABEL: {{^}}i32_sge: ; R600: SETGE_INT -; SI: V_CMP_GE_I32 +; SI: v_cmp_ge_i32 define void @i32_sge(i32 addrspace(1)* %out, i32 %a, i32 %b) { entry: %0 = icmp sge i32 %a, %b @@ -324,7 +324,7 @@ entry: ; FUNC-LABEL: {{^}}i32_slt: ; R600: SETGT_INT -; SI: V_CMP_LT_I32 +; SI: v_cmp_lt_i32 define void @i32_slt(i32 addrspace(1)* %out, i32 %a, i32 %b) { entry: %0 = icmp slt i32 %a, %b @@ -335,7 +335,7 @@ entry: ; FUNC-LABEL: {{^}}i32_sle: ; R600: SETGE_INT -; SI: V_CMP_LE_I32 +; SI: v_cmp_le_i32 define void @i32_sle(i32 addrspace(1)* %out, i32 %a, i32 %b) { entry: %0 = icmp sle i32 %a, %b diff --git a/test/CodeGen/R600/setcc64.ll b/test/CodeGen/R600/setcc64.ll index fd75e175486..6e43172b1cb 100644 --- a/test/CodeGen/R600/setcc64.ll +++ b/test/CodeGen/R600/setcc64.ll @@ -7,7 +7,7 @@ ;;;==========================================================================;;; ; FUNC-LABEL: {{^}}f64_oeq: -; SI: V_CMP_EQ_F64 +; SI: v_cmp_eq_f64 define void @f64_oeq(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp oeq double %a, %b @@ -17,7 +17,7 @@ entry: } ; FUNC-LABEL: {{^}}f64_ogt: -; SI: V_CMP_GT_F64 +; SI: v_cmp_gt_f64 define void @f64_ogt(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp ogt double %a, %b @@ -27,7 +27,7 @@ entry: } ; FUNC-LABEL: {{^}}f64_oge: -; SI: V_CMP_GE_F64 +; SI: v_cmp_ge_f64 define void @f64_oge(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp oge double %a, %b @@ -37,7 +37,7 @@ entry: } ; FUNC-LABEL: {{^}}f64_olt: -; SI: V_CMP_LT_F64 +; SI: v_cmp_lt_f64 define void @f64_olt(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp olt double %a, %b @@ -47,7 +47,7 @@ entry: } ; FUNC-LABEL: {{^}}f64_ole: -; SI: V_CMP_LE_F64 +; SI: v_cmp_le_f64 define void @f64_ole(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp ole double %a, %b @@ -57,11 +57,11 @@ entry: } ; FUNC-LABEL: {{^}}f64_one: -; SI: V_CMP_O_F64 -; SI: V_CMP_NEQ_F64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_AND_B32_e32 +; SI: v_cmp_o_f64 +; SI: v_cmp_neq_f64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_and_b32_e32 define void @f64_one(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp one double %a, %b @@ -71,7 +71,7 @@ entry: } ; FUNC-LABEL: {{^}}f64_ord: -; SI: V_CMP_O_F64 +; SI: v_cmp_o_f64 define void @f64_ord(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp ord double %a, %b @@ -81,11 +81,11 @@ entry: } ; FUNC-LABEL: {{^}}f64_ueq: -; SI: V_CMP_U_F64 -; SI: V_CMP_EQ_F64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_OR_B32_e32 +; SI: v_cmp_u_f64 +; SI: v_cmp_eq_f64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_or_b32_e32 define void @f64_ueq(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp ueq double %a, %b @@ -95,11 +95,11 @@ entry: } ; FUNC-LABEL: {{^}}f64_ugt: -; SI: V_CMP_U_F64 -; SI: V_CMP_GT_F64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_OR_B32_e32 +; SI: v_cmp_u_f64 +; SI: v_cmp_gt_f64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_or_b32_e32 define void @f64_ugt(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp ugt double %a, %b @@ -109,11 +109,11 @@ entry: } ; FUNC-LABEL: {{^}}f64_uge: -; SI: V_CMP_U_F64 -; SI: V_CMP_GE_F64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_OR_B32_e32 +; SI: v_cmp_u_f64 +; SI: v_cmp_ge_f64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_or_b32_e32 define void @f64_uge(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp uge double %a, %b @@ -123,11 +123,11 @@ entry: } ; FUNC-LABEL: {{^}}f64_ult: -; SI: V_CMP_U_F64 -; SI: V_CMP_LT_F64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_OR_B32_e32 +; SI: v_cmp_u_f64 +; SI: v_cmp_lt_f64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_or_b32_e32 define void @f64_ult(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp ult double %a, %b @@ -137,11 +137,11 @@ entry: } ; FUNC-LABEL: {{^}}f64_ule: -; SI: V_CMP_U_F64 -; SI: V_CMP_LE_F64 -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: V_OR_B32_e32 +; SI: v_cmp_u_f64 +; SI: v_cmp_le_f64 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: v_or_b32_e32 define void @f64_ule(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp ule double %a, %b @@ -151,7 +151,7 @@ entry: } ; FUNC-LABEL: {{^}}f64_une: -; SI: V_CMP_NEQ_F64 +; SI: v_cmp_neq_f64 define void @f64_une(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp une double %a, %b @@ -161,7 +161,7 @@ entry: } ; FUNC-LABEL: {{^}}f64_uno: -; SI: V_CMP_U_F64 +; SI: v_cmp_u_f64 define void @f64_uno(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp uno double %a, %b @@ -175,7 +175,7 @@ entry: ;;;==========================================================================;;; ; FUNC-LABEL: {{^}}i64_eq: -; SI: V_CMP_EQ_I64 +; SI: v_cmp_eq_i64 define void @i64_eq(i32 addrspace(1)* %out, i64 %a, i64 %b) { entry: %0 = icmp eq i64 %a, %b @@ -185,7 +185,7 @@ entry: } ; FUNC-LABEL: {{^}}i64_ne: -; SI: V_CMP_NE_I64 +; SI: v_cmp_ne_i64 define void @i64_ne(i32 addrspace(1)* %out, i64 %a, i64 %b) { entry: %0 = icmp ne i64 %a, %b @@ -195,7 +195,7 @@ entry: } ; FUNC-LABEL: {{^}}i64_ugt: -; SI: V_CMP_GT_U64 +; SI: v_cmp_gt_u64 define void @i64_ugt(i32 addrspace(1)* %out, i64 %a, i64 %b) { entry: %0 = icmp ugt i64 %a, %b @@ -205,7 +205,7 @@ entry: } ; FUNC-LABEL: {{^}}i64_uge: -; SI: V_CMP_GE_U64 +; SI: v_cmp_ge_u64 define void @i64_uge(i32 addrspace(1)* %out, i64 %a, i64 %b) { entry: %0 = icmp uge i64 %a, %b @@ -215,7 +215,7 @@ entry: } ; FUNC-LABEL: {{^}}i64_ult: -; SI: V_CMP_LT_U64 +; SI: v_cmp_lt_u64 define void @i64_ult(i32 addrspace(1)* %out, i64 %a, i64 %b) { entry: %0 = icmp ult i64 %a, %b @@ -225,7 +225,7 @@ entry: } ; FUNC-LABEL: {{^}}i64_ule: -; SI: V_CMP_LE_U64 +; SI: v_cmp_le_u64 define void @i64_ule(i32 addrspace(1)* %out, i64 %a, i64 %b) { entry: %0 = icmp ule i64 %a, %b @@ -235,7 +235,7 @@ entry: } ; FUNC-LABEL: {{^}}i64_sgt: -; SI: V_CMP_GT_I64 +; SI: v_cmp_gt_i64 define void @i64_sgt(i32 addrspace(1)* %out, i64 %a, i64 %b) { entry: %0 = icmp sgt i64 %a, %b @@ -245,7 +245,7 @@ entry: } ; FUNC-LABEL: {{^}}i64_sge: -; SI: V_CMP_GE_I64 +; SI: v_cmp_ge_i64 define void @i64_sge(i32 addrspace(1)* %out, i64 %a, i64 %b) { entry: %0 = icmp sge i64 %a, %b @@ -255,7 +255,7 @@ entry: } ; FUNC-LABEL: {{^}}i64_slt: -; SI: V_CMP_LT_I64 +; SI: v_cmp_lt_i64 define void @i64_slt(i32 addrspace(1)* %out, i64 %a, i64 %b) { entry: %0 = icmp slt i64 %a, %b @@ -265,7 +265,7 @@ entry: } ; FUNC-LABEL: {{^}}i64_sle: -; SI: V_CMP_LE_I64 +; SI: v_cmp_le_i64 define void @i64_sle(i32 addrspace(1)* %out, i64 %a, i64 %b) { entry: %0 = icmp sle i64 %a, %b diff --git a/test/CodeGen/R600/seto.ll b/test/CodeGen/R600/seto.ll index 384c9cf5bb8..5fe6ff6bcd3 100644 --- a/test/CodeGen/R600/seto.ll +++ b/test/CodeGen/R600/seto.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=r600 -mcpu=verde -verify-machineinstrs < %s | FileCheck %s ; CHECK-LABEL: {{^}}main: -; CHECK: V_CMP_O_F32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[SREG:s[0-9]+]], [[SREG]] -; CHECK-NEXT: V_CNDMASK_B32_e64 {{v[0-9]+}}, 0, 1.0, [[CMP]] +; CHECK: v_cmp_o_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[SREG:s[0-9]+]], [[SREG]] +; CHECK-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, 1.0, [[CMP]] define void @main(float %p) { main_body: %c = fcmp oeq float %p, %p diff --git a/test/CodeGen/R600/setuo.ll b/test/CodeGen/R600/setuo.ll index 7aec7acbb26..a3911777a9a 100644 --- a/test/CodeGen/R600/setuo.ll +++ b/test/CodeGen/R600/setuo.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=r600 -mcpu=verde -verify-machineinstrs < %s | FileCheck %s ; CHECK-LABEL: {{^}}main: -; CHECK: V_CMP_U_F32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[SREG:s[0-9]+]], [[SREG]] -; CHECK-NEXT: V_CNDMASK_B32_e64 {{v[0-9]+}}, 0, 1.0, [[CMP]] +; CHECK: v_cmp_u_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[SREG:s[0-9]+]], [[SREG]] +; CHECK-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, 1.0, [[CMP]] define void @main(float %p) { main_body: %c = fcmp une float %p, %p diff --git a/test/CodeGen/R600/sext-in-reg.ll b/test/CodeGen/R600/sext-in-reg.ll index a23931337ae..693ef9da375 100644 --- a/test/CodeGen/R600/sext-in-reg.ll +++ b/test/CodeGen/R600/sext-in-reg.ll @@ -5,10 +5,10 @@ declare i32 @llvm.AMDGPU.imax(i32, i32) nounwind readnone ; FUNC-LABEL: {{^}}sext_in_reg_i1_i32: -; SI: S_LOAD_DWORD [[ARG:s[0-9]+]], -; SI: S_BFE_I32 [[SEXTRACT:s[0-9]+]], [[ARG]], 0x10000 -; SI: V_MOV_B32_e32 [[EXTRACT:v[0-9]+]], [[SEXTRACT]] -; SI: BUFFER_STORE_DWORD [[EXTRACT]], +; SI: s_load_dword [[ARG:s[0-9]+]], +; SI: s_bfe_i32 [[SEXTRACT:s[0-9]+]], [[ARG]], 0x10000 +; SI: v_mov_b32_e32 [[EXTRACT:v[0-9]+]], [[SEXTRACT]] +; SI: buffer_store_dword [[EXTRACT]], ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]] ; EG: BFE_INT [[RES]], {{.*}}, 0.0, 1 @@ -21,10 +21,10 @@ define void @sext_in_reg_i1_i32(i32 addrspace(1)* %out, i32 %in) { } ; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i32: -; SI: S_ADD_I32 [[VAL:s[0-9]+]], -; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]] -; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]] -; SI: BUFFER_STORE_DWORD [[VEXTRACT]], +; SI: s_add_i32 [[VAL:s[0-9]+]], +; SI: s_sext_i32_i8 [[EXTRACT:s[0-9]+]], [[VAL]] +; SI: v_mov_b32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]] +; SI: buffer_store_dword [[VEXTRACT]], ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]] ; EG: ADD_INT @@ -39,10 +39,10 @@ define void @sext_in_reg_i8_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounw } ; FUNC-LABEL: {{^}}sext_in_reg_i16_to_i32: -; SI: S_ADD_I32 [[VAL:s[0-9]+]], -; SI: S_SEXT_I32_I16 [[EXTRACT:s[0-9]+]], [[VAL]] -; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]] -; SI: BUFFER_STORE_DWORD [[VEXTRACT]], +; SI: s_add_i32 [[VAL:s[0-9]+]], +; SI: s_sext_i32_i16 [[EXTRACT:s[0-9]+]], [[VAL]] +; SI: v_mov_b32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]] +; SI: buffer_store_dword [[VEXTRACT]], ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]] ; EG: ADD_INT @@ -57,10 +57,10 @@ define void @sext_in_reg_i16_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) noun } ; FUNC-LABEL: {{^}}sext_in_reg_i8_to_v1i32: -; SI: S_ADD_I32 [[VAL:s[0-9]+]], -; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]] -; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]] -; SI: BUFFER_STORE_DWORD [[VEXTRACT]], +; SI: s_add_i32 [[VAL:s[0-9]+]], +; SI: s_sext_i32_i8 [[EXTRACT:s[0-9]+]], [[VAL]] +; SI: v_mov_b32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]] +; SI: buffer_store_dword [[VEXTRACT]], ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]] ; EG: ADD_INT @@ -75,10 +75,10 @@ define void @sext_in_reg_i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i32> %a, } ; FUNC-LABEL: {{^}}sext_in_reg_i1_to_i64: -; SI: S_MOV_B32 {{s[0-9]+}}, -1 -; SI: S_ADD_I32 [[VAL:s[0-9]+]], -; SI: S_BFE_I32 s{{[0-9]+}}, s{{[0-9]+}}, 0x10000 -; SI: BUFFER_STORE_DWORDX2 +; SI: s_mov_b32 {{s[0-9]+}}, -1 +; SI: s_add_i32 [[VAL:s[0-9]+]], +; SI: s_bfe_i32 s{{[0-9]+}}, s{{[0-9]+}}, 0x10000 +; SI: buffer_store_dwordx2 define void @sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { %c = add i64 %a, %b %shl = shl i64 %c, 63 @@ -88,10 +88,10 @@ define void @sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounw } ; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i64: -; SI: S_MOV_B32 {{s[0-9]+}}, -1 -; SI: S_ADD_I32 [[VAL:s[0-9]+]], -; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_DWORDX2 +; SI: s_mov_b32 {{s[0-9]+}}, -1 +; SI: s_add_i32 [[VAL:s[0-9]+]], +; SI: s_sext_i32_i8 [[EXTRACT:s[0-9]+]], [[VAL]] +; SI: buffer_store_dwordx2 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]] ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]] @@ -112,10 +112,10 @@ define void @sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounw } ; FUNC-LABEL: {{^}}sext_in_reg_i16_to_i64: -; SI: S_MOV_B32 {{s[0-9]+}}, -1 -; SI: S_ADD_I32 [[VAL:s[0-9]+]], -; SI: S_SEXT_I32_I16 [[EXTRACT:s[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_DWORDX2 +; SI: s_mov_b32 {{s[0-9]+}}, -1 +; SI: s_add_i32 [[VAL:s[0-9]+]], +; SI: s_sext_i32_i16 [[EXTRACT:s[0-9]+]], [[VAL]] +; SI: buffer_store_dwordx2 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]] ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]] @@ -136,11 +136,11 @@ define void @sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) noun } ; FUNC-LABEL: {{^}}sext_in_reg_i32_to_i64: -; SI: S_LOAD_DWORD -; SI: S_LOAD_DWORD -; SI: S_ADD_I32 [[ADD:s[0-9]+]], -; SI: S_ASHR_I32 s{{[0-9]+}}, [[ADD]], 31 -; SI: BUFFER_STORE_DWORDX2 +; SI: s_load_dword +; SI: s_load_dword +; SI: s_add_i32 [[ADD:s[0-9]+]], +; SI: s_ashr_i32 s{{[0-9]+}}, [[ADD]], 31 +; SI: buffer_store_dwordx2 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]] ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]] @@ -162,9 +162,9 @@ define void @sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) noun ; This is broken on Evergreen for some reason related to the <1 x i64> kernel arguments. ; XFUNC-LABEL: {{^}}sext_in_reg_i8_to_v1i64: -; XSI: S_BFE_I32 [[EXTRACT:s[0-9]+]], {{s[0-9]+}}, 524288 -; XSI: S_ASHR_I32 {{v[0-9]+}}, [[EXTRACT]], 31 -; XSI: BUFFER_STORE_DWORD +; XSI: s_bfe_i32 [[EXTRACT:s[0-9]+]], {{s[0-9]+}}, 524288 +; XSI: s_ashr_i32 {{v[0-9]+}}, [[EXTRACT]], 31 +; XSI: buffer_store_dword ; XEG: BFE_INT ; XEG: ASHR ; define void @sext_in_reg_i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i64> %a, <1 x i64> %b) nounwind { @@ -176,9 +176,9 @@ define void @sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) noun ; } ; FUNC-LABEL: {{^}}sext_in_reg_i1_in_i32_other_amount: -; SI-NOT: BFE -; SI: S_LSHL_B32 [[REG:s[0-9]+]], {{s[0-9]+}}, 6 -; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG]], 7 +; SI-NOT: {{[^@]}}bfe +; SI: s_lshl_b32 [[REG:s[0-9]+]], {{s[0-9]+}}, 6 +; SI: s_ashr_i32 {{s[0-9]+}}, [[REG]], 7 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]] ; EG-NOT: BFE @@ -195,11 +195,11 @@ define void @sext_in_reg_i1_in_i32_other_amount(i32 addrspace(1)* %out, i32 %a, } ; FUNC-LABEL: {{^}}sext_in_reg_v2i1_in_v2i32_other_amount: -; SI-DAG: S_LSHL_B32 [[REG0:s[0-9]+]], {{s[0-9]}}, 6 -; SI-DAG: S_ASHR_I32 {{s[0-9]+}}, [[REG0]], 7 -; SI-DAG: S_LSHL_B32 [[REG1:s[0-9]+]], {{s[0-9]}}, 6 -; SI-DAG: S_ASHR_I32 {{s[0-9]+}}, [[REG1]], 7 -; SI: S_ENDPGM +; SI-DAG: s_lshl_b32 [[REG0:s[0-9]+]], {{s[0-9]}}, 6 +; SI-DAG: s_ashr_i32 {{s[0-9]+}}, [[REG0]], 7 +; SI-DAG: s_lshl_b32 [[REG1:s[0-9]+]], {{s[0-9]}}, 6 +; SI-DAG: s_ashr_i32 {{s[0-9]+}}, [[REG1]], 7 +; SI: s_endpgm ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] ; EG-NOT: BFE @@ -219,9 +219,9 @@ define void @sext_in_reg_v2i1_in_v2i32_other_amount(<2 x i32> addrspace(1)* %out ; FUNC-LABEL: {{^}}sext_in_reg_v2i1_to_v2i32: -; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 -; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 -; SI: BUFFER_STORE_DWORDX2 +; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 +; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 +; SI: buffer_store_dwordx2 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] ; EG: BFE_INT [[RES]] @@ -236,11 +236,11 @@ define void @sext_in_reg_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> % } ; FUNC-LABEL: {{^}}sext_in_reg_v4i1_to_v4i32: -; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 -; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 -; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 -; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 -; SI: BUFFER_STORE_DWORDX4 +; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 +; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 +; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 +; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 +; SI: buffer_store_dwordx4 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] ; EG: BFE_INT [[RES]] @@ -257,9 +257,9 @@ define void @sext_in_reg_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> % } ; FUNC-LABEL: {{^}}sext_in_reg_v2i8_to_v2i32: -; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}} -; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}} -; SI: BUFFER_STORE_DWORDX2 +; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} +; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} +; SI: buffer_store_dwordx2 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] ; EG: BFE_INT [[RES]] @@ -274,11 +274,11 @@ define void @sext_in_reg_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> % } ; FUNC-LABEL: {{^}}sext_in_reg_v4i8_to_v4i32: -; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}} -; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}} -; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}} -; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}} -; SI: BUFFER_STORE_DWORDX4 +; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} +; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} +; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} +; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} +; SI: buffer_store_dwordx4 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] ; EG: BFE_INT [[RES]] @@ -295,9 +295,9 @@ define void @sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> % } ; FUNC-LABEL: {{^}}sext_in_reg_v2i16_to_v2i32: -; SI: S_SEXT_I32_I16 {{s[0-9]+}}, {{s[0-9]+}} -; SI: S_SEXT_I32_I16 {{s[0-9]+}}, {{s[0-9]+}} -; SI: BUFFER_STORE_DWORDX2 +; SI: s_sext_i32_i16 {{s[0-9]+}}, {{s[0-9]+}} +; SI: s_sext_i32_i16 {{s[0-9]+}}, {{s[0-9]+}} +; SI: buffer_store_dwordx2 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] ; EG: BFE_INT [[RES]] @@ -336,10 +336,10 @@ define void @testcase_3(i8 addrspace(1)* %out, i8 %a) nounwind { } ; FUNC-LABEL: {{^}}vgpr_sext_in_reg_v4i8_to_v4i32: -; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 -; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 -; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 -; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 +; SI: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 +; SI: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 +; SI: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 +; SI: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 define void @vgpr_sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %b) nounwind { %loada = load <4 x i32> addrspace(1)* %a, align 16 %loadb = load <4 x i32> addrspace(1)* %b, align 16 @@ -351,8 +351,8 @@ define void @vgpr_sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i } ; FUNC-LABEL: {{^}}vgpr_sext_in_reg_v4i16_to_v4i32: -; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16 -; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16 +; SI: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16 +; SI: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16 define void @vgpr_sext_in_reg_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %b) nounwind { %loada = load <4 x i32> addrspace(1)* %a, align 16 %loadb = load <4 x i32> addrspace(1)* %b, align 16 @@ -367,10 +367,10 @@ define void @vgpr_sext_in_reg_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x ; when computeKnownBitsForTargetNode is implemented for imax. ; FUNC-LABEL: {{^}}sext_in_reg_to_illegal_type: -; SI: BUFFER_LOAD_SBYTE -; SI: V_MAX_I32 -; SI: V_BFE_I32 -; SI: BUFFER_STORE_SHORT +; SI: buffer_load_sbyte +; SI: v_max_i32 +; SI: v_bfe_i32 +; SI: buffer_store_short define void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind { %tmp5 = load i8 addrspace(1)* %src, align 1 %tmp2 = sext i8 %tmp5 to i32 @@ -384,8 +384,8 @@ define void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocapture %out, i8 ad declare i32 @llvm.AMDGPU.bfe.i32(i32, i32, i32) nounwind readnone ; FUNC-LABEL: {{^}}bfe_0_width: -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_0_width(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwind { %load = load i32 addrspace(1)* %ptr, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 8, i32 0) nounwind readnone @@ -394,9 +394,9 @@ define void @bfe_0_width(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwin } ; FUNC-LABEL: {{^}}bfe_8_bfe_8: -; SI: V_BFE_I32 -; SI-NOT: BFE -; SI: S_ENDPGM +; SI: v_bfe_i32 +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_8_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwind { %load = load i32 addrspace(1)* %ptr, align 4 %bfe0 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 0, i32 8) nounwind readnone @@ -406,8 +406,8 @@ define void @bfe_8_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwin } ; FUNC-LABEL: {{^}}bfe_8_bfe_16: -; SI: V_BFE_I32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8 -; SI: S_ENDPGM +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8 +; SI: s_endpgm define void @bfe_8_bfe_16(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwind { %load = load i32 addrspace(1)* %ptr, align 4 %bfe0 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 0, i32 8) nounwind readnone @@ -418,9 +418,9 @@ define void @bfe_8_bfe_16(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwi ; This really should be folded into 1 ; FUNC-LABEL: {{^}}bfe_16_bfe_8: -; SI: V_BFE_I32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8 -; SI-NOT: BFE -; SI: S_ENDPGM +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8 +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_16_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwind { %load = load i32 addrspace(1)* %ptr, align 4 %bfe0 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 0, i32 16) nounwind readnone @@ -431,9 +431,9 @@ define void @bfe_16_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwi ; Make sure there isn't a redundant BFE ; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i32_bfe: -; SI: S_SEXT_I32_I8 s{{[0-9]+}}, s{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; SI: s_sext_i32_i8 s{{[0-9]+}}, s{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @sext_in_reg_i8_to_i32_bfe(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %c = add i32 %a, %b ; add to prevent folding into extload %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %c, i32 0, i32 8) nounwind readnone @@ -454,9 +454,9 @@ define void @sext_in_reg_i8_to_i32_bfe_wrong(i32 addrspace(1)* %out, i32 %a, i32 } ; FUNC-LABEL: {{^}}sextload_i8_to_i32_bfe: -; SI: BUFFER_LOAD_SBYTE -; SI-NOT: BFE -; SI: S_ENDPGM +; SI: buffer_load_sbyte +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @sextload_i8_to_i32_bfe(i32 addrspace(1)* %out, i8 addrspace(1)* %ptr) nounwind { %load = load i8 addrspace(1)* %ptr, align 1 %sext = sext i8 %load to i32 @@ -469,8 +469,8 @@ define void @sextload_i8_to_i32_bfe(i32 addrspace(1)* %out, i8 addrspace(1)* %pt ; FUNC-LABEL: {{^}}sextload_i8_to_i32_bfe_0: ; SI: .text -; SI-NOT: BFE -; SI: S_ENDPGM +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @sextload_i8_to_i32_bfe_0(i32 addrspace(1)* %out, i8 addrspace(1)* %ptr) nounwind { %load = load i8 addrspace(1)* %ptr, align 1 %sext = sext i8 %load to i32 @@ -482,10 +482,10 @@ define void @sextload_i8_to_i32_bfe_0(i32 addrspace(1)* %out, i8 addrspace(1)* % } ; FUNC-LABEL: {{^}}sext_in_reg_i1_bfe_offset_0: -; SI-NOT: SHR -; SI-NOT: SHL -; SI: V_BFE_I32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1 -; SI: S_ENDPGM +; SI-NOT: shr +; SI-NOT: shl +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1 +; SI: s_endpgm define void @sext_in_reg_i1_bfe_offset_0(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -496,11 +496,11 @@ define void @sext_in_reg_i1_bfe_offset_0(i32 addrspace(1)* %out, i32 addrspace(1 } ; FUNC-LABEL: {{^}}sext_in_reg_i1_bfe_offset_1: -; SI: BUFFER_LOAD_DWORD -; SI-NOT: SHL -; SI-NOT: SHR -; SI: V_BFE_I32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 1 -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI-NOT: shl +; SI-NOT: shr +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 1 +; SI: s_endpgm define void @sext_in_reg_i1_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 30 @@ -511,11 +511,11 @@ define void @sext_in_reg_i1_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1 } ; FUNC-LABEL: {{^}}sext_in_reg_i2_bfe_offset_1: -; SI: BUFFER_LOAD_DWORD -; SI: V_LSHLREV_B32_e32 v{{[0-9]+}}, 30, v{{[0-9]+}} -; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 30, v{{[0-9]+}} -; SI: V_BFE_I32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 2 -; SI: S_ENDPGM +; SI: buffer_load_dword +; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, 30, v{{[0-9]+}} +; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 30, v{{[0-9]+}} +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 2 +; SI: s_endpgm define void @sext_in_reg_i2_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 30 diff --git a/test/CodeGen/R600/sgpr-control-flow.ll b/test/CodeGen/R600/sgpr-control-flow.ll index 4ce2a4bc9e4..d8b8dffa7fa 100644 --- a/test/CodeGen/R600/sgpr-control-flow.ll +++ b/test/CodeGen/R600/sgpr-control-flow.ll @@ -8,8 +8,8 @@ ; threads will execute the same code paths, so we don't need to worry ; about instructions in different blocks overwriting each other. ; SI-LABEL: {{^}}sgpr_if_else_salu_br: -; SI: S_ADD -; SI: S_ADD +; SI: s_add +; SI: s_add define void @sgpr_if_else_salu_br(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) { entry: @@ -35,8 +35,8 @@ endif: ; different threads will take different control flow paths. ; SI-LABEL: {{^}}sgpr_if_else_valu_br: -; SI: S_ADD_I32 [[SGPR:s[0-9]+]] -; SI-NOT: S_ADD_I32 [[SGPR]] +; SI: s_add_i32 [[SGPR:s[0-9]+]] +; SI-NOT: s_add_i32 [[SGPR]] define void @sgpr_if_else_valu_br(i32 addrspace(1)* %out, float %a, i32 %b, i32 %c, i32 %d, i32 %e) { entry: diff --git a/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll b/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll index fa6b0cdd29c..aa97fbf01fd 100644 --- a/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll +++ b/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll @@ -4,7 +4,7 @@ ; used in an REG_SEQUENCE that also needs to be handled. ; SI-LABEL: {{^}}test_dup_operands: -; SI: V_ADD_I32_e32 +; SI: v_add_i32_e32 define void @test_dup_operands(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %in) { %a = load <2 x i32> addrspace(1)* %in %lo = extractelement <2 x i32> %a, i32 0 diff --git a/test/CodeGen/R600/sgpr-copy.ll b/test/CodeGen/R600/sgpr-copy.ll index a58427940d8..b5a72f76b05 100644 --- a/test/CodeGen/R600/sgpr-copy.ll +++ b/test/CodeGen/R600/sgpr-copy.ll @@ -3,8 +3,8 @@ ; This test checks that no VGPR to SGPR copies are created by the register ; allocator. ; CHECK-LABEL: {{^}}phi1: -; CHECK: S_BUFFER_LOAD_DWORD [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0 -; CHECK: V_MOV_B32_e32 v{{[0-9]}}, [[DST]] +; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0 +; CHECK: v_mov_b32_e32 v{{[0-9]}}, [[DST]] define void @phi1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: @@ -228,10 +228,10 @@ declare i32 @llvm.SI.packf16(float, float) #1 ; an assertion failure. ; CHECK-LABEL: {{^}}sample_v3: -; CHECK: IMAGE_SAMPLE -; CHECK: IMAGE_SAMPLE -; CHECK: EXP -; CHECK: S_ENDPGM +; CHECK: image_sample +; CHECK: image_sample +; CHECK: exp +; CHECK: s_endpgm define void @sample_v3([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { entry: @@ -270,9 +270,9 @@ endif: !2 = metadata !{metadata !"const", null, i32 1} ; CHECK-LABEL: {{^}}copy1: -; CHECK: BUFFER_LOAD_DWORD -; CHECK: V_ADD -; CHECK: S_ENDPGM +; CHECK: buffer_load_dword +; CHECK: v_add +; CHECK: s_endpgm define void @copy1(float addrspace(1)* %out, float addrspace(1)* %in0) { entry: %0 = load float addrspace(1)* %in0 @@ -297,7 +297,7 @@ endif: ; This test is just checking that we don't crash / assertion fail. ; CHECK-LABEL: {{^}}copy2: -; CHECK: S_ENDPGM +; CHECK: s_endpgm define void @copy2([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { entry: diff --git a/test/CodeGen/R600/shl.ll b/test/CodeGen/R600/shl.ll index c3433d9077b..71c9fc46359 100644 --- a/test/CodeGen/R600/shl.ll +++ b/test/CodeGen/R600/shl.ll @@ -6,8 +6,8 @@ ;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;SI-CHECK: {{^}}shl_v2i32: -;SI-CHECK: V_LSHL_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_LSHL_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -25,10 +25,10 @@ define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in ;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;SI-CHECK: {{^}}shl_v4i32: -;SI-CHECK: V_LSHL_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_LSHL_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_LSHL_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_LSHL_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 @@ -52,7 +52,7 @@ define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in ;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0 ;SI-CHECK: {{^}}shl_i64: -;SI-CHECK: V_LSHL_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} define void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { %b_ptr = getelementptr i64 addrspace(1)* %in, i64 1 @@ -86,8 +86,8 @@ define void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { ;EG-CHECK-DAG: CNDE_INT ;SI-CHECK: {{^}}shl_v2i64: -;SI-CHECK: V_LSHL_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: V_LSHL_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} define void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1 @@ -141,10 +141,10 @@ define void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in ;EG-CHECK-DAG: CNDE_INT ;SI-CHECK: {{^}}shl_v4i64: -;SI-CHECK: V_LSHL_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: V_LSHL_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: V_LSHL_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: V_LSHL_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} define void @shl_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1 diff --git a/test/CodeGen/R600/shl_add_constant.ll b/test/CodeGen/R600/shl_add_constant.ll index f8c64c8f973..801f77de571 100644 --- a/test/CodeGen/R600/shl_add_constant.ll +++ b/test/CodeGen/R600/shl_add_constant.ll @@ -5,10 +5,10 @@ declare i32 @llvm.r600.read.tidig.x() #1 ; Test with inline immediate ; FUNC-LABEL: {{^}}shl_2_add_9_i32: -; SI: V_LSHLREV_B32_e32 [[REG:v[0-9]+]], 2, {{v[0-9]+}} -; SI: V_ADD_I32_e32 [[RESULT:v[0-9]+]], 36, [[REG]] -; SI: BUFFER_STORE_DWORD [[RESULT]] -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[REG:v[0-9]+]], 2, {{v[0-9]+}} +; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], 36, [[REG]] +; SI: buffer_store_dword [[RESULT]] +; SI: s_endpgm define void @shl_2_add_9_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %ptr = getelementptr i32 addrspace(1)* %in, i32 %tid.x @@ -20,11 +20,11 @@ define void @shl_2_add_9_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { } ; FUNC-LABEL: {{^}}shl_2_add_9_i32_2_add_uses: -; SI-DAG: V_ADD_I32_e32 [[ADDREG:v[0-9]+]], 9, {{v[0-9]+}} -; SI-DAG: V_LSHLREV_B32_e32 [[SHLREG:v[0-9]+]], 2, {{v[0-9]+}} -; SI-DAG: BUFFER_STORE_DWORD [[ADDREG]] -; SI-DAG: BUFFER_STORE_DWORD [[SHLREG]] -; SI: S_ENDPGM +; SI-DAG: v_add_i32_e32 [[ADDREG:v[0-9]+]], 9, {{v[0-9]+}} +; SI-DAG: v_lshlrev_b32_e32 [[SHLREG:v[0-9]+]], 2, {{v[0-9]+}} +; SI-DAG: buffer_store_dword [[ADDREG]] +; SI-DAG: buffer_store_dword [[SHLREG]] +; SI: s_endpgm define void @shl_2_add_9_i32_2_add_uses(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %in) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %ptr = getelementptr i32 addrspace(1)* %in, i32 %tid.x @@ -39,10 +39,10 @@ define void @shl_2_add_9_i32_2_add_uses(i32 addrspace(1)* %out0, i32 addrspace(1 ; Test with add literal constant ; FUNC-LABEL: {{^}}shl_2_add_999_i32: -; SI: V_LSHLREV_B32_e32 [[REG:v[0-9]+]], 2, {{v[0-9]+}} -; SI: V_ADD_I32_e32 [[RESULT:v[0-9]+]], 0xf9c, [[REG]] -; SI: BUFFER_STORE_DWORD [[RESULT]] -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[REG:v[0-9]+]], 2, {{v[0-9]+}} +; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], 0xf9c, [[REG]] +; SI: buffer_store_dword [[RESULT]] +; SI: s_endpgm define void @shl_2_add_999_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %ptr = getelementptr i32 addrspace(1)* %in, i32 %tid.x @@ -54,13 +54,13 @@ define void @shl_2_add_999_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 } ; FUNC-LABEL: {{^}}test_add_shl_add_constant: -; SI-DAG: S_LOAD_DWORD [[X:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: S_LOAD_DWORD [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI: S_LSHL_B32 [[SHL3:s[0-9]+]], [[X]], 3 -; SI: S_ADD_I32 [[TMP:s[0-9]+]], [[SHL3]], [[Y]] -; SI: S_ADD_I32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8 -; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[RESULT]] -; SI: BUFFER_STORE_DWORD [[VRESULT]] +; SI-DAG: s_load_dword [[X:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI: s_lshl_b32 [[SHL3:s[0-9]+]], [[X]], 3 +; SI: s_add_i32 [[TMP:s[0-9]+]], [[SHL3]], [[Y]] +; SI: s_add_i32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8 +; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]] +; SI: buffer_store_dword [[VRESULT]] define void @test_add_shl_add_constant(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 { %add.0 = add i32 %x, 123 %shl = shl i32 %add.0, 3 @@ -70,13 +70,13 @@ define void @test_add_shl_add_constant(i32 addrspace(1)* %out, i32 %x, i32 %y) # } ; FUNC-LABEL: {{^}}test_add_shl_add_constant_inv: -; SI-DAG: S_LOAD_DWORD [[X:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: S_LOAD_DWORD [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI: S_LSHL_B32 [[SHL3:s[0-9]+]], [[X]], 3 -; SI: S_ADD_I32 [[TMP:s[0-9]+]], [[SHL3]], [[Y]] -; SI: S_ADD_I32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8 -; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[RESULT]] -; SI: BUFFER_STORE_DWORD [[VRESULT]] +; SI-DAG: s_load_dword [[X:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI: s_lshl_b32 [[SHL3:s[0-9]+]], [[X]], 3 +; SI: s_add_i32 [[TMP:s[0-9]+]], [[SHL3]], [[Y]] +; SI: s_add_i32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8 +; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]] +; SI: buffer_store_dword [[VRESULT]] define void @test_add_shl_add_constant_inv(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 { %add.0 = add i32 %x, 123 diff --git a/test/CodeGen/R600/shl_add_ptr.ll b/test/CodeGen/R600/shl_add_ptr.ll index 344d3131ef1..e6dfc587eca 100644 --- a/test/CodeGen/R600/shl_add_ptr.ll +++ b/test/CodeGen/R600/shl_add_ptr.ll @@ -15,9 +15,9 @@ declare i32 @llvm.r600.read.tidig.x() #1 ; Make sure the (add tid, 2) << 2 gets folded into the ds's offset as (tid << 2) + 8 ; SI-LABEL: {{^}}load_shl_base_lds_0: -; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} -; SI: DS_READ_B32 {{v[0-9]+}}, [[PTR]] offset:8 [M0] -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; SI: ds_read_b32 {{v[0-9]+}}, [[PTR]] offset:8 [M0] +; SI: s_endpgm define void @load_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 2 @@ -32,12 +32,12 @@ define void @load_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %ad ; remaining add use goes through the normal shl + add constant fold. ; SI-LABEL: {{^}}load_shl_base_lds_1: -; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} -; SI: DS_READ_B32 [[RESULT:v[0-9]+]], [[PTR]] offset:8 [M0] -; SI: V_ADD_I32_e32 [[ADDUSE:v[0-9]+]], 8, v{{[0-9]+}} -; SI-DAG: BUFFER_STORE_DWORD [[RESULT]] -; SI-DAG: BUFFER_STORE_DWORD [[ADDUSE]] -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; SI: ds_read_b32 [[RESULT:v[0-9]+]], [[PTR]] offset:8 [M0] +; SI: v_add_i32_e32 [[ADDUSE:v[0-9]+]], 8, v{{[0-9]+}} +; SI-DAG: buffer_store_dword [[RESULT]] +; SI-DAG: buffer_store_dword [[ADDUSE]] +; SI: s_endpgm define void @load_shl_base_lds_1(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 2 @@ -52,8 +52,8 @@ define void @load_shl_base_lds_1(float addrspace(1)* %out, i32 addrspace(1)* %ad @maxlds = addrspace(3) global [65536 x i8] zeroinitializer, align 4 ; SI-LABEL: {{^}}load_shl_base_lds_max_offset -; SI: DS_READ_U8 v{{[0-9]+}}, v{{[0-9]+}} offset:65535 -; SI: S_ENDPGM +; SI: ds_read_u8 v{{[0-9]+}}, v{{[0-9]+}} offset:65535 +; SI: s_endpgm define void @load_shl_base_lds_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %lds, i32 addrspace(1)* %add_use) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 65535 @@ -68,9 +68,9 @@ define void @load_shl_base_lds_max_offset(i8 addrspace(1)* %out, i8 addrspace(3) ; pointer can be used with an offset into the second one. ; SI-LABEL: {{^}}load_shl_base_lds_2: -; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} -; SI-NEXT: DS_READ2ST64_B32 {{v\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:1 offset1:9 [M0] -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; SI-NEXT: ds_read2st64_b32 {{v\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:1 offset1:9 [M0] +; SI: s_endpgm define void @load_shl_base_lds_2(float addrspace(1)* %out) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 64 @@ -84,9 +84,9 @@ define void @load_shl_base_lds_2(float addrspace(1)* %out) #0 { } ; SI-LABEL: {{^}}store_shl_base_lds_0: -; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} -; SI: DS_WRITE_B32 [[PTR]], {{v[0-9]+}} offset:8 [M0] -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; SI: ds_write_b32 [[PTR]], {{v[0-9]+}} offset:8 [M0] +; SI: s_endpgm define void @store_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 2 @@ -114,9 +114,9 @@ define void @store_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %a ; SI-LABEL: {{^}}atomic_cmpxchg_shl_base_lds_0: -; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} -; SI: DS_CMPST_RTN_B32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, {{v[0-9]+}} offset:8 -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; SI: ds_cmpst_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, {{v[0-9]+}} offset:8 +; SI: s_endpgm define void @atomic_cmpxchg_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use, i32 %swap) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 2 @@ -129,9 +129,9 @@ define void @atomic_cmpxchg_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace } ; SI-LABEL: {{^}}atomic_swap_shl_base_lds_0: -; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} -; SI: DS_WRXCHG_RTN_B32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; SI: ds_wrxchg_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 +; SI: s_endpgm define void @atomic_swap_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 2 @@ -143,9 +143,9 @@ define void @atomic_swap_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1) } ; SI-LABEL: {{^}}atomic_add_shl_base_lds_0: -; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} -; SI: DS_ADD_RTN_U32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; SI: ds_add_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 +; SI: s_endpgm define void @atomic_add_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 2 @@ -157,9 +157,9 @@ define void @atomic_add_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* } ; SI-LABEL: {{^}}atomic_sub_shl_base_lds_0: -; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} -; SI: DS_SUB_RTN_U32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; SI: ds_sub_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 +; SI: s_endpgm define void @atomic_sub_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 2 @@ -171,9 +171,9 @@ define void @atomic_sub_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* } ; SI-LABEL: {{^}}atomic_and_shl_base_lds_0: -; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} -; SI: DS_AND_RTN_B32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; SI: ds_and_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 +; SI: s_endpgm define void @atomic_and_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 2 @@ -185,9 +185,9 @@ define void @atomic_and_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* } ; SI-LABEL: {{^}}atomic_or_shl_base_lds_0: -; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} -; SI: DS_OR_RTN_B32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; SI: ds_or_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 +; SI: s_endpgm define void @atomic_or_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 2 @@ -199,9 +199,9 @@ define void @atomic_or_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* } ; SI-LABEL: {{^}}atomic_xor_shl_base_lds_0: -; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} -; SI: DS_XOR_RTN_B32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; SI: ds_xor_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 +; SI: s_endpgm define void @atomic_xor_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 2 @@ -223,9 +223,9 @@ define void @atomic_xor_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* ; } ; SI-LABEL: {{^}}atomic_min_shl_base_lds_0: -; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} -; SI: DS_MIN_RTN_I32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; SI: ds_min_rtn_i32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 +; SI: s_endpgm define void @atomic_min_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 2 @@ -237,9 +237,9 @@ define void @atomic_min_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* } ; SI-LABEL: {{^}}atomic_max_shl_base_lds_0: -; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} -; SI: DS_MAX_RTN_I32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; SI: ds_max_rtn_i32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 +; SI: s_endpgm define void @atomic_max_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 2 @@ -251,9 +251,9 @@ define void @atomic_max_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* } ; SI-LABEL: {{^}}atomic_umin_shl_base_lds_0: -; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} -; SI: DS_MIN_RTN_U32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; SI: ds_min_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 +; SI: s_endpgm define void @atomic_umin_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 2 @@ -265,9 +265,9 @@ define void @atomic_umin_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1) } ; SI-LABEL: {{^}}atomic_umax_shl_base_lds_0: -; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} -; SI: DS_MAX_RTN_U32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 -; SI: S_ENDPGM +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; SI: ds_max_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 +; SI: s_endpgm define void @atomic_umax_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 %idx.0 = add nsw i32 %tid.x, 2 diff --git a/test/CodeGen/R600/si-lod-bias.ll b/test/CodeGen/R600/si-lod-bias.ll index 5c8befa17c2..60277d63182 100644 --- a/test/CodeGen/R600/si-lod-bias.ll +++ b/test/CodeGen/R600/si-lod-bias.ll @@ -4,7 +4,7 @@ ; the wrong register class is used for the REG_SEQUENCE instructions. ; CHECK: {{^}}main: -; CHECK: IMAGE_SAMPLE_B v{{\[[0-9]:[0-9]\]}}, 15, 0, 0, 0, 0, 0, 0, 0, v{{\[[0-9]:[0-9]\]}} +; CHECK: image_sample_b v{{\[[0-9]:[0-9]\]}}, 15, 0, 0, 0, 0, 0, 0, 0, v{{\[[0-9]:[0-9]\]}} define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: diff --git a/test/CodeGen/R600/si-sgpr-spill.ll b/test/CodeGen/R600/si-sgpr-spill.ll index 78f915f9995..439d8e212f9 100644 --- a/test/CodeGen/R600/si-sgpr-spill.ll +++ b/test/CodeGen/R600/si-sgpr-spill.ll @@ -5,8 +5,8 @@ ; CHECK-LABEL: {{^}}main: ; Writing to M0 from an SMRD instruction will hang the GPU. -; CHECK-NOT: S_BUFFER_LOAD_DWORD m0 -; CHECK: S_ENDPGM +; CHECK-NOT: s_buffer_load_dword m0 +; CHECK: s_endpgm @ddxy_lds = external addrspace(3) global [64 x i32] define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { @@ -689,7 +689,7 @@ attributes #4 = { nounwind readonly } !0 = metadata !{metadata !"const", null, i32 1} ; CHECK-LABEL: {{^}}main1: -; CHECK: S_ENDPGM +; CHECK: s_endpgm define void @main1([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 diff --git a/test/CodeGen/R600/si-vector-hang.ll b/test/CodeGen/R600/si-vector-hang.ll index a6fec02747c..6f91c71edb7 100644 --- a/test/CodeGen/R600/si-vector-hang.ll +++ b/test/CodeGen/R600/si-vector-hang.ll @@ -1,14 +1,14 @@ ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ; CHECK: {{^}}test_8_min_char: -; CHECK: BUFFER_STORE_BYTE -; CHECK: BUFFER_STORE_BYTE -; CHECK: BUFFER_STORE_BYTE -; CHECK: BUFFER_STORE_BYTE -; CHECK: BUFFER_STORE_BYTE -; CHECK: BUFFER_STORE_BYTE -; CHECK: BUFFER_STORE_BYTE -; CHECK: BUFFER_STORE_BYTE +; CHECK: buffer_store_byte +; CHECK: buffer_store_byte +; CHECK: buffer_store_byte +; CHECK: buffer_store_byte +; CHECK: buffer_store_byte +; CHECK: buffer_store_byte +; CHECK: buffer_store_byte +; CHECK: buffer_store_byte ; ModuleID = 'radeon' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64" target triple = "r600--" diff --git a/test/CodeGen/R600/sign_extend.ll b/test/CodeGen/R600/sign_extend.ll index f9d8fcc14ad..94f4c46321f 100644 --- a/test/CodeGen/R600/sign_extend.ll +++ b/test/CodeGen/R600/sign_extend.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; SI-LABEL: {{^}}s_sext_i1_to_i32: -; SI: V_CNDMASK_B32_e64 -; SI: S_ENDPGM +; SI: v_cndmask_b32_e64 +; SI: s_endpgm define void @s_sext_i1_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %cmp = icmp eq i32 %a, %b %sext = sext i1 %cmp to i32 @@ -11,8 +11,8 @@ define void @s_sext_i1_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { } ; SI-LABEL: {{^}}test_s_sext_i32_to_i64: -; SI: S_ASHR_I32 -; SI: S_ENDPG +; SI: s_ashr_i32 +; SI: s_endpg define void @test_s_sext_i32_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) nounwind { entry: %mul = mul i32 %a, %b @@ -23,9 +23,9 @@ entry: } ; SI-LABEL: {{^}}s_sext_i1_to_i64: -; SI: V_CNDMASK_B32_e64 -; SI: V_CNDMASK_B32_e64 -; SI: S_ENDPGM +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e64 +; SI: s_endpgm define void @s_sext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %cmp = icmp eq i32 %a, %b %sext = sext i1 %cmp to i64 @@ -34,8 +34,8 @@ define void @s_sext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind { } ; SI-LABEL: {{^}}s_sext_i32_to_i64: -; SI: S_ASHR_I32 -; SI: S_ENDPGM +; SI: s_ashr_i32 +; SI: s_endpgm define void @s_sext_i32_to_i64(i64 addrspace(1)* %out, i32 %a) nounwind { %sext = sext i32 %a to i64 store i64 %sext, i64 addrspace(1)* %out, align 8 @@ -43,8 +43,8 @@ define void @s_sext_i32_to_i64(i64 addrspace(1)* %out, i32 %a) nounwind { } ; SI-LABEL: {{^}}v_sext_i32_to_i64: -; SI: V_ASHR -; SI: S_ENDPGM +; SI: v_ashr +; SI: s_endpgm define void @v_sext_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %val = load i32 addrspace(1)* %in, align 4 %sext = sext i32 %val to i64 @@ -53,7 +53,7 @@ define void @v_sext_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) no } ; SI-LABEL: {{^}}s_sext_i16_to_i64: -; SI: S_ENDPGM +; SI: s_endpgm define void @s_sext_i16_to_i64(i64 addrspace(1)* %out, i16 %a) nounwind { %sext = sext i16 %a to i64 store i64 %sext, i64 addrspace(1)* %out, align 8 diff --git a/test/CodeGen/R600/simplify-demanded-bits-build-pair.ll b/test/CodeGen/R600/simplify-demanded-bits-build-pair.ll index cb5297ca318..8d9ee42ec1d 100644 --- a/test/CodeGen/R600/simplify-demanded-bits-build-pair.ll +++ b/test/CodeGen/R600/simplify-demanded-bits-build-pair.ll @@ -15,9 +15,9 @@ define void @trunc_select_i64(i32 addrspace(1)* %out, i64 %a, i64 %b, i32 %c) { ; FIXME: Fix truncating store for local memory ; SI-LABEL: {{^}}trunc_load_alloca_i64: -; SI: V_MOVRELS_B32 -; SI-NOT: V_MOVRELS_B32 -; SI: S_ENDPGM +; SI: v_movrels_b32 +; SI-NOT: v_movrels_b32 +; SI: s_endpgm define void @trunc_load_alloca_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) { %idx = add i32 %a, %b %alloca = alloca i64, i32 4 diff --git a/test/CodeGen/R600/sint_to_fp.f64.ll b/test/CodeGen/R600/sint_to_fp.f64.ll index d2b3f12c1f3..6e4f87c4d12 100644 --- a/test/CodeGen/R600/sint_to_fp.f64.ll +++ b/test/CodeGen/R600/sint_to_fp.f64.ll @@ -3,7 +3,7 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone ; SI-LABEL: {{^}}sint_to_fp_i32_to_f64 -; SI: V_CVT_F64_I32_e32 +; SI: v_cvt_f64_i32_e32 define void @sint_to_fp_i32_to_f64(double addrspace(1)* %out, i32 %in) { %result = sitofp i32 %in to double store double %result, double addrspace(1)* %out @@ -11,13 +11,13 @@ define void @sint_to_fp_i32_to_f64(double addrspace(1)* %out, i32 %in) { } ; SI-LABEL: {{^}}sint_to_fp_i1_f64: -; SI: V_CMP_EQ_I32_e64 [[CMP:s\[[0-9]+:[0-9]\]]], +; SI: v_cmp_eq_i32_e64 [[CMP:s\[[0-9]+:[0-9]\]]], ; FIXME: We should the VGPR sources for V_CNDMASK are copied from SGPRs, ; we should be able to fold the SGPRs into the V_CNDMASK instructions. -; SI: V_CNDMASK_B32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]] -; SI: V_CNDMASK_B32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]] -; SI: BUFFER_STORE_DWORDX2 -; SI: S_ENDPGM +; SI: v_cndmask_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]] +; SI: v_cndmask_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]] +; SI: buffer_store_dwordx2 +; SI: s_endpgm define void @sint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) { %cmp = icmp eq i32 %in, 0 %fp = sitofp i1 %cmp to double @@ -26,10 +26,10 @@ define void @sint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) { } ; SI-LABEL: {{^}}sint_to_fp_i1_f64_load: -; SI: V_CNDMASK_B32_e64 [[IRESULT:v[0-9]]], 0, -1 -; SI-NEXT: V_CVT_F64_I32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]] -; SI: BUFFER_STORE_DWORDX2 [[RESULT]] -; SI: S_ENDPGM +; SI: v_cndmask_b32_e64 [[IRESULT:v[0-9]]], 0, -1 +; SI-NEXT: v_cvt_f64_i32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]] +; SI: buffer_store_dwordx2 [[RESULT]] +; SI: s_endpgm define void @sint_to_fp_i1_f64_load(double addrspace(1)* %out, i1 %in) { %fp = sitofp i1 %in to double store double %fp, double addrspace(1)* %out, align 8 @@ -44,12 +44,12 @@ define void @s_sint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 %in) { } ; SI-LABEL: @v_sint_to_fp_i64_to_f64 -; SI: BUFFER_LOAD_DWORDX2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} -; SI-DAG: V_CVT_F64_U32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]] -; SI-DAG: V_CVT_F64_I32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]] -; SI: V_LDEXP_F64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32 -; SI: V_ADD_F64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]] -; SI: BUFFER_STORE_DWORDX2 [[RESULT]] +; SI: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} +; SI-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]] +; SI-DAG: v_cvt_f64_i32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]] +; SI: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32 +; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]] +; SI: buffer_store_dwordx2 [[RESULT]] define void @v_sint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep = getelementptr i64 addrspace(1)* %in, i32 %tid diff --git a/test/CodeGen/R600/sint_to_fp.ll b/test/CodeGen/R600/sint_to_fp.ll index b45982539c9..7b6ce43e304 100644 --- a/test/CodeGen/R600/sint_to_fp.ll +++ b/test/CodeGen/R600/sint_to_fp.ll @@ -4,7 +4,7 @@ ; FUNC-LABEL: {{^}}s_sint_to_fp_i32_to_f32: ; R600: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].Z -; SI: V_CVT_F32_I32_e32 {{v[0-9]+}}, {{s[0-9]+$}} +; SI: v_cvt_f32_i32_e32 {{v[0-9]+}}, {{s[0-9]+$}} define void @s_sint_to_fp_i32_to_f32(float addrspace(1)* %out, i32 %in) { %result = sitofp i32 %in to float store float %result, float addrspace(1)* %out @@ -15,8 +15,8 @@ define void @s_sint_to_fp_i32_to_f32(float addrspace(1)* %out, i32 %in) { ; R600-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W ; R600-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X -; SI: V_CVT_F32_I32_e32 -; SI: V_CVT_F32_I32_e32 +; SI: v_cvt_f32_i32_e32 +; SI: v_cvt_f32_i32_e32 define void @sint_to_fp_v2i32(<2 x float> addrspace(1)* %out, <2 x i32> %in) { %result = sitofp <2 x i32> %in to <2 x float> store <2 x float> %result, <2 x float> addrspace(1)* %out @@ -29,10 +29,10 @@ define void @sint_to_fp_v2i32(<2 x float> addrspace(1)* %out, <2 x i32> %in) { ; R600: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; R600: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; SI: V_CVT_F32_I32_e32 -; SI: V_CVT_F32_I32_e32 -; SI: V_CVT_F32_I32_e32 -; SI: V_CVT_F32_I32_e32 +; SI: v_cvt_f32_i32_e32 +; SI: v_cvt_f32_i32_e32 +; SI: v_cvt_f32_i32_e32 +; SI: v_cvt_f32_i32_e32 define void @sint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %value = load <4 x i32> addrspace(1) * %in %result = sitofp <4 x i32> %value to <4 x float> @@ -41,10 +41,10 @@ define void @sint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspac } ; FUNC-LABEL: {{^}}sint_to_fp_i1_f32: -; SI: V_CMP_EQ_I32_e64 [[CMP:s\[[0-9]+:[0-9]\]]], -; SI-NEXT: V_CNDMASK_B32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: v_cmp_eq_i32_e64 [[CMP:s\[[0-9]+:[0-9]\]]], +; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm define void @sint_to_fp_i1_f32(float addrspace(1)* %out, i32 %in) { %cmp = icmp eq i32 %in, 0 %fp = uitofp i1 %cmp to float @@ -53,9 +53,9 @@ define void @sint_to_fp_i1_f32(float addrspace(1)* %out, i32 %in) { } ; FUNC-LABEL: {{^}}sint_to_fp_i1_f32_load: -; SI: V_CNDMASK_B32_e64 [[RESULT:v[0-9]+]], 0, -1.0 -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1.0 +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm define void @sint_to_fp_i1_f32_load(float addrspace(1)* %out, i1 %in) { %fp = sitofp i1 %in to float store float %fp, float addrspace(1)* %out, align 4 diff --git a/test/CodeGen/R600/smrd.ll b/test/CodeGen/R600/smrd.ll index d18e4fa3f53..23118f9a954 100644 --- a/test/CodeGen/R600/smrd.ll +++ b/test/CodeGen/R600/smrd.ll @@ -2,7 +2,7 @@ ; SMRD load with an immediate offset. ; CHECK-LABEL: {{^}}smrd0: -; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01 +; CHECK: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01 define void @smrd0(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) { entry: %0 = getelementptr i32 addrspace(2)* %ptr, i64 1 @@ -13,7 +13,7 @@ entry: ; SMRD load with the largest possible immediate offset. ; CHECK-LABEL: {{^}}smrd1: -; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff +; CHECK: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff define void @smrd1(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) { entry: %0 = getelementptr i32 addrspace(2)* %ptr, i64 255 @@ -24,9 +24,9 @@ entry: ; SMRD load with an offset greater than the largest possible immediate. ; CHECK-LABEL: {{^}}smrd2: -; CHECK: S_MOV_B32 s[[OFFSET:[0-9]]], 0x400 -; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]] -; CHECK: S_ENDPGM +; CHECK: s_mov_b32 s[[OFFSET:[0-9]]], 0x400 +; CHECK: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]] +; CHECK: s_endpgm define void @smrd2(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) { entry: %0 = getelementptr i32 addrspace(2)* %ptr, i64 256 @@ -37,14 +37,14 @@ entry: ; SMRD load with a 64-bit offset ; CHECK-LABEL: {{^}}smrd3: -; CHECK-DAG: S_MOV_B32 s[[SHI:[0-9]+]], 4 -; CHECK-DAG: S_MOV_B32 s[[SLO:[0-9]+]], 0 ; +; CHECK-DAG: s_mov_b32 s[[SHI:[0-9]+]], 4 +; CHECK-DAG: s_mov_b32 s[[SLO:[0-9]+]], 0 ; ; FIXME: We don't need to copy these values to VGPRs -; CHECK-DAG: V_MOV_B32_e32 v[[VLO:[0-9]+]], s[[SLO]] -; CHECK-DAG: V_MOV_B32_e32 v[[VHI:[0-9]+]], s[[SHI]] -; FIXME: We should be able to use S_LOAD_DWORD here -; CHECK: BUFFER_LOAD_DWORD v{{[0-9]+}}, v{{\[}}[[VLO]]:[[VHI]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 -; CHECK: S_ENDPGM +; CHECK-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]] +; CHECK-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] +; FIXME: We should be able to use s_load_dword here +; CHECK: buffer_load_dword v{{[0-9]+}}, v{{\[}}[[VLO]]:[[VHI]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 +; CHECK: s_endpgm define void @smrd3(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) { entry: %0 = getelementptr i32 addrspace(2)* %ptr, i64 4294967296 ; 2 ^ 32 @@ -55,7 +55,7 @@ entry: ; SMRD load using the load.const intrinsic with an immediate offset ; CHECK-LABEL: {{^}}smrd_load_const0: -; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04 +; CHECK: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04 define void @smrd_load_const0(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0 @@ -68,7 +68,7 @@ main_body: ; SMRD load using the load.const intrinsic with the largest possible immediate ; offset. ; CHECK-LABEL: {{^}}smrd_load_const1: -; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff +; CHECK: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff define void @smrd_load_const1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0 @@ -81,8 +81,8 @@ main_body: ; largets possible immediate. ; immediate offset. ; CHECK-LABEL: {{^}}smrd_load_const2: -; CHECK: S_MOV_B32 s[[OFFSET:[0-9]]], 0x400 -; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]] +; CHECK: s_mov_b32 s[[OFFSET:[0-9]]], 0x400 +; CHECK: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]] define void @smrd_load_const2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0 diff --git a/test/CodeGen/R600/sra.ll b/test/CodeGen/R600/sra.ll index f14c52021e0..8ba9daa353f 100644 --- a/test/CodeGen/R600/sra.ll +++ b/test/CodeGen/R600/sra.ll @@ -6,8 +6,8 @@ ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;SI-CHECK-LABEL: {{^}}ashr_v2i32: -;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -25,10 +25,10 @@ define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %i ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;SI-CHECK-LABEL: {{^}}ashr_v4i32: -;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 @@ -43,7 +43,7 @@ define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %i ;EG-CHECK: ASHR ;SI-CHECK-LABEL: {{^}}ashr_i64: -;SI-CHECK: S_ASHR_I64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8 +;SI-CHECK: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8 define void @ashr_i64(i64 addrspace(1)* %out, i32 %in) { entry: %0 = sext i32 %in to i64 @@ -67,7 +67,7 @@ entry: ;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} ;SI-CHECK-LABEL: {{^}}ashr_i64_2: -;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} define void @ashr_i64_2(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { entry: %b_ptr = getelementptr i64 addrspace(1)* %in, i64 1 @@ -105,8 +105,8 @@ entry: ;EG-CHECK-DAG: CNDE_INT ;SI-CHECK-LABEL: {{^}}ashr_v2i64: -;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1 @@ -168,10 +168,10 @@ define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %i ;EG-CHECK-DAG: CNDE_INT ;SI-CHECK-LABEL: {{^}}ashr_v4i64: -;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} define void @ashr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1 diff --git a/test/CodeGen/R600/srl.ll b/test/CodeGen/R600/srl.ll index d8800a45bc5..8c5daf68f6e 100644 --- a/test/CodeGen/R600/srl.ll +++ b/test/CodeGen/R600/srl.ll @@ -6,8 +6,8 @@ ;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;SI-CHECK: {{^}}lshr_v2i32: -;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @lshr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -26,10 +26,10 @@ define void @lshr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %i ;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;SI-CHECK: {{^}}lshr_v4i32: -;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 @@ -54,7 +54,7 @@ define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %i ;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0 ;SI-CHECK: {{^}}lshr_i64: -;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} define void @lshr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { %b_ptr = getelementptr i64 addrspace(1)* %in, i64 1 @@ -90,8 +90,8 @@ define void @lshr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { ;EG-CHECK-DAG: CNDE_INT ;SI-CHECK: {{^}}lshr_v2i64: -;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} define void @lshr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1 @@ -152,10 +152,10 @@ define void @lshr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %i ;EG-CHECK-DAG: CNDE_INT ;SI-CHECK: {{^}}lshr_v4i64: -;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +;SI-CHECK: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} define void @lshr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1 diff --git a/test/CodeGen/R600/ssubo.ll b/test/CodeGen/R600/ssubo.ll index 18d3e02cefd..8031c6f76f8 100644 --- a/test/CodeGen/R600/ssubo.ll +++ b/test/CodeGen/R600/ssubo.ll @@ -38,8 +38,8 @@ define void @v_ssubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 } ; FUNC-LABEL: {{^}}s_ssubo_i64: -; SI: S_SUB_U32 -; SI: S_SUBB_U32 +; SI: s_sub_u32 +; SI: s_subb_u32 define void @s_ssubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a, i64 %b) nounwind { %ssub = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) nounwind %val = extractvalue { i64, i1 } %ssub, 0 @@ -50,8 +50,8 @@ define void @s_ssubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 } ; FUNC-LABEL: {{^}}v_ssubo_i64: -; SI: V_SUB_I32_e32 -; SI: V_SUBB_U32_e32 +; SI: v_sub_i32_e32 +; SI: v_subb_u32_e32 define void @v_ssubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind { %a = load i64 addrspace(1)* %aptr, align 4 %b = load i64 addrspace(1)* %bptr, align 4 diff --git a/test/CodeGen/R600/store-v3i32.ll b/test/CodeGen/R600/store-v3i32.ll index c87bd3591f9..0f28f339e83 100644 --- a/test/CodeGen/R600/store-v3i32.ll +++ b/test/CodeGen/R600/store-v3i32.ll @@ -5,7 +5,7 @@ ; should be done in a single store. ; SI-LABEL: {{^}}store_v3i32: -; SI: BUFFER_STORE_DWORDX4 +; SI: buffer_store_dwordx4 define void @store_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a) nounwind { store <3 x i32> %a, <3 x i32> addrspace(1)* %out, align 16 ret void diff --git a/test/CodeGen/R600/store-v3i64.ll b/test/CodeGen/R600/store-v3i64.ll index 310ff415d50..247a5615183 100644 --- a/test/CodeGen/R600/store-v3i64.ll +++ b/test/CodeGen/R600/store-v3i64.ll @@ -2,8 +2,8 @@ ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI ; SI-LABEL: {{^}}global_store_v3i64: -; SI: BUFFER_STORE_DWORDX4 -; SI: BUFFER_STORE_DWORDX4 +; SI: buffer_store_dwordx4 +; SI: buffer_store_dwordx4 define void @global_store_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> %x) { store <3 x i64> %x, <3 x i64> addrspace(1)* %out, align 32 ret void diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll index 447044c9f33..713ecd67d7c 100644 --- a/test/CodeGen/R600/store.ll +++ b/test/CodeGen/R600/store.ll @@ -7,7 +7,7 @@ ;===------------------------------------------------------------------------===; ; FUNC-LABEL: {{^}}store_i1: ; EG-CHECK: MEM_RAT MSKOR -; SI-CHECK: BUFFER_STORE_BYTE +; SI-CHECK: buffer_store_byte define void @store_i1(i1 addrspace(1)* %out) { entry: store i1 true, i1 addrspace(1)* %out @@ -35,7 +35,7 @@ entry: ; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0 ; SI-CHECK-LABEL: {{^}}store_i8: -; SI-CHECK: BUFFER_STORE_BYTE +; SI-CHECK: buffer_store_byte define void @store_i8(i8 addrspace(1)* %out, i8 %in) { entry: @@ -64,7 +64,7 @@ entry: ; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0 ; SI-CHECK-LABEL: {{^}}store_i16: -; SI-CHECK: BUFFER_STORE_SHORT +; SI-CHECK: buffer_store_short define void @store_i16(i16 addrspace(1)* %out, i16 %in) { entry: store i16 %in, i16 addrspace(1)* %out @@ -75,8 +75,8 @@ entry: ; EG-CHECK: MEM_RAT MSKOR ; EG-CHECK-NOT: MEM_RAT MSKOR ; SI-CHECK-LABEL: {{^}}store_v2i8: -; SI-CHECK: BUFFER_STORE_BYTE -; SI-CHECK: BUFFER_STORE_BYTE +; SI-CHECK: buffer_store_byte +; SI-CHECK: buffer_store_byte define void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) { entry: %0 = trunc <2 x i32> %in to <2 x i8> @@ -90,8 +90,8 @@ entry: ; CM-CHECK-LABEL: {{^}}store_v2i16: ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD ; SI-CHECK-LABEL: {{^}}store_v2i16: -; SI-CHECK: BUFFER_STORE_SHORT -; SI-CHECK: BUFFER_STORE_SHORT +; SI-CHECK: buffer_store_short +; SI-CHECK: buffer_store_short define void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) { entry: %0 = trunc <2 x i32> %in to <2 x i16> @@ -104,10 +104,10 @@ entry: ; CM-CHECK-LABEL: {{^}}store_v4i8: ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD ; SI-CHECK-LABEL: {{^}}store_v4i8: -; SI-CHECK: BUFFER_STORE_BYTE -; SI-CHECK: BUFFER_STORE_BYTE -; SI-CHECK: BUFFER_STORE_BYTE -; SI-CHECK: BUFFER_STORE_BYTE +; SI-CHECK: buffer_store_byte +; SI-CHECK: buffer_store_byte +; SI-CHECK: buffer_store_byte +; SI-CHECK: buffer_store_byte define void @store_v4i8(<4 x i8> addrspace(1)* %out, <4 x i32> %in) { entry: %0 = trunc <4 x i32> %in to <4 x i8> @@ -121,7 +121,7 @@ entry: ; CM-CHECK-LABEL: {{^}}store_f32: ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}} ; SI-CHECK-LABEL: {{^}}store_f32: -; SI-CHECK: BUFFER_STORE_DWORD +; SI-CHECK: buffer_store_dword define void @store_f32(float addrspace(1)* %out, float %in) { store float %in, float addrspace(1)* %out @@ -135,11 +135,11 @@ define void @store_f32(float addrspace(1)* %out, float %in) { ; EG-CHECK: MEM_RAT MSKOR ; EG-CHECK-NOT: MEM_RAT MSKOR ; SI-CHECK-LABEL: {{^}}store_v4i16: -; SI-CHECK: BUFFER_STORE_SHORT -; SI-CHECK: BUFFER_STORE_SHORT -; SI-CHECK: BUFFER_STORE_SHORT -; SI-CHECK: BUFFER_STORE_SHORT -; SI-CHECK-NOT: BUFFER_STORE_BYTE +; SI-CHECK: buffer_store_short +; SI-CHECK: buffer_store_short +; SI-CHECK: buffer_store_short +; SI-CHECK: buffer_store_short +; SI-CHECK-NOT: buffer_store_byte define void @store_v4i16(<4 x i16> addrspace(1)* %out, <4 x i32> %in) { entry: %0 = trunc <4 x i32> %in to <4 x i16> @@ -153,7 +153,7 @@ entry: ; CM-CHECK-LABEL: {{^}}store_v2f32: ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD ; SI-CHECK-LABEL: {{^}}store_v2f32: -; SI-CHECK: BUFFER_STORE_DWORDX2 +; SI-CHECK: buffer_store_dwordx2 define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) { entry: @@ -170,7 +170,7 @@ entry: ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD ; CM-CHECK-NOT: MEM_RAT_CACHELESS STORE_DWORD ; SI-CHECK-LABEL: {{^}}store_v4i32: -; SI-CHECK: BUFFER_STORE_DWORDX4 +; SI-CHECK: buffer_store_dwordx4 define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) { entry: store <4 x i32> %in, <4 x i32> addrspace(1)* %out @@ -179,7 +179,7 @@ entry: ; FUNC-LABEL: {{^}}store_i64_i8: ; EG-CHECK: MEM_RAT MSKOR -; SI-CHECK: BUFFER_STORE_BYTE +; SI-CHECK: buffer_store_byte define void @store_i64_i8(i8 addrspace(1)* %out, i64 %in) { entry: %0 = trunc i64 %in to i8 @@ -189,7 +189,7 @@ entry: ; FUNC-LABEL: {{^}}store_i64_i16: ; EG-CHECK: MEM_RAT MSKOR -; SI-CHECK: BUFFER_STORE_SHORT +; SI-CHECK: buffer_store_short define void @store_i64_i16(i16 addrspace(1)* %out, i64 %in) { entry: %0 = trunc i64 %in to i16 @@ -203,7 +203,7 @@ entry: ; FUNC-LABEL: {{^}}store_local_i1: ; EG-CHECK: LDS_BYTE_WRITE -; SI-CHECK: DS_WRITE_B8 +; SI-CHECK: ds_write_b8 define void @store_local_i1(i1 addrspace(3)* %out) { entry: store i1 true, i1 addrspace(3)* %out @@ -213,7 +213,7 @@ entry: ; EG-CHECK-LABEL: {{^}}store_local_i8: ; EG-CHECK: LDS_BYTE_WRITE ; SI-CHECK-LABEL: {{^}}store_local_i8: -; SI-CHECK: DS_WRITE_B8 +; SI-CHECK: ds_write_b8 define void @store_local_i8(i8 addrspace(3)* %out, i8 %in) { store i8 %in, i8 addrspace(3)* %out ret void @@ -222,7 +222,7 @@ define void @store_local_i8(i8 addrspace(3)* %out, i8 %in) { ; EG-CHECK-LABEL: {{^}}store_local_i16: ; EG-CHECK: LDS_SHORT_WRITE ; SI-CHECK-LABEL: {{^}}store_local_i16: -; SI-CHECK: DS_WRITE_B16 +; SI-CHECK: ds_write_b16 define void @store_local_i16(i16 addrspace(3)* %out, i16 %in) { store i16 %in, i16 addrspace(3)* %out ret void @@ -233,8 +233,8 @@ define void @store_local_i16(i16 addrspace(3)* %out, i16 %in) { ; CM-CHECK-LABEL: {{^}}store_local_v2i16: ; CM-CHECK: LDS_WRITE ; SI-CHECK-LABEL: {{^}}store_local_v2i16: -; SI-CHECK: DS_WRITE_B16 -; SI-CHECK: DS_WRITE_B16 +; SI-CHECK: ds_write_b16 +; SI-CHECK: ds_write_b16 define void @store_local_v2i16(<2 x i16> addrspace(3)* %out, <2 x i16> %in) { entry: store <2 x i16> %in, <2 x i16> addrspace(3)* %out @@ -246,10 +246,10 @@ entry: ; CM-CHECK-LABEL: {{^}}store_local_v4i8: ; CM-CHECK: LDS_WRITE ; SI-CHECK-LABEL: {{^}}store_local_v4i8: -; SI-CHECK: DS_WRITE_B8 -; SI-CHECK: DS_WRITE_B8 -; SI-CHECK: DS_WRITE_B8 -; SI-CHECK: DS_WRITE_B8 +; SI-CHECK: ds_write_b8 +; SI-CHECK: ds_write_b8 +; SI-CHECK: ds_write_b8 +; SI-CHECK: ds_write_b8 define void @store_local_v4i8(<4 x i8> addrspace(3)* %out, <4 x i8> %in) { entry: store <4 x i8> %in, <4 x i8> addrspace(3)* %out @@ -263,7 +263,7 @@ entry: ; CM-CHECK: LDS_WRITE ; CM-CHECK: LDS_WRITE ; SI-CHECK-LABEL: {{^}}store_local_v2i32: -; SI-CHECK: DS_WRITE_B64 +; SI-CHECK: ds_write_b64 define void @store_local_v2i32(<2 x i32> addrspace(3)* %out, <2 x i32> %in) { entry: store <2 x i32> %in, <2 x i32> addrspace(3)* %out @@ -281,10 +281,10 @@ entry: ; CM-CHECK: LDS_WRITE ; CM-CHECK: LDS_WRITE ; SI-CHECK-LABEL: {{^}}store_local_v4i32: -; SI-CHECK: DS_WRITE_B32 -; SI-CHECK: DS_WRITE_B32 -; SI-CHECK: DS_WRITE_B32 -; SI-CHECK: DS_WRITE_B32 +; SI-CHECK: ds_write_b32 +; SI-CHECK: ds_write_b32 +; SI-CHECK: ds_write_b32 +; SI-CHECK: ds_write_b32 define void @store_local_v4i32(<4 x i32> addrspace(3)* %out, <4 x i32> %in) { entry: store <4 x i32> %in, <4 x i32> addrspace(3)* %out @@ -293,7 +293,7 @@ entry: ; FUNC-LABEL: {{^}}store_local_i64_i8: ; EG-CHECK: LDS_BYTE_WRITE -; SI-CHECK: DS_WRITE_B8 +; SI-CHECK: ds_write_b8 define void @store_local_i64_i8(i8 addrspace(3)* %out, i64 %in) { entry: %0 = trunc i64 %in to i8 @@ -303,7 +303,7 @@ entry: ; FUNC-LABEL: {{^}}store_local_i64_i16: ; EG-CHECK: LDS_SHORT_WRITE -; SI-CHECK: DS_WRITE_B16 +; SI-CHECK: ds_write_b16 define void @store_local_i64_i16(i16 addrspace(3)* %out, i64 %in) { entry: %0 = trunc i64 %in to i16 @@ -323,7 +323,7 @@ entry: ; CM-CHECK-LABEL: {{^}}vecload2: ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD ; SI-CHECK-LABEL: {{^}}vecload2: -; SI-CHECK: BUFFER_STORE_DWORDX2 +; SI-CHECK: buffer_store_dwordx2 define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 { entry: %0 = load i32 addrspace(2)* %mem, align 4 @@ -349,8 +349,8 @@ attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"= ; CM-CHECK: STORE_DWORD ; CM-CHECK: STORE_DWORD ; CM-CHECK: STORE_DWORD -; SI: BUFFER_STORE_DWORDX2 -; SI: BUFFER_STORE_DWORDX2 +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 define void @i128-const-store(i32 addrspace(1)* %out) { entry: store i32 1, i32 addrspace(1)* %out, align 4 diff --git a/test/CodeGen/R600/sub.ll b/test/CodeGen/R600/sub.ll index bcdb53e6874..2bbc0cf3771 100644 --- a/test/CodeGen/R600/sub.ll +++ b/test/CodeGen/R600/sub.ll @@ -7,8 +7,8 @@ declare i32 @llvm.r600.read.tidig.x() readnone ;EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -25,10 +25,10 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { ;EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 @@ -40,8 +40,8 @@ define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}s_sub_i64: -; SI: S_SUB_U32 -; SI: S_SUBB_U32 +; SI: s_sub_u32 +; SI: s_subb_u32 ; EG-DAG: SETGE_UINT ; EG-DAG: CNDE_INT @@ -55,8 +55,8 @@ define void @s_sub_i64(i64 addrspace(1)* noalias %out, i64 %a, i64 %b) nounwind } ; FUNC-LABEL: {{^}}v_sub_i64: -; SI: V_SUB_I32_e32 -; SI: V_SUBB_U32_e32 +; SI: v_sub_i32_e32 +; SI: v_subb_u32_e32 ; EG-DAG: SETGE_UINT ; EG-DAG: CNDE_INT diff --git a/test/CodeGen/R600/trunc-store-i1.ll b/test/CodeGen/R600/trunc-store-i1.ll index 0e6f49daf6f..3c1b19fb021 100644 --- a/test/CodeGen/R600/trunc-store-i1.ll +++ b/test/CodeGen/R600/trunc-store-i1.ll @@ -2,10 +2,10 @@ ; SI-LABEL: {{^}}global_truncstore_i32_to_i1: -; SI: S_LOAD_DWORD [[LOAD:s[0-9]+]], -; SI: S_AND_B32 [[SREG:s[0-9]+]], [[LOAD]], 1 -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], [[SREG]] -; SI: BUFFER_STORE_BYTE [[VREG]], +; SI: s_load_dword [[LOAD:s[0-9]+]], +; SI: s_and_b32 [[SREG:s[0-9]+]], [[LOAD]], 1 +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]] +; SI: buffer_store_byte [[VREG]], define void @global_truncstore_i32_to_i1(i1 addrspace(1)* %out, i32 %val) nounwind { %trunc = trunc i32 %val to i1 store i1 %trunc, i1 addrspace(1)* %out, align 1 @@ -13,7 +13,7 @@ define void @global_truncstore_i32_to_i1(i1 addrspace(1)* %out, i32 %val) nounwi } ; SI-LABEL: {{^}}global_truncstore_i64_to_i1: -; SI: BUFFER_STORE_BYTE +; SI: buffer_store_byte define void @global_truncstore_i64_to_i1(i1 addrspace(1)* %out, i64 %val) nounwind { %trunc = trunc i64 %val to i1 store i1 %trunc, i1 addrspace(1)* %out, align 1 @@ -21,10 +21,10 @@ define void @global_truncstore_i64_to_i1(i1 addrspace(1)* %out, i64 %val) nounwi } ; SI-LABEL: {{^}}global_truncstore_i16_to_i1: -; SI: S_LOAD_DWORD [[LOAD:s[0-9]+]], -; SI: S_AND_B32 [[SREG:s[0-9]+]], [[LOAD]], 1 -; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], [[SREG]] -; SI: BUFFER_STORE_BYTE [[VREG]], +; SI: s_load_dword [[LOAD:s[0-9]+]], +; SI: s_and_b32 [[SREG:s[0-9]+]], [[LOAD]], 1 +; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]] +; SI: buffer_store_byte [[VREG]], define void @global_truncstore_i16_to_i1(i1 addrspace(1)* %out, i16 %val) nounwind { %trunc = trunc i16 %val to i1 store i1 %trunc, i1 addrspace(1)* %out, align 1 diff --git a/test/CodeGen/R600/trunc.ll b/test/CodeGen/R600/trunc.ll index 16c57f7f386..7519d10f92b 100644 --- a/test/CodeGen/R600/trunc.ll +++ b/test/CodeGen/R600/trunc.ll @@ -3,9 +3,9 @@ define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) { ; SI-LABEL: {{^}}trunc_i64_to_i32_store: -; SI: S_LOAD_DWORD [[SLOAD:s[0-9]+]], s[0:1], 0xb -; SI: V_MOV_B32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]] -; SI: BUFFER_STORE_DWORD [[VLOAD]] +; SI: s_load_dword [[SLOAD:s[0-9]+]], s[0:1], 0xb +; SI: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]] +; SI: buffer_store_dword [[VLOAD]] ; EG-LABEL: {{^}}trunc_i64_to_i32_store: ; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 @@ -17,11 +17,11 @@ define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) { } ; SI-LABEL: {{^}}trunc_load_shl_i64: -; SI-DAG: S_LOAD_DWORDX2 -; SI-DAG: S_LOAD_DWORD [[SREG:s[0-9]+]], -; SI: S_LSHL_B32 [[SHL:s[0-9]+]], [[SREG]], 2 -; SI: V_MOV_B32_e32 [[VSHL:v[0-9]+]], [[SHL]] -; SI: BUFFER_STORE_DWORD [[VSHL]], +; SI-DAG: s_load_dwordx2 +; SI-DAG: s_load_dword [[SREG:s[0-9]+]], +; SI: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2 +; SI: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]] +; SI: buffer_store_dword [[VSHL]], define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) { %b = shl i64 %a, 2 %result = trunc i64 %b to i32 @@ -30,12 +30,12 @@ define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) { } ; SI-LABEL: {{^}}trunc_shl_i64: -; SI: S_LOAD_DWORDX2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI: S_LSHL_B64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2 -; SI: S_ADD_U32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]], -; SI: S_ADDC_U32 -; SI: V_MOV_B32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]] -; SI: BUFFER_STORE_DWORD v[[LO_VREG]], +; SI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd +; SI: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2 +; SI: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]], +; SI: s_addc_u32 +; SI: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]] +; SI: buffer_store_dword v[[LO_VREG]], define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) { %aa = add i64 %a, 234 ; Prevent shrinking store. %b = shl i64 %aa, 2 @@ -46,8 +46,8 @@ define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 } ; SI-LABEL: {{^}}trunc_i32_to_i1: -; SI: V_AND_B32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} -; SI: V_CMP_EQ_I32 +; SI: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} +; SI: v_cmp_eq_i32 define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) { %a = load i32 addrspace(1)* %ptr, align 4 %trunc = trunc i32 %a to i1 @@ -57,8 +57,8 @@ define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) { } ; SI-LABEL: {{^}}sgpr_trunc_i32_to_i1: -; SI: V_AND_B32_e64 v{{[0-9]+}}, 1, s{{[0-9]+}} -; SI: V_CMP_EQ_I32 +; SI: v_and_b32_e64 v{{[0-9]+}}, 1, s{{[0-9]+}} +; SI: v_cmp_eq_i32 define void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) { %trunc = trunc i32 %a to i1 %result = select i1 %trunc, i32 1, i32 0 diff --git a/test/CodeGen/R600/uaddo.ll b/test/CodeGen/R600/uaddo.ll index acdbb18fd3c..eb242c1d864 100644 --- a/test/CodeGen/R600/uaddo.ll +++ b/test/CodeGen/R600/uaddo.ll @@ -5,9 +5,9 @@ declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone ; FUNC-LABEL: {{^}}uaddo_i64_zext: -; SI: ADD -; SI: ADDC -; SI: ADDC +; SI: add +; SI: addc +; SI: addc define void @uaddo_i64_zext(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { %uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) nounwind %val = extractvalue { i64, i1 } %uadd, 0 @@ -19,7 +19,7 @@ define void @uaddo_i64_zext(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { } ; FUNC-LABEL: {{^}}s_uaddo_i32: -; SI: S_ADD_I32 +; SI: s_add_i32 define void @s_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) nounwind { %uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) nounwind %val = extractvalue { i32, i1 } %uadd, 0 @@ -30,7 +30,7 @@ define void @s_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 } ; FUNC-LABEL: {{^}}v_uaddo_i32: -; SI: V_ADD_I32 +; SI: v_add_i32 define void @v_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind { %a = load i32 addrspace(1)* %aptr, align 4 %b = load i32 addrspace(1)* %bptr, align 4 @@ -43,8 +43,8 @@ define void @v_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 } ; FUNC-LABEL: {{^}}s_uaddo_i64: -; SI: S_ADD_U32 -; SI: S_ADDC_U32 +; SI: s_add_u32 +; SI: s_addc_u32 define void @s_uaddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a, i64 %b) nounwind { %uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) nounwind %val = extractvalue { i64, i1 } %uadd, 0 @@ -55,8 +55,8 @@ define void @s_uaddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 } ; FUNC-LABEL: {{^}}v_uaddo_i64: -; SI: V_ADD_I32 -; SI: V_ADDC_U32 +; SI: v_add_i32 +; SI: v_addc_u32 define void @v_uaddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind { %a = load i64 addrspace(1)* %aptr, align 4 %b = load i64 addrspace(1)* %bptr, align 4 diff --git a/test/CodeGen/R600/udiv.ll b/test/CodeGen/R600/udiv.ll index 6f05e8526f3..59e91f8986c 100644 --- a/test/CodeGen/R600/udiv.ll +++ b/test/CodeGen/R600/udiv.ll @@ -21,7 +21,7 @@ define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ;EG-CHECK-LABEL: {{^}}test2: ;EG-CHECK: CF_END ;SI-CHECK-LABEL: {{^}}test2: -;SI-CHECK: S_ENDPGM +;SI-CHECK: s_endpgm define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -35,7 +35,7 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { ;EG-CHECK-LABEL: {{^}}test4: ;EG-CHECK: CF_END ;SI-CHECK-LABEL: {{^}}test4: -;SI-CHECK: S_ENDPGM +;SI-CHECK: s_endpgm define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 diff --git a/test/CodeGen/R600/udivrem.ll b/test/CodeGen/R600/udivrem.ll index 57db20f188f..9112d032ffd 100644 --- a/test/CodeGen/R600/udivrem.ll +++ b/test/CodeGen/R600/udivrem.ll @@ -26,30 +26,30 @@ ; EG-DAG: CNDE_INT ; EG-DAG: CNDE_INT -; SI: V_RCP_IFLAG_F32_e32 [[RCP:v[0-9]+]] -; SI-DAG: V_MUL_HI_U32 [[RCP_HI:v[0-9]+]], [[RCP]] -; SI-DAG: V_MUL_LO_I32 [[RCP_LO:v[0-9]+]], [[RCP]] -; SI-DAG: V_SUB_I32_e32 [[NEG_RCP_LO:v[0-9]+]], 0, [[RCP_LO]] -; SI: V_CNDMASK_B32_e64 -; SI: V_MUL_HI_U32 [[E:v[0-9]+]], {{v[0-9]+}}, [[RCP]] -; SI-DAG: V_ADD_I32_e32 [[RCP_A_E:v[0-9]+]], [[E]], [[RCP]] -; SI-DAG: V_SUBREV_I32_e32 [[RCP_S_E:v[0-9]+]], [[E]], [[RCP]] -; SI: V_CNDMASK_B32_e64 -; SI: V_MUL_HI_U32 [[Quotient:v[0-9]+]] -; SI: V_MUL_LO_I32 [[Num_S_Remainder:v[0-9]+]] -; SI-DAG: V_SUB_I32_e32 [[Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[Num_S_Remainder]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI: V_AND_B32_e32 [[Tmp1:v[0-9]+]] -; SI-DAG: V_ADD_I32_e32 [[Quotient_A_One:v[0-9]+]], 1, [[Quotient]] -; SI-DAG: V_SUBREV_I32_e32 [[Quotient_S_One:v[0-9]+]], -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_ADD_I32_e32 [[Remainder_A_Den:v[0-9]+]], -; SI-DAG: V_SUBREV_I32_e32 [[Remainder_S_Den:v[0-9]+]], -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI: S_ENDPGM +; SI: v_rcp_iflag_f32_e32 [[RCP:v[0-9]+]] +; SI-DAG: v_mul_hi_u32 [[RCP_HI:v[0-9]+]], [[RCP]] +; SI-DAG: v_mul_lo_i32 [[RCP_LO:v[0-9]+]], [[RCP]] +; SI-DAG: v_sub_i32_e32 [[NEG_RCP_LO:v[0-9]+]], 0, [[RCP_LO]] +; SI: v_cndmask_b32_e64 +; SI: v_mul_hi_u32 [[E:v[0-9]+]], {{v[0-9]+}}, [[RCP]] +; SI-DAG: v_add_i32_e32 [[RCP_A_E:v[0-9]+]], [[E]], [[RCP]] +; SI-DAG: v_subrev_i32_e32 [[RCP_S_E:v[0-9]+]], [[E]], [[RCP]] +; SI: v_cndmask_b32_e64 +; SI: v_mul_hi_u32 [[Quotient:v[0-9]+]] +; SI: v_mul_lo_i32 [[Num_S_Remainder:v[0-9]+]] +; SI-DAG: v_sub_i32_e32 [[Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[Num_S_Remainder]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI: v_and_b32_e32 [[Tmp1:v[0-9]+]] +; SI-DAG: v_add_i32_e32 [[Quotient_A_One:v[0-9]+]], 1, [[Quotient]] +; SI-DAG: v_subrev_i32_e32 [[Quotient_S_One:v[0-9]+]], +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_add_i32_e32 [[Remainder_A_Den:v[0-9]+]], +; SI-DAG: v_subrev_i32_e32 [[Remainder_S_Den:v[0-9]+]], +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI: s_endpgm define void @test_udivrem(i32 addrspace(1)* %out, i32 %x, i32 %y) { %result0 = udiv i32 %x, %y store i32 %result0, i32 addrspace(1)* %out @@ -106,53 +106,53 @@ define void @test_udivrem(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; EG-DAG: CNDE_INT ; EG-DAG: CNDE_INT -; SI-DAG: V_RCP_IFLAG_F32_e32 [[FIRST_RCP:v[0-9]+]] -; SI-DAG: V_MUL_HI_U32 [[FIRST_RCP_HI:v[0-9]+]], [[FIRST_RCP]] -; SI-DAG: V_MUL_LO_I32 [[FIRST_RCP_LO:v[0-9]+]], [[FIRST_RCP]] -; SI-DAG: V_SUB_I32_e32 [[FIRST_NEG_RCP_LO:v[0-9]+]], 0, [[FIRST_RCP_LO]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_MUL_HI_U32 [[FIRST_E:v[0-9]+]], {{v[0-9]+}}, [[FIRST_RCP]] -; SI-DAG: V_ADD_I32_e32 [[FIRST_RCP_A_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]] -; SI-DAG: V_SUBREV_I32_e32 [[FIRST_RCP_S_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_MUL_HI_U32 [[FIRST_Quotient:v[0-9]+]] -; SI-DAG: V_MUL_LO_I32 [[FIRST_Num_S_Remainder:v[0-9]+]] -; SI-DAG: V_SUB_I32_e32 [[FIRST_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[FIRST_Num_S_Remainder]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_AND_B32_e32 [[FIRST_Tmp1:v[0-9]+]] -; SI-DAG: V_ADD_I32_e32 [[FIRST_Quotient_A_One:v[0-9]+]], {{.*}}, [[FIRST_Quotient]] -; SI-DAG: V_SUBREV_I32_e32 [[FIRST_Quotient_S_One:v[0-9]+]], -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_ADD_I32_e32 [[FIRST_Remainder_A_Den:v[0-9]+]], -; SI-DAG: V_SUBREV_I32_e32 [[FIRST_Remainder_S_Den:v[0-9]+]], -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_RCP_IFLAG_F32_e32 [[SECOND_RCP:v[0-9]+]] -; SI-DAG: V_MUL_HI_U32 [[SECOND_RCP_HI:v[0-9]+]], [[SECOND_RCP]] -; SI-DAG: V_MUL_LO_I32 [[SECOND_RCP_LO:v[0-9]+]], [[SECOND_RCP]] -; SI-DAG: V_SUB_I32_e32 [[SECOND_NEG_RCP_LO:v[0-9]+]], 0, [[SECOND_RCP_LO]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_MUL_HI_U32 [[SECOND_E:v[0-9]+]], {{v[0-9]+}}, [[SECOND_RCP]] -; SI-DAG: V_ADD_I32_e32 [[SECOND_RCP_A_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]] -; SI-DAG: V_SUBREV_I32_e32 [[SECOND_RCP_S_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_MUL_HI_U32 [[SECOND_Quotient:v[0-9]+]] -; SI-DAG: V_MUL_LO_I32 [[SECOND_Num_S_Remainder:v[0-9]+]] -; SI-DAG: V_SUB_I32_e32 [[SECOND_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[SECOND_Num_S_Remainder]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_AND_B32_e32 [[SECOND_Tmp1:v[0-9]+]] -; SI-DAG: V_ADD_I32_e32 [[SECOND_Quotient_A_One:v[0-9]+]], {{.*}}, [[SECOND_Quotient]] -; SI-DAG: V_SUBREV_I32_e32 [[SECOND_Quotient_S_One:v[0-9]+]], -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_ADD_I32_e32 [[SECOND_Remainder_A_Den:v[0-9]+]], -; SI-DAG: V_SUBREV_I32_e32 [[SECOND_Remainder_S_Den:v[0-9]+]], -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI: S_ENDPGM +; SI-DAG: v_rcp_iflag_f32_e32 [[FIRST_RCP:v[0-9]+]] +; SI-DAG: v_mul_hi_u32 [[FIRST_RCP_HI:v[0-9]+]], [[FIRST_RCP]] +; SI-DAG: v_mul_lo_i32 [[FIRST_RCP_LO:v[0-9]+]], [[FIRST_RCP]] +; SI-DAG: v_sub_i32_e32 [[FIRST_NEG_RCP_LO:v[0-9]+]], 0, [[FIRST_RCP_LO]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_mul_hi_u32 [[FIRST_E:v[0-9]+]], {{v[0-9]+}}, [[FIRST_RCP]] +; SI-DAG: v_add_i32_e32 [[FIRST_RCP_A_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]] +; SI-DAG: v_subrev_i32_e32 [[FIRST_RCP_S_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_mul_hi_u32 [[FIRST_Quotient:v[0-9]+]] +; SI-DAG: v_mul_lo_i32 [[FIRST_Num_S_Remainder:v[0-9]+]] +; SI-DAG: v_sub_i32_e32 [[FIRST_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[FIRST_Num_S_Remainder]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_and_b32_e32 [[FIRST_Tmp1:v[0-9]+]] +; SI-DAG: v_add_i32_e32 [[FIRST_Quotient_A_One:v[0-9]+]], {{.*}}, [[FIRST_Quotient]] +; SI-DAG: v_subrev_i32_e32 [[FIRST_Quotient_S_One:v[0-9]+]], +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_add_i32_e32 [[FIRST_Remainder_A_Den:v[0-9]+]], +; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder_S_Den:v[0-9]+]], +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_rcp_iflag_f32_e32 [[SECOND_RCP:v[0-9]+]] +; SI-DAG: v_mul_hi_u32 [[SECOND_RCP_HI:v[0-9]+]], [[SECOND_RCP]] +; SI-DAG: v_mul_lo_i32 [[SECOND_RCP_LO:v[0-9]+]], [[SECOND_RCP]] +; SI-DAG: v_sub_i32_e32 [[SECOND_NEG_RCP_LO:v[0-9]+]], 0, [[SECOND_RCP_LO]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_mul_hi_u32 [[SECOND_E:v[0-9]+]], {{v[0-9]+}}, [[SECOND_RCP]] +; SI-DAG: v_add_i32_e32 [[SECOND_RCP_A_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]] +; SI-DAG: v_subrev_i32_e32 [[SECOND_RCP_S_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_mul_hi_u32 [[SECOND_Quotient:v[0-9]+]] +; SI-DAG: v_mul_lo_i32 [[SECOND_Num_S_Remainder:v[0-9]+]] +; SI-DAG: v_sub_i32_e32 [[SECOND_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[SECOND_Num_S_Remainder]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_and_b32_e32 [[SECOND_Tmp1:v[0-9]+]] +; SI-DAG: v_add_i32_e32 [[SECOND_Quotient_A_One:v[0-9]+]], {{.*}}, [[SECOND_Quotient]] +; SI-DAG: v_subrev_i32_e32 [[SECOND_Quotient_S_One:v[0-9]+]], +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_add_i32_e32 [[SECOND_Remainder_A_Den:v[0-9]+]], +; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder_S_Den:v[0-9]+]], +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI: s_endpgm define void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) { %result0 = udiv <2 x i32> %x, %y store <2 x i32> %result0, <2 x i32> addrspace(1)* %out @@ -256,99 +256,99 @@ define void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i3 ; EG-DAG: CNDE_INT ; EG-DAG: CNDE_INT -; SI-DAG: V_RCP_IFLAG_F32_e32 [[FIRST_RCP:v[0-9]+]] -; SI-DAG: V_MUL_HI_U32 [[FIRST_RCP_HI:v[0-9]+]], [[FIRST_RCP]] -; SI-DAG: V_MUL_LO_I32 [[FIRST_RCP_LO:v[0-9]+]], [[FIRST_RCP]] -; SI-DAG: V_SUB_I32_e32 [[FIRST_NEG_RCP_LO:v[0-9]+]], 0, [[FIRST_RCP_LO]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_MUL_HI_U32 [[FIRST_E:v[0-9]+]], {{v[0-9]+}}, [[FIRST_RCP]] -; SI-DAG: V_ADD_I32_e32 [[FIRST_RCP_A_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]] -; SI-DAG: V_SUBREV_I32_e32 [[FIRST_RCP_S_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_MUL_HI_U32 [[FIRST_Quotient:v[0-9]+]] -; SI-DAG: V_MUL_LO_I32 [[FIRST_Num_S_Remainder:v[0-9]+]] -; SI-DAG: V_SUB_I32_e32 [[FIRST_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[FIRST_Num_S_Remainder]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_AND_B32_e32 [[FIRST_Tmp1:v[0-9]+]] -; SI-DAG: V_ADD_I32_e32 [[FIRST_Quotient_A_One:v[0-9]+]], {{.*}}, [[FIRST_Quotient]] -; SI-DAG: V_SUBREV_I32_e32 [[FIRST_Quotient_S_One:v[0-9]+]], -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_ADD_I32_e32 [[FIRST_Remainder_A_Den:v[0-9]+]], -; SI-DAG: V_SUBREV_I32_e32 [[FIRST_Remainder_S_Den:v[0-9]+]], -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_RCP_IFLAG_F32_e32 [[SECOND_RCP:v[0-9]+]] -; SI-DAG: V_MUL_HI_U32 [[SECOND_RCP_HI:v[0-9]+]], [[SECOND_RCP]] -; SI-DAG: V_MUL_LO_I32 [[SECOND_RCP_LO:v[0-9]+]], [[SECOND_RCP]] -; SI-DAG: V_SUB_I32_e32 [[SECOND_NEG_RCP_LO:v[0-9]+]], 0, [[SECOND_RCP_LO]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_MUL_HI_U32 [[SECOND_E:v[0-9]+]], {{v[0-9]+}}, [[SECOND_RCP]] -; SI-DAG: V_ADD_I32_e32 [[SECOND_RCP_A_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]] -; SI-DAG: V_SUBREV_I32_e32 [[SECOND_RCP_S_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_MUL_HI_U32 [[SECOND_Quotient:v[0-9]+]] -; SI-DAG: V_MUL_LO_I32 [[SECOND_Num_S_Remainder:v[0-9]+]] -; SI-DAG: V_SUB_I32_e32 [[SECOND_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[SECOND_Num_S_Remainder]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_AND_B32_e32 [[SECOND_Tmp1:v[0-9]+]] -; SI-DAG: V_ADD_I32_e32 [[SECOND_Quotient_A_One:v[0-9]+]], {{.*}}, [[SECOND_Quotient]] -; SI-DAG: V_SUBREV_I32_e32 [[SECOND_Quotient_S_One:v[0-9]+]], -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_ADD_I32_e32 [[SECOND_Remainder_A_Den:v[0-9]+]], -; SI-DAG: V_SUBREV_I32_e32 [[SECOND_Remainder_S_Den:v[0-9]+]], -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_RCP_IFLAG_F32_e32 [[THIRD_RCP:v[0-9]+]] -; SI-DAG: V_MUL_HI_U32 [[THIRD_RCP_HI:v[0-9]+]], [[THIRD_RCP]] -; SI-DAG: V_MUL_LO_I32 [[THIRD_RCP_LO:v[0-9]+]], [[THIRD_RCP]] -; SI-DAG: V_SUB_I32_e32 [[THIRD_NEG_RCP_LO:v[0-9]+]], 0, [[THIRD_RCP_LO]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_MUL_HI_U32 [[THIRD_E:v[0-9]+]], {{v[0-9]+}}, [[THIRD_RCP]] -; SI-DAG: V_ADD_I32_e32 [[THIRD_RCP_A_E:v[0-9]+]], [[THIRD_E]], [[THIRD_RCP]] -; SI-DAG: V_SUBREV_I32_e32 [[THIRD_RCP_S_E:v[0-9]+]], [[THIRD_E]], [[THIRD_RCP]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_MUL_HI_U32 [[THIRD_Quotient:v[0-9]+]] -; SI-DAG: V_MUL_LO_I32 [[THIRD_Num_S_Remainder:v[0-9]+]] -; SI-DAG: V_SUB_I32_e32 [[THIRD_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[THIRD_Num_S_Remainder]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_AND_B32_e32 [[THIRD_Tmp1:v[0-9]+]] -; SI-DAG: V_ADD_I32_e32 [[THIRD_Quotient_A_One:v[0-9]+]], {{.*}}, [[THIRD_Quotient]] -; SI-DAG: V_SUBREV_I32_e32 [[THIRD_Quotient_S_One:v[0-9]+]], -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_ADD_I32_e32 [[THIRD_Remainder_A_Den:v[0-9]+]], -; SI-DAG: V_SUBREV_I32_e32 [[THIRD_Remainder_S_Den:v[0-9]+]], -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_RCP_IFLAG_F32_e32 [[FOURTH_RCP:v[0-9]+]] -; SI-DAG: V_MUL_HI_U32 [[FOURTH_RCP_HI:v[0-9]+]], [[FOURTH_RCP]] -; SI-DAG: V_MUL_LO_I32 [[FOURTH_RCP_LO:v[0-9]+]], [[FOURTH_RCP]] -; SI-DAG: V_SUB_I32_e32 [[FOURTH_NEG_RCP_LO:v[0-9]+]], 0, [[FOURTH_RCP_LO]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_MUL_HI_U32 [[FOURTH_E:v[0-9]+]], {{v[0-9]+}}, [[FOURTH_RCP]] -; SI-DAG: V_ADD_I32_e32 [[FOURTH_RCP_A_E:v[0-9]+]], [[FOURTH_E]], [[FOURTH_RCP]] -; SI-DAG: V_SUBREV_I32_e32 [[FOURTH_RCP_S_E:v[0-9]+]], [[FOURTH_E]], [[FOURTH_RCP]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_MUL_HI_U32 [[FOURTH_Quotient:v[0-9]+]] -; SI-DAG: V_MUL_LO_I32 [[FOURTH_Num_S_Remainder:v[0-9]+]] -; SI-DAG: V_SUB_I32_e32 [[FOURTH_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[FOURTH_Num_S_Remainder]] -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_AND_B32_e32 [[FOURTH_Tmp1:v[0-9]+]] -; SI-DAG: V_ADD_I32_e32 [[FOURTH_Quotient_A_One:v[0-9]+]], {{.*}}, [[FOURTH_Quotient]] -; SI-DAG: V_SUBREV_I32_e32 [[FOURTH_Quotient_S_One:v[0-9]+]], -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_ADD_I32_e32 [[FOURTH_Remainder_A_Den:v[0-9]+]], -; SI-DAG: V_SUBREV_I32_e32 [[FOURTH_Remainder_S_Den:v[0-9]+]], -; SI-DAG: V_CNDMASK_B32_e64 -; SI-DAG: V_CNDMASK_B32_e64 -; SI: S_ENDPGM +; SI-DAG: v_rcp_iflag_f32_e32 [[FIRST_RCP:v[0-9]+]] +; SI-DAG: v_mul_hi_u32 [[FIRST_RCP_HI:v[0-9]+]], [[FIRST_RCP]] +; SI-DAG: v_mul_lo_i32 [[FIRST_RCP_LO:v[0-9]+]], [[FIRST_RCP]] +; SI-DAG: v_sub_i32_e32 [[FIRST_NEG_RCP_LO:v[0-9]+]], 0, [[FIRST_RCP_LO]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_mul_hi_u32 [[FIRST_E:v[0-9]+]], {{v[0-9]+}}, [[FIRST_RCP]] +; SI-DAG: v_add_i32_e32 [[FIRST_RCP_A_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]] +; SI-DAG: v_subrev_i32_e32 [[FIRST_RCP_S_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_mul_hi_u32 [[FIRST_Quotient:v[0-9]+]] +; SI-DAG: v_mul_lo_i32 [[FIRST_Num_S_Remainder:v[0-9]+]] +; SI-DAG: v_sub_i32_e32 [[FIRST_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[FIRST_Num_S_Remainder]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_and_b32_e32 [[FIRST_Tmp1:v[0-9]+]] +; SI-DAG: v_add_i32_e32 [[FIRST_Quotient_A_One:v[0-9]+]], {{.*}}, [[FIRST_Quotient]] +; SI-DAG: v_subrev_i32_e32 [[FIRST_Quotient_S_One:v[0-9]+]], +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_add_i32_e32 [[FIRST_Remainder_A_Den:v[0-9]+]], +; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder_S_Den:v[0-9]+]], +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_rcp_iflag_f32_e32 [[SECOND_RCP:v[0-9]+]] +; SI-DAG: v_mul_hi_u32 [[SECOND_RCP_HI:v[0-9]+]], [[SECOND_RCP]] +; SI-DAG: v_mul_lo_i32 [[SECOND_RCP_LO:v[0-9]+]], [[SECOND_RCP]] +; SI-DAG: v_sub_i32_e32 [[SECOND_NEG_RCP_LO:v[0-9]+]], 0, [[SECOND_RCP_LO]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_mul_hi_u32 [[SECOND_E:v[0-9]+]], {{v[0-9]+}}, [[SECOND_RCP]] +; SI-DAG: v_add_i32_e32 [[SECOND_RCP_A_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]] +; SI-DAG: v_subrev_i32_e32 [[SECOND_RCP_S_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_mul_hi_u32 [[SECOND_Quotient:v[0-9]+]] +; SI-DAG: v_mul_lo_i32 [[SECOND_Num_S_Remainder:v[0-9]+]] +; SI-DAG: v_sub_i32_e32 [[SECOND_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[SECOND_Num_S_Remainder]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_and_b32_e32 [[SECOND_Tmp1:v[0-9]+]] +; SI-DAG: v_add_i32_e32 [[SECOND_Quotient_A_One:v[0-9]+]], {{.*}}, [[SECOND_Quotient]] +; SI-DAG: v_subrev_i32_e32 [[SECOND_Quotient_S_One:v[0-9]+]], +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_add_i32_e32 [[SECOND_Remainder_A_Den:v[0-9]+]], +; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder_S_Den:v[0-9]+]], +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_rcp_iflag_f32_e32 [[THIRD_RCP:v[0-9]+]] +; SI-DAG: v_mul_hi_u32 [[THIRD_RCP_HI:v[0-9]+]], [[THIRD_RCP]] +; SI-DAG: v_mul_lo_i32 [[THIRD_RCP_LO:v[0-9]+]], [[THIRD_RCP]] +; SI-DAG: v_sub_i32_e32 [[THIRD_NEG_RCP_LO:v[0-9]+]], 0, [[THIRD_RCP_LO]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_mul_hi_u32 [[THIRD_E:v[0-9]+]], {{v[0-9]+}}, [[THIRD_RCP]] +; SI-DAG: v_add_i32_e32 [[THIRD_RCP_A_E:v[0-9]+]], [[THIRD_E]], [[THIRD_RCP]] +; SI-DAG: v_subrev_i32_e32 [[THIRD_RCP_S_E:v[0-9]+]], [[THIRD_E]], [[THIRD_RCP]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_mul_hi_u32 [[THIRD_Quotient:v[0-9]+]] +; SI-DAG: v_mul_lo_i32 [[THIRD_Num_S_Remainder:v[0-9]+]] +; SI-DAG: v_sub_i32_e32 [[THIRD_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[THIRD_Num_S_Remainder]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_and_b32_e32 [[THIRD_Tmp1:v[0-9]+]] +; SI-DAG: v_add_i32_e32 [[THIRD_Quotient_A_One:v[0-9]+]], {{.*}}, [[THIRD_Quotient]] +; SI-DAG: v_subrev_i32_e32 [[THIRD_Quotient_S_One:v[0-9]+]], +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_add_i32_e32 [[THIRD_Remainder_A_Den:v[0-9]+]], +; SI-DAG: v_subrev_i32_e32 [[THIRD_Remainder_S_Den:v[0-9]+]], +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_rcp_iflag_f32_e32 [[FOURTH_RCP:v[0-9]+]] +; SI-DAG: v_mul_hi_u32 [[FOURTH_RCP_HI:v[0-9]+]], [[FOURTH_RCP]] +; SI-DAG: v_mul_lo_i32 [[FOURTH_RCP_LO:v[0-9]+]], [[FOURTH_RCP]] +; SI-DAG: v_sub_i32_e32 [[FOURTH_NEG_RCP_LO:v[0-9]+]], 0, [[FOURTH_RCP_LO]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_mul_hi_u32 [[FOURTH_E:v[0-9]+]], {{v[0-9]+}}, [[FOURTH_RCP]] +; SI-DAG: v_add_i32_e32 [[FOURTH_RCP_A_E:v[0-9]+]], [[FOURTH_E]], [[FOURTH_RCP]] +; SI-DAG: v_subrev_i32_e32 [[FOURTH_RCP_S_E:v[0-9]+]], [[FOURTH_E]], [[FOURTH_RCP]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_mul_hi_u32 [[FOURTH_Quotient:v[0-9]+]] +; SI-DAG: v_mul_lo_i32 [[FOURTH_Num_S_Remainder:v[0-9]+]] +; SI-DAG: v_sub_i32_e32 [[FOURTH_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[FOURTH_Num_S_Remainder]] +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_and_b32_e32 [[FOURTH_Tmp1:v[0-9]+]] +; SI-DAG: v_add_i32_e32 [[FOURTH_Quotient_A_One:v[0-9]+]], {{.*}}, [[FOURTH_Quotient]] +; SI-DAG: v_subrev_i32_e32 [[FOURTH_Quotient_S_One:v[0-9]+]], +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_add_i32_e32 [[FOURTH_Remainder_A_Den:v[0-9]+]], +; SI-DAG: v_subrev_i32_e32 [[FOURTH_Remainder_S_Den:v[0-9]+]], +; SI-DAG: v_cndmask_b32_e64 +; SI-DAG: v_cndmask_b32_e64 +; SI: s_endpgm define void @test_udivrem_v4(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) { %result0 = udiv <4 x i32> %x, %y store <4 x i32> %result0, <4 x i32> addrspace(1)* %out diff --git a/test/CodeGen/R600/udivrem24.ll b/test/CodeGen/R600/udivrem24.ll index 191ab7a4cf2..defb3c099e2 100644 --- a/test/CodeGen/R600/udivrem24.ll +++ b/test/CodeGen/R600/udivrem24.ll @@ -2,10 +2,10 @@ ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}udiv24_i8: -; SI: V_CVT_F32_UBYTE -; SI: V_CVT_F32_UBYTE -; SI: V_RCP_F32 -; SI: V_CVT_U32_F32 +; SI: v_cvt_f32_ubyte +; SI: v_cvt_f32_ubyte +; SI: v_rcp_f32 +; SI: v_cvt_u32_f32 ; EG: UINT_TO_FLT ; EG-DAG: UINT_TO_FLT @@ -21,10 +21,10 @@ define void @udiv24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}udiv24_i16: -; SI: V_CVT_F32_U32 -; SI: V_CVT_F32_U32 -; SI: V_RCP_F32 -; SI: V_CVT_U32_F32 +; SI: v_cvt_f32_u32 +; SI: v_cvt_f32_u32 +; SI: v_rcp_f32 +; SI: v_cvt_u32_f32 ; EG: UINT_TO_FLT ; EG-DAG: UINT_TO_FLT @@ -40,10 +40,10 @@ define void @udiv24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}udiv24_i32: -; SI: V_CVT_F32_U32 -; SI-DAG: V_CVT_F32_U32 -; SI-DAG: V_RCP_F32 -; SI: V_CVT_U32_F32 +; SI: v_cvt_f32_u32 +; SI-DAG: v_cvt_f32_u32 +; SI-DAG: v_rcp_f32 +; SI: v_cvt_u32_f32 ; EG: UINT_TO_FLT ; EG-DAG: UINT_TO_FLT @@ -64,8 +64,8 @@ define void @udiv24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ; FUNC-LABEL: {{^}}udiv25_i32: ; RCP_IFLAG is for URECIP in the full 32b alg -; SI: V_RCP_IFLAG -; SI-NOT: V_RCP_F32 +; SI: v_rcp_iflag +; SI-NOT: v_rcp_f32 ; EG-NOT: UINT_TO_FLT ; EG-NOT: RECIP_IEEE @@ -84,8 +84,8 @@ define void @udiv25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ; FUNC-LABEL: {{^}}test_no_udiv24_i32_1: ; RCP_IFLAG is for URECIP in the full 32b alg -; SI: V_RCP_IFLAG -; SI-NOT: V_RCP_F32 +; SI: v_rcp_iflag +; SI-NOT: v_rcp_f32 ; EG-NOT: UINT_TO_FLT ; EG-NOT: RECIP_IEEE @@ -104,8 +104,8 @@ define void @test_no_udiv24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) ; FUNC-LABEL: {{^}}test_no_udiv24_i32_2: ; RCP_IFLAG is for URECIP in the full 32b alg -; SI: V_RCP_IFLAG -; SI-NOT: V_RCP_F32 +; SI: v_rcp_iflag +; SI-NOT: v_rcp_f32 ; EG-NOT: UINT_TO_FLT ; EG-NOT: RECIP_IEEE @@ -123,10 +123,10 @@ define void @test_no_udiv24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) } ; FUNC-LABEL: {{^}}urem24_i8: -; SI: V_CVT_F32_UBYTE -; SI: V_CVT_F32_UBYTE -; SI: V_RCP_F32 -; SI: V_CVT_U32_F32 +; SI: v_cvt_f32_ubyte +; SI: v_cvt_f32_ubyte +; SI: v_rcp_f32 +; SI: v_cvt_u32_f32 ; EG: UINT_TO_FLT ; EG-DAG: UINT_TO_FLT @@ -142,10 +142,10 @@ define void @urem24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}urem24_i16: -; SI: V_CVT_F32_U32 -; SI: V_CVT_F32_U32 -; SI: V_RCP_F32 -; SI: V_CVT_U32_F32 +; SI: v_cvt_f32_u32 +; SI: v_cvt_f32_u32 +; SI: v_rcp_f32 +; SI: v_cvt_u32_f32 ; EG: UINT_TO_FLT ; EG-DAG: UINT_TO_FLT @@ -161,10 +161,10 @@ define void @urem24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}urem24_i32: -; SI: V_CVT_F32_U32 -; SI: V_CVT_F32_U32 -; SI: V_RCP_F32 -; SI: V_CVT_U32_F32 +; SI: v_cvt_f32_u32 +; SI: v_cvt_f32_u32 +; SI: v_rcp_f32 +; SI: v_cvt_u32_f32 ; EG: UINT_TO_FLT ; EG-DAG: UINT_TO_FLT @@ -185,8 +185,8 @@ define void @urem24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ; FUNC-LABEL: {{^}}urem25_i32: ; RCP_IFLAG is for URECIP in the full 32b alg -; SI: V_RCP_IFLAG -; SI-NOT: V_RCP_F32 +; SI: v_rcp_iflag +; SI-NOT: v_rcp_f32 ; EG-NOT: UINT_TO_FLT ; EG-NOT: RECIP_IEEE @@ -205,8 +205,8 @@ define void @urem25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ; FUNC-LABEL: {{^}}test_no_urem24_i32_1: ; RCP_IFLAG is for URECIP in the full 32b alg -; SI: V_RCP_IFLAG -; SI-NOT: V_RCP_F32 +; SI: v_rcp_iflag +; SI-NOT: v_rcp_f32 ; EG-NOT: UINT_TO_FLT ; EG-NOT: RECIP_IEEE @@ -225,8 +225,8 @@ define void @test_no_urem24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) ; FUNC-LABEL: {{^}}test_no_urem24_i32_2: ; RCP_IFLAG is for URECIP in the full 32b alg -; SI: V_RCP_IFLAG -; SI-NOT: V_RCP_F32 +; SI: v_rcp_iflag +; SI-NOT: v_rcp_f32 ; EG-NOT: UINT_TO_FLT ; EG-NOT: RECIP_IEEE diff --git a/test/CodeGen/R600/udivrem64.ll b/test/CodeGen/R600/udivrem64.ll index caf8ebb28c6..8864c8368ee 100644 --- a/test/CodeGen/R600/udivrem64.ll +++ b/test/CodeGen/R600/udivrem64.ll @@ -34,7 +34,7 @@ ;EG: BFE_UINT ;EG: BFE_UINT ;EG: BFE_UINT -;SI: S_ENDPGM +;SI: s_endpgm define void @test_udiv(i64 addrspace(1)* %out, i64 %x, i64 %y) { %result = udiv i64 %x, %y store i64 %result, i64 addrspace(1)* %out @@ -74,7 +74,7 @@ define void @test_udiv(i64 addrspace(1)* %out, i64 %x, i64 %y) { ;EG: BFE_UINT ;EG: BFE_UINT ;EG: AND_INT {{.*}}, 1, -;SI: S_ENDPGM +;SI: s_endpgm define void @test_urem(i64 addrspace(1)* %out, i64 %x, i64 %y) { %result = urem i64 %x, %y store i64 %result, i64 addrspace(1)* %out diff --git a/test/CodeGen/R600/uint_to_fp.f64.ll b/test/CodeGen/R600/uint_to_fp.f64.ll index 1ce022904df..bddf700d0e8 100644 --- a/test/CodeGen/R600/uint_to_fp.f64.ll +++ b/test/CodeGen/R600/uint_to_fp.f64.ll @@ -3,8 +3,8 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone ; SI-LABEL: {{^}}uint_to_fp_f64_i32 -; SI: V_CVT_F64_U32_e32 -; SI: S_ENDPGM +; SI: v_cvt_f64_u32_e32 +; SI: s_endpgm define void @uint_to_fp_f64_i32(double addrspace(1)* %out, i32 %in) { %cast = uitofp i32 %in to double store double %cast, double addrspace(1)* %out, align 8 @@ -12,13 +12,13 @@ define void @uint_to_fp_f64_i32(double addrspace(1)* %out, i32 %in) { } ; SI-LABEL: {{^}}uint_to_fp_i1_f64: -; SI: V_CMP_EQ_I32_e64 [[CMP:s\[[0-9]+:[0-9]\]]], +; SI: v_cmp_eq_i32_e64 [[CMP:s\[[0-9]+:[0-9]\]]], ; FIXME: We should the VGPR sources for V_CNDMASK are copied from SGPRs, ; we should be able to fold the SGPRs into the V_CNDMASK instructions. -; SI: V_CNDMASK_B32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]] -; SI: V_CNDMASK_B32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]] -; SI: BUFFER_STORE_DWORDX2 -; SI: S_ENDPGM +; SI: v_cndmask_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]] +; SI: v_cndmask_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]] +; SI: buffer_store_dwordx2 +; SI: s_endpgm define void @uint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) { %cmp = icmp eq i32 %in, 0 %fp = uitofp i1 %cmp to double @@ -27,10 +27,10 @@ define void @uint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) { } ; SI-LABEL: {{^}}uint_to_fp_i1_f64_load: -; SI: V_CNDMASK_B32_e64 [[IRESULT:v[0-9]]], 0, 1 -; SI-NEXT: V_CVT_F64_U32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]] -; SI: BUFFER_STORE_DWORDX2 [[RESULT]] -; SI: S_ENDPGM +; SI: v_cndmask_b32_e64 [[IRESULT:v[0-9]]], 0, 1 +; SI-NEXT: v_cvt_f64_u32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]] +; SI: buffer_store_dwordx2 [[RESULT]] +; SI: s_endpgm define void @uint_to_fp_i1_f64_load(double addrspace(1)* %out, i1 %in) { %fp = uitofp i1 %in to double store double %fp, double addrspace(1)* %out, align 8 @@ -38,12 +38,12 @@ define void @uint_to_fp_i1_f64_load(double addrspace(1)* %out, i1 %in) { } ; SI-LABEL: {{^}}v_uint_to_fp_i64_to_f64 -; SI: BUFFER_LOAD_DWORDX2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} -; SI-DAG: V_CVT_F64_U32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]] -; SI-DAG: V_CVT_F64_U32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]] -; SI: V_LDEXP_F64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32 -; SI: V_ADD_F64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]] -; SI: BUFFER_STORE_DWORDX2 [[RESULT]] +; SI: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} +; SI-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]] +; SI-DAG: v_cvt_f64_u32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]] +; SI: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32 +; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]] +; SI: buffer_store_dwordx2 [[RESULT]] define void @v_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) { %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep = getelementptr i64 addrspace(1)* %in, i32 %tid diff --git a/test/CodeGen/R600/uint_to_fp.ll b/test/CodeGen/R600/uint_to_fp.ll index 657d6f8e22d..f58f10b9150 100644 --- a/test/CodeGen/R600/uint_to_fp.ll +++ b/test/CodeGen/R600/uint_to_fp.ll @@ -5,9 +5,9 @@ ; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W ; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X -; SI: V_CVT_F32_U32_e32 -; SI: V_CVT_F32_U32_e32 -; SI: S_ENDPGM +; SI: v_cvt_f32_u32_e32 +; SI: v_cvt_f32_u32_e32 +; SI: s_endpgm define void @uint_to_fp_v2i32(<2 x float> addrspace(1)* %out, <2 x i32> %in) { %result = uitofp <2 x i32> %in to <2 x float> store <2 x float> %result, <2 x float> addrspace(1)* %out @@ -20,11 +20,11 @@ define void @uint_to_fp_v2i32(<2 x float> addrspace(1)* %out, <2 x i32> %in) { ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; SI: V_CVT_F32_U32_e32 -; SI: V_CVT_F32_U32_e32 -; SI: V_CVT_F32_U32_e32 -; SI: V_CVT_F32_U32_e32 -; SI: S_ENDPGM +; SI: v_cvt_f32_u32_e32 +; SI: v_cvt_f32_u32_e32 +; SI: v_cvt_f32_u32_e32 +; SI: v_cvt_f32_u32_e32 +; SI: s_endpgm define void @uint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %value = load <4 x i32> addrspace(1) * %in %result = uitofp <4 x i32> %value to <4 x float> @@ -36,10 +36,10 @@ define void @uint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspac ; R600: UINT_TO_FLT ; R600: UINT_TO_FLT ; R600: MULADD_IEEE -; SI: V_CVT_F32_U32_e32 -; SI: V_CVT_F32_U32_e32 -; SI: V_MAD_F32 -; SI: S_ENDPGM +; SI: v_cvt_f32_u32_e32 +; SI: v_cvt_f32_u32_e32 +; SI: v_mad_f32 +; SI: s_endpgm define void @uint_to_fp_i64_f32(float addrspace(1)* %out, i64 %in) { entry: %0 = uitofp i64 %in to float @@ -48,10 +48,10 @@ entry: } ; FUNC-LABEL: {{^}}uint_to_fp_i1_f32: -; SI: V_CMP_EQ_I32_e64 [[CMP:s\[[0-9]+:[0-9]\]]], -; SI-NEXT: V_CNDMASK_B32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: v_cmp_eq_i32_e64 [[CMP:s\[[0-9]+:[0-9]\]]], +; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm define void @uint_to_fp_i1_f32(float addrspace(1)* %out, i32 %in) { %cmp = icmp eq i32 %in, 0 %fp = uitofp i1 %cmp to float @@ -60,9 +60,9 @@ define void @uint_to_fp_i1_f32(float addrspace(1)* %out, i32 %in) { } ; FUNC-LABEL: {{^}}uint_to_fp_i1_f32_load: -; SI: V_CNDMASK_B32_e64 [[RESULT:v[0-9]+]], 0, 1.0 -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0 +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm define void @uint_to_fp_i1_f32_load(float addrspace(1)* %out, i1 %in) { %fp = uitofp i1 %in to float store float %fp, float addrspace(1)* %out, align 4 diff --git a/test/CodeGen/R600/unaligned-load-store.ll b/test/CodeGen/R600/unaligned-load-store.ll index 47d052720c9..f8737e6f572 100644 --- a/test/CodeGen/R600/unaligned-load-store.ll +++ b/test/CodeGen/R600/unaligned-load-store.ll @@ -2,10 +2,10 @@ ; FIXME: This is probably wrong. This probably needs to expand to 8-bit reads and writes. ; SI-LABEL: {{^}}unaligned_load_store_i32: -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_WRITE_B32 -; SI: S_ENDPGM +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_write_b32 +; SI: s_endpgm define void @unaligned_load_store_i32(i32 addrspace(3)* %p, i32 addrspace(3)* %r) nounwind { %v = load i32 addrspace(3)* %p, align 1 store i32 %v, i32 addrspace(3)* %r, align 1 @@ -13,19 +13,19 @@ define void @unaligned_load_store_i32(i32 addrspace(3)* %p, i32 addrspace(3)* %r } ; SI-LABEL: {{^}}unaligned_load_store_v4i32: -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_READ_U16 -; SI: DS_WRITE_B32 -; SI: DS_WRITE_B32 -; SI: DS_WRITE_B32 -; SI: DS_WRITE_B32 -; SI: S_ENDPGM +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_read_u16 +; SI: ds_write_b32 +; SI: ds_write_b32 +; SI: ds_write_b32 +; SI: ds_write_b32 +; SI: s_endpgm define void @unaligned_load_store_v4i32(<4 x i32> addrspace(3)* %p, <4 x i32> addrspace(3)* %r) nounwind { %v = load <4 x i32> addrspace(3)* %p, align 1 store <4 x i32> %v, <4 x i32> addrspace(3)* %r, align 1 @@ -33,8 +33,8 @@ define void @unaligned_load_store_v4i32(<4 x i32> addrspace(3)* %p, <4 x i32> ad } ; SI-LABEL: {{^}}load_lds_i64_align_4: -; SI: DS_READ2_B32 -; SI: S_ENDPGM +; SI: ds_read2_b32 +; SI: s_endpgm define void @load_lds_i64_align_4(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 { %val = load i64 addrspace(3)* %in, align 4 store i64 %val, i64 addrspace(1)* %out, align 8 @@ -42,8 +42,8 @@ define void @load_lds_i64_align_4(i64 addrspace(1)* nocapture %out, i64 addrspac } ; SI-LABEL: {{^}}load_lds_i64_align_4_with_offset -; SI: DS_READ2_B32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset0:8 offset1:9 -; SI: S_ENDPGM +; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset0:8 offset1:9 +; SI: s_endpgm define void @load_lds_i64_align_4_with_offset(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 { %ptr = getelementptr i64 addrspace(3)* %in, i32 4 %val = load i64 addrspace(3)* %ptr, align 4 @@ -53,8 +53,8 @@ define void @load_lds_i64_align_4_with_offset(i64 addrspace(1)* nocapture %out, ; SI-LABEL: {{^}}load_lds_i64_align_4_with_split_offset: ; The tests for the case where the lo offset is 8-bits, but the hi offset is 9-bits -; SI: DS_READ2_B32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset0:0 offset1:1 -; SI: S_ENDPGM +; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset0:0 offset1:1 +; SI: s_endpgm define void @load_lds_i64_align_4_with_split_offset(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 { %ptr = bitcast i64 addrspace(3)* %in to i32 addrspace(3)* %ptr255 = getelementptr i32 addrspace(3)* %ptr, i32 255 @@ -72,16 +72,16 @@ define void @load_lds_i64_align_4_with_split_offset(i64 addrspace(1)* nocapture ; } ; SI-LABEL: {{^}}store_lds_i64_align_4: -; SI: DS_WRITE2_B32 -; SI: S_ENDPGM +; SI: ds_write2_b32 +; SI: s_endpgm define void @store_lds_i64_align_4(i64 addrspace(3)* %out, i64 %val) #0 { store i64 %val, i64 addrspace(3)* %out, align 4 ret void } ; SI-LABEL: {{^}}store_lds_i64_align_4_with_offset -; SI: DS_WRITE2_B32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:8 offset1:9 -; SI: S_ENDPGM +; SI: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:8 offset1:9 +; SI: s_endpgm define void @store_lds_i64_align_4_with_offset(i64 addrspace(3)* %out) #0 { %ptr = getelementptr i64 addrspace(3)* %out, i32 4 store i64 0, i64 addrspace(3)* %ptr, align 4 @@ -90,8 +90,8 @@ define void @store_lds_i64_align_4_with_offset(i64 addrspace(3)* %out) #0 { ; SI-LABEL: {{^}}store_lds_i64_align_4_with_split_offset: ; The tests for the case where the lo offset is 8-bits, but the hi offset is 9-bits -; SI: DS_WRITE2_B32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:0 offset1:1 -; SI: S_ENDPGM +; SI: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:0 offset1:1 +; SI: s_endpgm define void @store_lds_i64_align_4_with_split_offset(i64 addrspace(3)* %out) #0 { %ptr = bitcast i64 addrspace(3)* %out to i32 addrspace(3)* %ptr255 = getelementptr i32 addrspace(3)* %ptr, i32 255 diff --git a/test/CodeGen/R600/unhandled-loop-condition-assertion.ll b/test/CodeGen/R600/unhandled-loop-condition-assertion.ll index ee0a83084af..ff01a1e0002 100644 --- a/test/CodeGen/R600/unhandled-loop-condition-assertion.ll +++ b/test/CodeGen/R600/unhandled-loop-condition-assertion.ll @@ -41,7 +41,7 @@ for.end: ; preds = %for.body, %entry ; COMMON-LABEL: {{^}}branch_false: ; SI: .text -; SI-NEXT: S_ENDPGM +; SI-NEXT: s_endpgm define void @branch_false(i8 addrspace(1)* nocapture %main, i32 %main_stride) #0 { entry: br i1 false, label %for.end, label %for.body.lr.ph @@ -77,7 +77,7 @@ for.end: ; preds = %for.body, %entry ; COMMON-LABEL: {{^}}branch_undef: ; SI: .text -; SI-NEXT: S_ENDPGM +; SI-NEXT: s_endpgm define void @branch_undef(i8 addrspace(1)* nocapture %main, i32 %main_stride) #0 { entry: br i1 undef, label %for.end, label %for.body.lr.ph diff --git a/test/CodeGen/R600/urecip.ll b/test/CodeGen/R600/urecip.ll index e808e3d2cf1..4d953b57c52 100644 --- a/test/CodeGen/R600/urecip.ll +++ b/test/CodeGen/R600/urecip.ll @@ -1,6 +1,6 @@ ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s -;CHECK: V_RCP_IFLAG_F32_e32 +;CHECK: v_rcp_iflag_f32_e32 define void @test(i32 %p, i32 %q) { %i = udiv i32 %p, %q diff --git a/test/CodeGen/R600/urem.ll b/test/CodeGen/R600/urem.ll index 449e19f3c72..914f5d088e7 100644 --- a/test/CodeGen/R600/urem.ll +++ b/test/CodeGen/R600/urem.ll @@ -8,7 +8,7 @@ ;EG-CHECK: {{^}}test2: ;EG-CHECK: CF_END ;SI-CHECK: {{^}}test2: -;SI-CHECK: S_ENDPGM +;SI-CHECK: s_endpgm define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -22,7 +22,7 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { ;EG-CHECK: {{^}}test4: ;EG-CHECK: CF_END ;SI-CHECK: {{^}}test4: -;SI-CHECK: S_ENDPGM +;SI-CHECK: s_endpgm define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 diff --git a/test/CodeGen/R600/use-sgpr-multiple-times.ll b/test/CodeGen/R600/use-sgpr-multiple-times.ll index 0744295006b..2e67fbf5e2a 100644 --- a/test/CodeGen/R600/use-sgpr-multiple-times.ll +++ b/test/CodeGen/R600/use-sgpr-multiple-times.ll @@ -6,9 +6,9 @@ declare i32 @llvm.AMDGPU.imad24(i32, i32, i32) #1 ; SI-LABEL: {{^}}test_sgpr_use_twice_binop: -; SI: S_LOAD_DWORD [[SGPR:s[0-9]+]], -; SI: V_ADD_F32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]] -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI: s_load_dword [[SGPR:s[0-9]+]], +; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]] +; SI: buffer_store_dword [[RESULT]] define void @test_sgpr_use_twice_binop(float addrspace(1)* %out, float %a) #0 { %dbl = fadd float %a, %a store float %dbl, float addrspace(1)* %out, align 4 @@ -16,9 +16,9 @@ define void @test_sgpr_use_twice_binop(float addrspace(1)* %out, float %a) #0 { } ; SI-LABEL: {{^}}test_sgpr_use_three_ternary_op: -; SI: S_LOAD_DWORD [[SGPR:s[0-9]+]], -; SI: V_FMA_F32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]] -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI: s_load_dword [[SGPR:s[0-9]+]], +; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]] +; SI: buffer_store_dword [[RESULT]] define void @test_sgpr_use_three_ternary_op(float addrspace(1)* %out, float %a) #0 { %fma = call float @llvm.fma.f32(float %a, float %a, float %a) #1 store float %fma, float addrspace(1)* %out, align 4 @@ -26,11 +26,11 @@ define void @test_sgpr_use_three_ternary_op(float addrspace(1)* %out, float %a) } ; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_b: -; SI: S_LOAD_DWORD [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI: S_LOAD_DWORD [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI: V_MOV_B32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]] -; SI: V_FMA_F32 [[RESULT:v[0-9]+]], [[SGPR0]], [[SGPR0]], [[VGPR1]] -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]] +; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[SGPR0]], [[VGPR1]] +; SI: buffer_store_dword [[RESULT]] define void @test_sgpr_use_twice_ternary_op_a_a_b(float addrspace(1)* %out, float %a, float %b) #0 { %fma = call float @llvm.fma.f32(float %a, float %a, float %b) #1 store float %fma, float addrspace(1)* %out, align 4 @@ -38,11 +38,11 @@ define void @test_sgpr_use_twice_ternary_op_a_a_b(float addrspace(1)* %out, floa } ; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_b_a: -; SI: S_LOAD_DWORD [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI: S_LOAD_DWORD [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI: V_MOV_B32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]] -; SI: V_FMA_F32 [[RESULT:v[0-9]+]], [[SGPR0]], [[VGPR1]], [[SGPR0]] -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]] +; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[VGPR1]], [[SGPR0]] +; SI: buffer_store_dword [[RESULT]] define void @test_sgpr_use_twice_ternary_op_a_b_a(float addrspace(1)* %out, float %a, float %b) #0 { %fma = call float @llvm.fma.f32(float %a, float %b, float %a) #1 store float %fma, float addrspace(1)* %out, align 4 @@ -50,11 +50,11 @@ define void @test_sgpr_use_twice_ternary_op_a_b_a(float addrspace(1)* %out, floa } ; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_b_a_a: -; SI: S_LOAD_DWORD [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI: S_LOAD_DWORD [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI: V_MOV_B32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]] -; SI: V_FMA_F32 [[RESULT:v[0-9]+]], [[VGPR1]], [[SGPR0]], [[SGPR0]] -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]] +; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], [[SGPR0]], [[SGPR0]] +; SI: buffer_store_dword [[RESULT]] define void @test_sgpr_use_twice_ternary_op_b_a_a(float addrspace(1)* %out, float %a, float %b) #0 { %fma = call float @llvm.fma.f32(float %b, float %a, float %a) #1 store float %fma, float addrspace(1)* %out, align 4 @@ -62,9 +62,9 @@ define void @test_sgpr_use_twice_ternary_op_b_a_a(float addrspace(1)* %out, floa } ; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_imm: -; SI: S_LOAD_DWORD [[SGPR:s[0-9]+]] -; SI: V_FMA_F32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], 2.0 -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI: s_load_dword [[SGPR:s[0-9]+]] +; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], 2.0 +; SI: buffer_store_dword [[RESULT]] define void @test_sgpr_use_twice_ternary_op_a_a_imm(float addrspace(1)* %out, float %a) #0 { %fma = call float @llvm.fma.f32(float %a, float %a, float 2.0) #1 store float %fma, float addrspace(1)* %out, align 4 @@ -72,9 +72,9 @@ define void @test_sgpr_use_twice_ternary_op_a_a_imm(float addrspace(1)* %out, fl } ; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_imm_a: -; SI: S_LOAD_DWORD [[SGPR:s[0-9]+]] -; SI: V_FMA_F32 [[RESULT:v[0-9]+]], [[SGPR]], 2.0, [[SGPR]] -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI: s_load_dword [[SGPR:s[0-9]+]] +; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], 2.0, [[SGPR]] +; SI: buffer_store_dword [[RESULT]] define void @test_sgpr_use_twice_ternary_op_a_imm_a(float addrspace(1)* %out, float %a) #0 { %fma = call float @llvm.fma.f32(float %a, float 2.0, float %a) #1 store float %fma, float addrspace(1)* %out, align 4 @@ -83,9 +83,9 @@ define void @test_sgpr_use_twice_ternary_op_a_imm_a(float addrspace(1)* %out, fl ; Don't use fma since fma c, x, y is canonicalized to fma x, c, y ; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_imm_a_a: -; SI: S_LOAD_DWORD [[SGPR:s[0-9]+]] -; SI: V_MAD_I32_I24 [[RESULT:v[0-9]+]], 2, [[SGPR]], [[SGPR]] -; SI: BUFFER_STORE_DWORD [[RESULT]] +; SI: s_load_dword [[SGPR:s[0-9]+]] +; SI: v_mad_i32_i24 [[RESULT:v[0-9]+]], 2, [[SGPR]], [[SGPR]] +; SI: buffer_store_dword [[RESULT]] define void @test_sgpr_use_twice_ternary_op_imm_a_a(i32 addrspace(1)* %out, i32 %a) #0 { %fma = call i32 @llvm.AMDGPU.imad24(i32 2, i32 %a, i32 %a) #1 store i32 %fma, i32 addrspace(1)* %out, align 4 diff --git a/test/CodeGen/R600/usubo.ll b/test/CodeGen/R600/usubo.ll index 10e79d7ab54..4d4060006bd 100644 --- a/test/CodeGen/R600/usubo.ll +++ b/test/CodeGen/R600/usubo.ll @@ -16,7 +16,7 @@ define void @usubo_i64_zext(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { } ; FUNC-LABEL: {{^}}s_usubo_i32: -; SI: S_SUB_I32 +; SI: s_sub_i32 define void @s_usubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) nounwind { %usub = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b) nounwind %val = extractvalue { i32, i1 } %usub, 0 @@ -27,7 +27,7 @@ define void @s_usubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 } ; FUNC-LABEL: {{^}}v_usubo_i32: -; SI: V_SUBREV_I32_e32 +; SI: v_subrev_i32_e32 define void @v_usubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind { %a = load i32 addrspace(1)* %aptr, align 4 %b = load i32 addrspace(1)* %bptr, align 4 @@ -40,8 +40,8 @@ define void @v_usubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 } ; FUNC-LABEL: {{^}}s_usubo_i64: -; SI: S_SUB_U32 -; SI: S_SUBB_U32 +; SI: s_sub_u32 +; SI: s_subb_u32 define void @s_usubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a, i64 %b) nounwind { %usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) nounwind %val = extractvalue { i64, i1 } %usub, 0 @@ -52,8 +52,8 @@ define void @s_usubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 } ; FUNC-LABEL: {{^}}v_usubo_i64: -; SI: V_SUB_I32 -; SI: V_SUBB_U32 +; SI: v_sub_i32 +; SI: v_subb_u32 define void @v_usubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind { %a = load i64 addrspace(1)* %aptr, align 4 %b = load i64 addrspace(1)* %bptr, align 4 diff --git a/test/CodeGen/R600/v_cndmask.ll b/test/CodeGen/R600/v_cndmask.ll index b9c25105a83..a24dcc79b9c 100644 --- a/test/CodeGen/R600/v_cndmask.ll +++ b/test/CodeGen/R600/v_cndmask.ll @@ -3,10 +3,10 @@ declare i32 @llvm.r600.read.tidig.x() #1 ; SI-LABEL: {{^}}v_cnd_nan_nosgpr: -; SI: V_CNDMASK_B32_e64 v{{[0-9]}}, v{{[0-9]}}, -1, s{{\[[0-9]+:[0-9]+\]}} +; SI: v_cndmask_b32_e64 v{{[0-9]}}, v{{[0-9]}}, -1, s{{\[[0-9]+:[0-9]+\]}} ; SI-DAG: v{{[0-9]}} ; All nan values are converted to 0xffffffff -; SI: S_ENDPGM +; SI: s_endpgm define void @v_cnd_nan_nosgpr(float addrspace(1)* %out, i32 %c, float addrspace(1)* %fptr) #0 { %idx = call i32 @llvm.r600.read.tidig.x() #1 %f.gep = getelementptr float addrspace(1)* %fptr, i32 %idx @@ -23,10 +23,10 @@ define void @v_cnd_nan_nosgpr(float addrspace(1)* %out, i32 %c, float addrspace( ; never be moved. ; SI-LABEL: {{^}}v_cnd_nan: -; SI: V_CNDMASK_B32_e64 v{{[0-9]}}, v{{[0-9]}}, -1, s{{\[[0-9]+:[0-9]+\]}} +; SI: v_cndmask_b32_e64 v{{[0-9]}}, v{{[0-9]}}, -1, s{{\[[0-9]+:[0-9]+\]}} ; SI-DAG: v{{[0-9]}} ; All nan values are converted to 0xffffffff -; SI: S_ENDPGM +; SI: s_endpgm define void @v_cnd_nan(float addrspace(1)* %out, i32 %c, float %f) #0 { %setcc = icmp ne i32 %c, 0 %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f diff --git a/test/CodeGen/R600/valu-i1.ll b/test/CodeGen/R600/valu-i1.ll index 5d5e3ff63a4..2c209fcb857 100644 --- a/test/CodeGen/R600/valu-i1.ll +++ b/test/CodeGen/R600/valu-i1.ll @@ -2,8 +2,8 @@ ; Make sure the i1 values created by the cfg structurizer pass are ; moved using VALU instructions -; SI-NOT: S_MOV_B64 s[{{[0-9]:[0-9]}}], -1 -; SI: V_MOV_B32_e32 v{{[0-9]}}, -1 +; SI-NOT: s_mov_b64 s[{{[0-9]:[0-9]}}], -1 +; SI: v_mov_b32_e32 v{{[0-9]}}, -1 define void @test_if(i32 %a, i32 %b, i32 addrspace(1)* %src, i32 addrspace(1)* %dst) { entry: switch i32 %a, label %default [ diff --git a/test/CodeGen/R600/vop-shrink.ll b/test/CodeGen/R600/vop-shrink.ll index 034d3f114ee..e7f0288c87e 100644 --- a/test/CodeGen/R600/vop-shrink.ll +++ b/test/CodeGen/R600/vop-shrink.ll @@ -2,8 +2,8 @@ ; Test that we correctly commute a sub instruction ; FUNC-LABEL: {{^}}sub_rev: -; SI-NOT: V_SUB_I32_e32 v{{[0-9]+}}, s -; SI: V_SUBREV_I32_e32 v{{[0-9]+}}, s +; SI-NOT: v_sub_i32_e32 v{{[0-9]+}}, s +; SI: v_subrev_i32_e32 v{{[0-9]+}}, s ; ModuleID = 'vop-shrink.ll' @@ -33,7 +33,7 @@ endif: ; preds = %else, %if ; 32-bit op when we shrink it. ; FUNC-LABEL: {{^}}add_fold: -; SI: V_ADD_F32_e32 v{{[0-9]+}}, 0x44800000 +; SI: v_add_f32_e32 v{{[0-9]+}}, 0x44800000 define void @add_fold(float addrspace(1)* %out) { entry: %tmp = call i32 @llvm.r600.read.tidig.x() diff --git a/test/CodeGen/R600/vselect.ll b/test/CodeGen/R600/vselect.ll index a1f4ae1261b..e84b8f7da71 100644 --- a/test/CodeGen/R600/vselect.ll +++ b/test/CodeGen/R600/vselect.ll @@ -6,8 +6,8 @@ ;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;SI-CHECK: {{^}}test_select_v2i32: -;SI-CHECK: V_CNDMASK_B32_e64 -;SI-CHECK: V_CNDMASK_B32_e64 +;SI-CHECK: v_cndmask_b32_e64 +;SI-CHECK: v_cndmask_b32_e64 define void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) { entry: @@ -24,8 +24,8 @@ entry: ;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;SI-CHECK: {{^}}test_select_v2f32: -;SI-CHECK: V_CNDMASK_B32_e64 -;SI-CHECK: V_CNDMASK_B32_e64 +;SI-CHECK: v_cndmask_b32_e64 +;SI-CHECK: v_cndmask_b32_e64 define void @test_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in0, <2 x float> addrspace(1)* %in1) { entry: @@ -44,10 +44,10 @@ entry: ;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;SI-CHECK: {{^}}test_select_v4i32: -;SI-CHECK: V_CNDMASK_B32_e64 -;SI-CHECK: V_CNDMASK_B32_e64 -;SI-CHECK: V_CNDMASK_B32_e64 -;SI-CHECK: V_CNDMASK_B32_e64 +;SI-CHECK: v_cndmask_b32_e64 +;SI-CHECK: v_cndmask_b32_e64 +;SI-CHECK: v_cndmask_b32_e64 +;SI-CHECK: v_cndmask_b32_e64 define void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) { entry: diff --git a/test/CodeGen/R600/wait.ll b/test/CodeGen/R600/wait.ll index 7703b84ec28..735eabdccdd 100644 --- a/test/CodeGen/R600/wait.ll +++ b/test/CodeGen/R600/wait.ll @@ -1,11 +1,11 @@ ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace %s ; CHECK-LABEL: {{^}}main: -; CHECK: S_LOAD_DWORDX4 -; CHECK: S_LOAD_DWORDX4 -; CHECK: S_WAITCNT lgkmcnt(0){{$}} -; CHECK: S_WAITCNT vmcnt(0){{$}} -; CHECK: S_WAITCNT expcnt(0) lgkmcnt(0){{$}} +; CHECK: s_load_dwordx4 +; CHECK: s_load_dwordx4 +; CHECK: s_waitcnt lgkmcnt(0){{$}} +; CHECK: s_waitcnt vmcnt(0){{$}} +; CHECK: s_waitcnt expcnt(0) lgkmcnt(0){{$}} define void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, <16 x i8> addrspace(2)* inreg %arg3, <16 x i8> addrspace(2)* inreg %arg4, i32 inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(2)* inreg %constptr) #0 { main_body: %tmp = getelementptr <16 x i8> addrspace(2)* %arg3, i32 0 diff --git a/test/CodeGen/R600/work-item-intrinsics.ll b/test/CodeGen/R600/work-item-intrinsics.ll index cbefe2577fd..47f65f5e4e5 100644 --- a/test/CodeGen/R600/work-item-intrinsics.ll +++ b/test/CodeGen/R600/work-item-intrinsics.ll @@ -6,9 +6,9 @@ ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV [[VAL]], KC0[0].X -; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0 -; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_DWORD [[VVAL]] +; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0 +; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[VVAL]] define void @ngroups_x (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.ngroups.x() #0 @@ -20,9 +20,9 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV [[VAL]], KC0[0].Y -; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x1 -; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_DWORD [[VVAL]] +; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1 +; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[VVAL]] define void @ngroups_y (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.ngroups.y() #0 @@ -34,9 +34,9 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV [[VAL]], KC0[0].Z -; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x2 -; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_DWORD [[VVAL]] +; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2 +; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[VVAL]] define void @ngroups_z (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.ngroups.z() #0 @@ -48,9 +48,9 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV [[VAL]], KC0[0].W -; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x3 -; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_DWORD [[VVAL]] +; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x3 +; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[VVAL]] define void @global_size_x (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.global.size.x() #0 @@ -62,9 +62,9 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV [[VAL]], KC0[1].X -; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x4 -; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_DWORD [[VVAL]] +; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4 +; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[VVAL]] define void @global_size_y (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.global.size.y() #0 @@ -76,9 +76,9 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV [[VAL]], KC0[1].Y -; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x5 -; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_DWORD [[VVAL]] +; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x5 +; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[VVAL]] define void @global_size_z (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.global.size.z() #0 @@ -90,9 +90,9 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV [[VAL]], KC0[1].Z -; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x6 -; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_DWORD [[VVAL]] +; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x6 +; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[VVAL]] define void @local_size_x (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.local.size.x() #0 @@ -104,9 +104,9 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV [[VAL]], KC0[1].W -; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x7 -; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_DWORD [[VVAL]] +; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x7 +; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[VVAL]] define void @local_size_y (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.local.size.y() #0 @@ -118,9 +118,9 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV [[VAL]], KC0[2].X -; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x8 -; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_DWORD [[VVAL]] +; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8 +; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[VVAL]] define void @local_size_z (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.local.size.z() #0 @@ -132,9 +132,9 @@ entry: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; EG: MOV [[VAL]], KC0[2].Z -; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0xb -; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; SI: BUFFER_STORE_DWORD [[VVAL]] +; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb +; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[VVAL]] define void @get_work_dim (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.AMDGPU.read.workdim() #0 @@ -147,8 +147,8 @@ entry: ; kernel arguments, but this may change in the future. ; FUNC-LABEL: {{^}}tgid_x: -; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], s4 -; SI: BUFFER_STORE_DWORD [[VVAL]] +; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], s4 +; SI: buffer_store_dword [[VVAL]] define void @tgid_x (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.tgid.x() #0 @@ -157,8 +157,8 @@ entry: } ; FUNC-LABEL: {{^}}tgid_y: -; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], s5 -; SI: BUFFER_STORE_DWORD [[VVAL]] +; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], s5 +; SI: buffer_store_dword [[VVAL]] define void @tgid_y (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.tgid.y() #0 @@ -167,8 +167,8 @@ entry: } ; FUNC-LABEL: {{^}}tgid_z: -; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], s6 -; SI: BUFFER_STORE_DWORD [[VVAL]] +; SI: v_mov_b32_e32 [[VVAL:v[0-9]+]], s6 +; SI: buffer_store_dword [[VVAL]] define void @tgid_z (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.tgid.z() #0 @@ -177,7 +177,7 @@ entry: } ; FUNC-LABEL: {{^}}tidig_x: -; SI: BUFFER_STORE_DWORD v0 +; SI: buffer_store_dword v0 define void @tidig_x (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.tidig.x() #0 @@ -186,7 +186,7 @@ entry: } ; FUNC-LABEL: {{^}}tidig_y: -; SI: BUFFER_STORE_DWORD v1 +; SI: buffer_store_dword v1 define void @tidig_y (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.tidig.y() #0 @@ -195,7 +195,7 @@ entry: } ; FUNC-LABEL: {{^}}tidig_z: -; SI: BUFFER_STORE_DWORD v2 +; SI: buffer_store_dword v2 define void @tidig_z (i32 addrspace(1)* %out) { entry: %0 = call i32 @llvm.r600.read.tidig.z() #0 diff --git a/test/CodeGen/R600/xor.ll b/test/CodeGen/R600/xor.ll index 00e57f68ec7..fa54e3816d5 100644 --- a/test/CodeGen/R600/xor.ll +++ b/test/CodeGen/R600/xor.ll @@ -6,8 +6,8 @@ ;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;SI-CHECK: {{^}}xor_v2i32: -;SI-CHECK: V_XOR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_XOR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_xor_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_xor_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @xor_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) { @@ -25,10 +25,10 @@ define void @xor_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in ;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;SI-CHECK: {{^}}xor_v4i32: -;SI-CHECK: V_XOR_B32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_XOR_B32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_XOR_B32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_XOR_B32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_xor_b32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_xor_b32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_xor_b32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_xor_b32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} define void @xor_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) { %a = load <4 x i32> addrspace(1) * %in0 @@ -42,7 +42,7 @@ define void @xor_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in ;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}} ;SI-CHECK: {{^}}xor_i1: -;SI-CHECK: V_XOR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +;SI-CHECK: v_xor_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} define void @xor_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) { %a = load float addrspace(1) * %in0 @@ -56,7 +56,7 @@ define void @xor_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float ad } ; SI-CHECK-LABEL: {{^}}vector_xor_i32: -; SI-CHECK: V_XOR_B32_e32 +; SI-CHECK: v_xor_b32_e32 define void @vector_xor_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) { %a = load i32 addrspace(1)* %in0 %b = load i32 addrspace(1)* %in1 @@ -66,7 +66,7 @@ define void @vector_xor_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 } ; SI-CHECK-LABEL: {{^}}scalar_xor_i32: -; SI-CHECK: S_XOR_B32 +; SI-CHECK: s_xor_b32 define void @scalar_xor_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { %result = xor i32 %a, %b store i32 %result, i32 addrspace(1)* %out @@ -74,7 +74,7 @@ define void @scalar_xor_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { } ; SI-CHECK-LABEL: {{^}}scalar_not_i32: -; SI-CHECK: S_NOT_B32 +; SI-CHECK: s_not_b32 define void @scalar_not_i32(i32 addrspace(1)* %out, i32 %a) { %result = xor i32 %a, -1 store i32 %result, i32 addrspace(1)* %out @@ -82,7 +82,7 @@ define void @scalar_not_i32(i32 addrspace(1)* %out, i32 %a) { } ; SI-CHECK-LABEL: {{^}}vector_not_i32: -; SI-CHECK: V_NOT_B32 +; SI-CHECK: v_not_b32 define void @vector_not_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) { %a = load i32 addrspace(1)* %in0 %b = load i32 addrspace(1)* %in1 @@ -92,9 +92,9 @@ define void @vector_not_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 } ; SI-CHECK-LABEL: {{^}}vector_xor_i64: -; SI-CHECK: V_XOR_B32_e32 -; SI-CHECK: V_XOR_B32_e32 -; SI-CHECK: S_ENDPGM +; SI-CHECK: v_xor_b32_e32 +; SI-CHECK: v_xor_b32_e32 +; SI-CHECK: s_endpgm define void @vector_xor_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i64 addrspace(1)* %in1) { %a = load i64 addrspace(1)* %in0 %b = load i64 addrspace(1)* %in1 @@ -104,8 +104,8 @@ define void @vector_xor_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i64 } ; SI-CHECK-LABEL: {{^}}scalar_xor_i64: -; SI-CHECK: S_XOR_B64 -; SI-CHECK: S_ENDPGM +; SI-CHECK: s_xor_b64 +; SI-CHECK: s_endpgm define void @scalar_xor_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { %result = xor i64 %a, %b store i64 %result, i64 addrspace(1)* %out @@ -113,7 +113,7 @@ define void @scalar_xor_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { } ; SI-CHECK-LABEL: {{^}}scalar_not_i64: -; SI-CHECK: S_NOT_B64 +; SI-CHECK: s_not_b64 define void @scalar_not_i64(i64 addrspace(1)* %out, i64 %a) { %result = xor i64 %a, -1 store i64 %result, i64 addrspace(1)* %out @@ -121,8 +121,8 @@ define void @scalar_not_i64(i64 addrspace(1)* %out, i64 %a) { } ; SI-CHECK-LABEL: {{^}}vector_not_i64: -; SI-CHECK: V_NOT_B32 -; SI-CHECK: V_NOT_B32 +; SI-CHECK: v_not_b32 +; SI-CHECK: v_not_b32 define void @vector_not_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i64 addrspace(1)* %in1) { %a = load i64 addrspace(1)* %in0 %b = load i64 addrspace(1)* %in1 @@ -136,7 +136,7 @@ define void @vector_not_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i64 ; use an SALU instruction for this. ; SI-CHECK-LABEL: {{^}}xor_cf: -; SI-CHECK: S_XOR_B64 +; SI-CHECK: s_xor_b64 define void @xor_cf(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b) { entry: %0 = icmp eq i64 %a, 0 diff --git a/test/CodeGen/R600/zero_extend.ll b/test/CodeGen/R600/zero_extend.ll index 0e527d6d1a2..0fe1f15e51f 100644 --- a/test/CodeGen/R600/zero_extend.ll +++ b/test/CodeGen/R600/zero_extend.ll @@ -6,9 +6,9 @@ ; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW ; SI-CHECK: {{^}}test: -; SI-CHECK: S_MOV_B32 [[ZERO:s[0-9]]], 0{{$}} -; SI-CHECK: V_MOV_B32_e32 v[[V_ZERO:[0-9]]], [[ZERO]] -; SI-CHECK: BUFFER_STORE_DWORDX2 v[0:[[V_ZERO]]{{\]}} +; SI-CHECK: s_mov_b32 [[ZERO:s[0-9]]], 0{{$}} +; SI-CHECK: v_mov_b32_e32 v[[V_ZERO:[0-9]]], [[ZERO]] +; SI-CHECK: buffer_store_dwordx2 v[0:[[V_ZERO]]{{\]}} define void @test(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { entry: %0 = mul i32 %a, %b @@ -19,7 +19,7 @@ entry: } ; SI-CHECK-LABEL: {{^}}testi1toi32: -; SI-CHECK: V_CNDMASK_B32 +; SI-CHECK: v_cndmask_b32 define void @testi1toi32(i32 addrspace(1)* %out, i32 %a, i32 %b) { entry: %0 = icmp eq i32 %a, %b @@ -29,9 +29,9 @@ entry: } ; SI-CHECK-LABEL: {{^}}zext_i1_to_i64: -; SI-CHECK: V_CMP_EQ_I32 -; SI-CHECK: V_CNDMASK_B32 -; SI-CHECK: S_MOV_B32 s{{[0-9]+}}, 0 +; SI-CHECK: v_cmp_eq_i32 +; SI-CHECK: v_cndmask_b32 +; SI-CHECK: s_mov_b32 s{{[0-9]+}}, 0 define void @zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %cmp = icmp eq i32 %a, %b %ext = zext i1 %cmp to i64