From: Zhenyu Wang Date: Mon, 23 Aug 2010 06:37:52 +0000 (+0800) Subject: agp/intel: fix physical address mask bits for sandybridge X-Git-Tag: firefly_0821_release~9833^2~409^2~19 X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=8dfc2b14ebf538f28a05565f34913ecffedf5024;p=firefly-linux-kernel-4.4.55.git agp/intel: fix physical address mask bits for sandybridge It should shift bit 39-32 into pte's bit 11-4. Reported-by:Takashi Iwai Signed-off-by: Zhenyu Wang Cc: stable@kernel.org Signed-off-by: Chris Wilson --- diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index ce536e68b6c6..7f35854d33a3 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -1333,8 +1333,8 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr, int type) { - /* Shift high bits down */ - addr |= (addr >> 28) & 0xff; + /* gen6 has bit11-4 for physical addr bit39-32 */ + addr |= (addr >> 28) & 0xff0; /* Type checking must be done elsewhere */ return addr | bridge->driver->masks[type].mask;