From: chenxing <chenxing@rock-chips.com>
Date: Thu, 20 Jun 2013 10:03:11 +0000 (+0800)
Subject: rk3188: fix uart0 init 49.5MHz error, set uart0 = 48MHz
X-Git-Tag: firefly_0821_release~6965^2~45
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=88db180a61801925bbee64be133c053a03a0906d;p=firefly-linux-kernel-4.4.55.git

rk3188: fix uart0 init 49.5MHz error, set uart0 = 48MHz
---

diff --git a/arch/arm/mach-rk3188/clock_data.c b/arch/arm/mach-rk3188/clock_data.c
index c04177a7b4b9..757098415340 100755
--- a/arch/arm/mach-rk3188/clock_data.c
+++ b/arch/arm/mach-rk3188/clock_data.c
@@ -3553,7 +3553,7 @@ static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long
 	clk_set_parent_nolock(&aclk_gpu, &general_pll_clk);
 	clk_set_rate_nolock(&aclk_gpu, 200 * MHZ);
 	
-	clk_set_rate_nolock(&clk_uart0, 49500000);
+	clk_set_rate_nolock(&clk_uart0, 48000000);
 	clk_set_rate_nolock(&clk_sdmmc, 24750000);
 	clk_set_rate_nolock(&clk_sdio, 24750000);
 }