From: Jim Laskey Date: Wed, 28 Feb 2007 20:43:58 +0000 (+0000) Subject: Chain is on second operand. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=8782d481a3c720304540254a7b71d25bbe7cbf49;p=oota-llvm.git Chain is on second operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34759 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index efff9f48280..c32311373ec 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -676,16 +676,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { else Result = DAG.getConstant(0, TLI.getPointerTy()); break; - case ISD::EHSELECTION: case ISD::EXCEPTIONADDR: { Tmp1 = LegalizeOp(Node->getOperand(0)); MVT::ValueType VT = Node->getValueType(0); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: { - unsigned Reg = Node->getOpcode() == ISD::EXCEPTIONADDR ? - TLI.getExceptionAddressRegister() : - TLI.getExceptionSelectorRegister(); + unsigned Reg = TLI.getExceptionAddressRegister(); Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo); } break; @@ -700,6 +697,28 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } } break; + case ISD::EHSELECTION: { + Tmp1 = LegalizeOp(Node->getOperand(0)); + Tmp2 = LegalizeOp(Node->getOperand(1)); + MVT::ValueType VT = Node->getValueType(0); + switch (TLI.getOperationAction(Node->getOpcode(), VT)) { + default: assert(0 && "This action is not supported yet!"); + case TargetLowering::Expand: { + unsigned Reg = TLI.getExceptionSelectorRegister(); + Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo); + } + break; + case TargetLowering::Custom: + Result = TLI.LowerOperation(Op, DAG); + if (Result.Val) break; + // Fall Thru + case TargetLowering::Legal: + Result = DAG.getNode(ISD::MERGE_VALUES, VT, DAG.getConstant(0, VT), Tmp2). + getValue(Op.ResNo); + break; + } + } + break; case ISD::AssertSext: case ISD::AssertZext: Tmp1 = LegalizeOp(Node->getOperand(0));