From: Chris Lattner Date: Wed, 30 Oct 2002 01:49:01 +0000 (+0000) Subject: Make sure to set the destination register correctly X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=8548ee75eb3eb44ed396b137b5962cbdc28e97b8;p=oota-llvm.git Make sure to set the destination register correctly git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4444 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index b13946e08fe..d0d80e3226c 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -85,7 +85,6 @@ namespace { return Reg; } - }; } @@ -98,22 +97,22 @@ void ISel::copyConstantToRegister(Constant *C, unsigned R) { switch (C->getType()->getPrimitiveID()) { case Type::SByteTyID: - BuildMI(BB, X86::MOVir8, R).addSImm(cast(C)->getValue()); + BuildMI(BB, X86::MOVir8, 1, R).addSImm(cast(C)->getValue()); break; case Type::UByteTyID: - BuildMI(BB, X86::MOVir8, R).addZImm(cast(C)->getValue()); + BuildMI(BB, X86::MOVir8, 1, R).addZImm(cast(C)->getValue()); break; case Type::ShortTyID: - BuildMI(BB, X86::MOVir16, R).addSImm(cast(C)->getValue()); + BuildMI(BB, X86::MOVir16, 1, R).addSImm(cast(C)->getValue()); break; case Type::UShortTyID: - BuildMI(BB, X86::MOVir16, R).addZImm(cast(C)->getValue()); + BuildMI(BB, X86::MOVir16, 1, R).addZImm(cast(C)->getValue()); break; case Type::IntTyID: - BuildMI(BB, X86::MOVir32, R).addSImm(cast(C)->getValue()); + BuildMI(BB, X86::MOVir32, 1, R).addSImm(cast(C)->getValue()); break; case Type::UIntTyID: - BuildMI(BB, X86::MOVir32, R).addZImm(cast(C)->getValue()); + BuildMI(BB, X86::MOVir32, 1, R).addZImm(cast(C)->getValue()); break; default: assert(0 && "Type not handled yet!"); } @@ -150,13 +149,13 @@ void ISel::visitAdd(BinaryOperator &B) { switch (B.getType()->getPrimitiveSize()) { case 1: // UByte, SByte - BuildMI(BB, X86::ADDrr8, DestReg).addReg(Op0r).addReg(Op1r); + BuildMI(BB, X86::ADDrr8, 2, DestReg).addReg(Op0r).addReg(Op1r); break; case 2: // UShort, Short - BuildMI(BB, X86::ADDrr16, DestReg).addReg(Op0r).addReg(Op1r); + BuildMI(BB, X86::ADDrr16, 2, DestReg).addReg(Op0r).addReg(Op1r); break; case 4: // UInt, Int - BuildMI(BB, X86::ADDrr32, DestReg).addReg(Op0r).addReg(Op1r); + BuildMI(BB, X86::ADDrr32, 2, DestReg).addReg(Op0r).addReg(Op1r); break; case 8: // ULong, Long diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp index b13946e08fe..d0d80e3226c 100644 --- a/lib/Target/X86/X86ISelSimple.cpp +++ b/lib/Target/X86/X86ISelSimple.cpp @@ -85,7 +85,6 @@ namespace { return Reg; } - }; } @@ -98,22 +97,22 @@ void ISel::copyConstantToRegister(Constant *C, unsigned R) { switch (C->getType()->getPrimitiveID()) { case Type::SByteTyID: - BuildMI(BB, X86::MOVir8, R).addSImm(cast(C)->getValue()); + BuildMI(BB, X86::MOVir8, 1, R).addSImm(cast(C)->getValue()); break; case Type::UByteTyID: - BuildMI(BB, X86::MOVir8, R).addZImm(cast(C)->getValue()); + BuildMI(BB, X86::MOVir8, 1, R).addZImm(cast(C)->getValue()); break; case Type::ShortTyID: - BuildMI(BB, X86::MOVir16, R).addSImm(cast(C)->getValue()); + BuildMI(BB, X86::MOVir16, 1, R).addSImm(cast(C)->getValue()); break; case Type::UShortTyID: - BuildMI(BB, X86::MOVir16, R).addZImm(cast(C)->getValue()); + BuildMI(BB, X86::MOVir16, 1, R).addZImm(cast(C)->getValue()); break; case Type::IntTyID: - BuildMI(BB, X86::MOVir32, R).addSImm(cast(C)->getValue()); + BuildMI(BB, X86::MOVir32, 1, R).addSImm(cast(C)->getValue()); break; case Type::UIntTyID: - BuildMI(BB, X86::MOVir32, R).addZImm(cast(C)->getValue()); + BuildMI(BB, X86::MOVir32, 1, R).addZImm(cast(C)->getValue()); break; default: assert(0 && "Type not handled yet!"); } @@ -150,13 +149,13 @@ void ISel::visitAdd(BinaryOperator &B) { switch (B.getType()->getPrimitiveSize()) { case 1: // UByte, SByte - BuildMI(BB, X86::ADDrr8, DestReg).addReg(Op0r).addReg(Op1r); + BuildMI(BB, X86::ADDrr8, 2, DestReg).addReg(Op0r).addReg(Op1r); break; case 2: // UShort, Short - BuildMI(BB, X86::ADDrr16, DestReg).addReg(Op0r).addReg(Op1r); + BuildMI(BB, X86::ADDrr16, 2, DestReg).addReg(Op0r).addReg(Op1r); break; case 4: // UInt, Int - BuildMI(BB, X86::ADDrr32, DestReg).addReg(Op0r).addReg(Op1r); + BuildMI(BB, X86::ADDrr32, 2, DestReg).addReg(Op0r).addReg(Op1r); break; case 8: // ULong, Long