From: Jim Grosbach <grosbach@apple.com>
Date: Thu, 21 Jul 2011 23:03:59 +0000 (+0000)
Subject: ARM parsing and encoding tests for SBC instruction.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=8409f047312da0318af2a2fce162810ca3a95da3;p=oota-llvm.git

ARM parsing and encoding tests for SBC instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135718 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s
index 68558d8e3d4..f1407b6733f 100644
--- a/test/MC/ARM/arm_instructions.s
+++ b/test/MC/ARM/arm_instructions.s
@@ -39,9 +39,6 @@
 @ CHECK: adc	r1, r2, r3 @ encoding: [0x03,0x10,0xa2,0xe0]
         adc r1,r2,r3
 
-@ CHECK: sbc	r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe0]
-        sbc r1,r2,r3
-
 @ CHECK: bic	r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1]
         bic r1,r2,r3
 
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index 957c0e78938..f8ec6e778b8 100644
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -1240,6 +1240,59 @@ _func:
 @ CHECK: sasxeq	r9, r12, r0             @ encoding: [0x30,0x9f,0x1c,0x06]
 
 
+@------------------------------------------------------------------------------
+@ SBC
+@------------------------------------------------------------------------------
+        sbc r4, r5, #0xf000
+        sbc r4, r5, r6
+        sbc r4, r5, r6, lsl #5
+        sbc r4, r5, r6, lsr #5
+        sbc r4, r5, r6, lsr #5
+        sbc r4, r5, r6, asr #5
+        sbc r4, r5, r6, ror #5
+        sbc r6, r7, r8, lsl r9
+        sbc r6, r7, r8, lsr r9
+        sbc r6, r7, r8, asr r9
+        sbc r6, r7, r8, ror r9
+
+        @ destination register is optional
+        sbc r5, #0xf000
+        sbc r4, r5
+        sbc r4, r5, lsl #5
+        sbc r4, r5, lsr #5
+        sbc r4, r5, lsr #5
+        sbc r4, r5, asr #5
+        sbc r4, r5, ror #5
+        sbc r6, r7, lsl r9
+        sbc r6, r7, lsr r9
+        sbc r6, r7, asr r9
+        sbc r6, r7, ror r9
+
+@ CHECK: sbc	r4, r5, #61440          @ encoding: [0x0f,0x4a,0xc5,0xe2]
+@ CHECK: sbc	r4, r5, r6              @ encoding: [0x06,0x40,0xc5,0xe0]
+@ CHECK: sbc	r4, r5, r6, lsl #5      @ encoding: [0x86,0x42,0xc5,0xe0]
+@ CHECK: sbc	r4, r5, r6, lsr #5      @ encoding: [0xa6,0x42,0xc5,0xe0]
+@ CHECK: sbc	r4, r5, r6, lsr #5      @ encoding: [0xa6,0x42,0xc5,0xe0]
+@ CHECK: sbc	r4, r5, r6, asr #5      @ encoding: [0xc6,0x42,0xc5,0xe0]
+@ CHECK: sbc	r4, r5, r6, ror #5      @ encoding: [0xe6,0x42,0xc5,0xe0]
+@ CHECK: sbc	r6, r7, r8, lsl r9      @ encoding: [0x18,0x69,0xc7,0xe0]
+@ CHECK: sbc	r6, r7, r8, lsr r9      @ encoding: [0x38,0x69,0xc7,0xe0]
+@ CHECK: sbc	r6, r7, r8, asr r9      @ encoding: [0x58,0x69,0xc7,0xe0]
+@ CHECK: sbc	r6, r7, r8, ror r9      @ encoding: [0x78,0x69,0xc7,0xe0]
+
+@ CHECK: sbc	r5, r5, #61440          @ encoding: [0x0f,0x5a,0xc5,0xe2]
+@ CHECK: sbc	r4, r4, r5              @ encoding: [0x05,0x40,0xc4,0xe0]
+@ CHECK: sbc	r4, r4, r5, lsl #5      @ encoding: [0x85,0x42,0xc4,0xe0]
+@ CHECK: sbc	r4, r4, r5, lsr #5      @ encoding: [0xa5,0x42,0xc4,0xe0]
+@ CHECK: sbc	r4, r4, r5, lsr #5      @ encoding: [0xa5,0x42,0xc4,0xe0]
+@ CHECK: sbc	r4, r4, r5, asr #5      @ encoding: [0xc5,0x42,0xc4,0xe0]
+@ CHECK: sbc	r4, r4, r5, ror #5      @ encoding: [0xe5,0x42,0xc4,0xe0]
+@ CHECK: sbc	r6, r6, r7, lsl r9      @ encoding: [0x17,0x69,0xc6,0xe0]
+@ CHECK: sbc	r6, r6, r7, lsr r9      @ encoding: [0x37,0x69,0xc6,0xe0]
+@ CHECK: sbc	r6, r6, r7, asr r9      @ encoding: [0x57,0x69,0xc6,0xe0]
+@ CHECK: sbc	r6, r6, r7, ror r9      @ encoding: [0x77,0x69,0xc6,0xe0]
+
+
 @------------------------------------------------------------------------------
 @ STM*
 @------------------------------------------------------------------------------