From: Eric Christopher <echristo@apple.com>
Date: Sat, 2 Jul 2011 04:06:41 +0000 (+0000)
Subject: Be less specific about register allocation ordering.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=839656120b70333970a7bb696b8047a1c76de1c0;p=oota-llvm.git

Be less specific about register allocation ordering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134308 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/atomic-or.ll b/test/CodeGen/X86/atomic-or.ll
index 9db6f6f06dd..164252de3c1 100644
--- a/test/CodeGen/X86/atomic-or.ll
+++ b/test/CodeGen/X86/atomic-or.ll
@@ -11,7 +11,7 @@ entry:
 ; CHECK: t1:
 ; CHECK: movl    $2147483648, %eax
 ; CHECK: lock
-; CHECK-NEXT: orq %rax, (%rdi)
+; CHECK-NEXT: orq %r{{.*}}, (%r{{.*}})
   %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483648)
   call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
   ret void
@@ -26,7 +26,7 @@ entry:
 ; CHECK: t2:
 ; CHECK-NOT: movl
 ; CHECK: lock
-; CHECK-NEXT: orq $2147483644, (%rdi)
+; CHECK-NEXT: orq $2147483644, (%r{{.*}})
   %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483644)
   call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
   ret void