From: Marek Olsak Date: Sun, 7 Dec 2014 12:18:57 +0000 (+0000) Subject: R600/SI: Add VI instructions X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=7eeb6074973cac6ddaabec1e010d494ff0e9b3c2;p=oota-llvm.git R600/SI: Add VI instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223603 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/R600/AMDGPU.td b/lib/Target/R600/AMDGPU.td index 4cf12430d9d..8a5ca613dc8 100644 --- a/lib/Target/R600/AMDGPU.td +++ b/lib/Target/R600/AMDGPU.td @@ -147,6 +147,11 @@ def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS", def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS", [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536, FeatureWavefrontSize64, FeatureFlatAddressSpace]>; + +def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS", + [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536, + FeatureWavefrontSize64, FeatureFlatAddressSpace]>; + //===----------------------------------------------------------------------===// def AMDGPUInstrInfo : InstrInfo { diff --git a/lib/Target/R600/AMDGPUInstrInfo.cpp b/lib/Target/R600/AMDGPUInstrInfo.cpp index a8fc614d9b0..5beaa6841c9 100644 --- a/lib/Target/R600/AMDGPUInstrInfo.cpp +++ b/lib/Target/R600/AMDGPUInstrInfo.cpp @@ -342,7 +342,7 @@ int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const { namespace llvm { namespace AMDGPU { int getMCOpcode(uint16_t Opcode, unsigned Gen) { - return getMCOpcode(Opcode); + return getMCOpcodeGen(Opcode, (enum Subtarget)Gen); } } } diff --git a/lib/Target/R600/AMDGPUMCInstLower.cpp b/lib/Target/R600/AMDGPUMCInstLower.cpp index bca027f3cb8..2dcebf5f7e1 100644 --- a/lib/Target/R600/AMDGPUMCInstLower.cpp +++ b/lib/Target/R600/AMDGPUMCInstLower.cpp @@ -40,8 +40,13 @@ AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st): { } enum AMDGPUMCInstLower::SISubtarget -AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned) const { - return AMDGPUMCInstLower::SI; +AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned Gen) const { + switch (Gen) { + default: + return AMDGPUMCInstLower::SI; + case AMDGPUSubtarget::VOLCANIC_ISLANDS: + return AMDGPUMCInstLower::VI; + } } unsigned AMDGPUMCInstLower::getMCOpcode(unsigned MIOpcode) const { diff --git a/lib/Target/R600/AMDGPUMCInstLower.h b/lib/Target/R600/AMDGPUMCInstLower.h index 00d1f1ba19a..0ae4d11bf1d 100644 --- a/lib/Target/R600/AMDGPUMCInstLower.h +++ b/lib/Target/R600/AMDGPUMCInstLower.h @@ -22,7 +22,8 @@ class AMDGPUMCInstLower { // This must be kept in sync with the SISubtarget class in SIInstrInfo.td enum SISubtarget { - SI = 0 + SI = 0, + VI = 1 }; MCContext &Ctx; diff --git a/lib/Target/R600/AMDGPUSubtarget.h b/lib/Target/R600/AMDGPUSubtarget.h index e329b12d925..0642b4ad5c8 100644 --- a/lib/Target/R600/AMDGPUSubtarget.h +++ b/lib/Target/R600/AMDGPUSubtarget.h @@ -39,7 +39,8 @@ public: EVERGREEN, NORTHERN_ISLANDS, SOUTHERN_ISLANDS, - SEA_ISLANDS + SEA_ISLANDS, + VOLCANIC_ISLANDS, }; private: diff --git a/lib/Target/R600/CIInstructions.td b/lib/Target/R600/CIInstructions.td new file mode 100644 index 00000000000..fdb58bbebd5 --- /dev/null +++ b/lib/Target/R600/CIInstructions.td @@ -0,0 +1,42 @@ +//===-- CIInstructions.td - CI Instruction Defintions ---------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// Instruction definitions for CI and newer. +//===----------------------------------------------------------------------===// + + +def isCIVI : Predicate < + "Subtarget.getGeneration() == AMDGPUSubtarget::SEA_ISLANDS || " + "Subtarget.getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS" +>; + +//===----------------------------------------------------------------------===// +// VOP1 Instructions +//===----------------------------------------------------------------------===// + +let SubtargetPredicate = isCIVI in { + +defm V_TRUNC_F64 : VOP1Inst , "v_trunc_f64", + VOP_F64_F64, ftrunc +>; +defm V_CEIL_F64 : VOP1Inst , "v_ceil_f64", + VOP_F64_F64, fceil +>; +defm V_FLOOR_F64 : VOP1Inst , "v_floor_f64", + VOP_F64_F64, ffloor +>; +defm V_RNDNE_F64 : VOP1Inst , "v_rndne_f64", + VOP_F64_F64, frint +>; +defm V_LOG_LEGACY_F32 : VOP1Inst , "v_log_legacy_f32", + VOP_F32_F32 +>; +defm V_EXP_LEGACY_F32 : VOP1Inst , "v_exp_legacy_f32", + VOP_F32_F32 +>; +} // End SubtargetPredicate = isCIVI diff --git a/lib/Target/R600/Processors.td b/lib/Target/R600/Processors.td index ce17d7cb7f1..fa78ffcbde0 100644 --- a/lib/Target/R600/Processors.td +++ b/lib/Target/R600/Processors.td @@ -108,3 +108,9 @@ def : Proc<"kaveri", SI_Itin, [FeatureSeaIslands]>; def : Proc<"hawaii", SI_Itin, [FeatureSeaIslands]>; def : Proc<"mullins", SI_Itin, [FeatureSeaIslands]>; + +def : Proc<"tonga", SI_Itin, [FeatureVolcanicIslands]>; + +def : Proc<"iceland", SI_Itin, [FeatureVolcanicIslands]>; + +def : Proc<"carrizo", SI_Itin, [FeatureVolcanicIslands]>; diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td index 3301a82bd09..ff8db67a619 100644 --- a/lib/Target/R600/SIInstrFormats.td +++ b/lib/Target/R600/SIInstrFormats.td @@ -82,6 +82,21 @@ class Enc64 { int Size = 8; } +let Uses = [EXEC] in { + +class VOPCCommon pattern> : + InstSI <(outs VCCReg:$dst), ins, asm, pattern> { + + let DisableEncoding = "$dst"; + let mayLoad = 0; + let mayStore = 0; + let hasSideEffects = 0; + let UseNamedOperandTable = 1; + let VOPC = 1; + let VALU = 1; + let Size = 4; +} + class VOP1Common pattern> : InstSI { let mayLoad = 0; @@ -90,6 +105,19 @@ class VOP1Common pattern> : let UseNamedOperandTable = 1; let VOP1 = 1; let VALU = 1; + let Size = 4; +} + +class VOP2Common pattern> : + InstSI { + + let mayLoad = 0; + let mayStore = 0; + let hasSideEffects = 0; + let UseNamedOperandTable = 1; + let VOP2 = 1; + let VALU = 1; + let Size = 4; } class VOP3Common pattern> : @@ -109,9 +137,10 @@ class VOP3Common pattern> : let VALU = 1; int Size = 8; - let Uses = [EXEC]; } +} // End Uses = [EXEC] + //===----------------------------------------------------------------------===// // Scalar operations //===----------------------------------------------------------------------===// @@ -185,8 +214,8 @@ class SMRDe op, bits<1> imm> : Enc32 { let Inst{31-27} = 0x18; //encoding } -class SOP1 op, dag outs, dag ins, string asm, list pattern> : - InstSI, SOP1e { +class SOP1 pattern> : + InstSI { let mayLoad = 0; let mayStore = 0; @@ -195,8 +224,8 @@ class SOP1 op, dag outs, dag ins, string asm, list pattern> : let SOP1 = 1; } -class SOP2 op, dag outs, dag ins, string asm, list pattern> : - InstSI , SOP2e { +class SOP2 pattern> : + InstSI { let mayLoad = 0; let mayStore = 0; @@ -220,8 +249,8 @@ class SOPC op, dag outs, dag ins, string asm, list pattern> : let UseNamedOperandTable = 1; } -class SOPK op, dag outs, dag ins, string asm, list pattern> : - InstSI , SOPKe { +class SOPK pattern> : + InstSI { let mayLoad = 0; let mayStore = 0; @@ -529,36 +558,16 @@ class VOP1 op, dag outs, dag ins, string asm, list pattern> : VOP1e; class VOP2 op, dag outs, dag ins, string asm, list pattern> : - InstSI , VOP2e { - - let mayLoad = 0; - let mayStore = 0; - let hasSideEffects = 0; - let UseNamedOperandTable = 1; - let VOP2 = 1; - let VALU = 1; -} - -class VOP3 op, dag outs, dag ins, string asm, list pattern> : - VOP3Common , VOP3e; + VOP2Common , VOP2e; class VOP3b op, dag outs, dag ins, string asm, list pattern> : VOP3Common , VOP3be; class VOPC op, dag ins, string asm, list pattern> : - InstSI <(outs VCCReg:$dst), ins, asm, pattern>, VOPCe { - - let DisableEncoding = "$dst"; - let mayLoad = 0; - let mayStore = 0; - let hasSideEffects = 0; - let UseNamedOperandTable = 1; - let VOPC = 1; - let VALU = 1; -} + VOPCCommon , VOPCe ; -class VINTRP op, dag outs, dag ins, string asm, list pattern> : - InstSI , VINTRPe { +class VINTRPCommon pattern> : + InstSI { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -572,8 +581,8 @@ class VINTRP op, dag outs, dag ins, string asm, list pattern> : let Uses = [EXEC] in { -class DS op, dag outs, dag ins, string asm, list pattern> : - InstSI , DSe { +class DS pattern> : + InstSI { let LGKM_CNT = 1; let DS = 1; @@ -581,8 +590,11 @@ class DS op, dag outs, dag ins, string asm, list pattern> : let DisableEncoding = "$m0"; } -class MUBUF op, dag outs, dag ins, string asm, list pattern> : - InstSI, MUBUFe { +class DS_si op, dag outs, dag ins, string asm, list pattern> : + DS , DSe; + +class MUBUF pattern> : + InstSI { let VM_CNT = 1; let EXP_CNT = 1; diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index 4b3be5be578..464eedeea82 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -9,28 +9,51 @@ class vop { field bits<9> SI3; + field bits<10> VI3; } -class vopc si> : vop { +class vopc si, bits<8> vi = !add(0x40, si)> : vop { field bits<8> SI = si; + field bits<8> VI = vi; - field bits<9> SI3 = {0, si{7-0}}; + field bits<9> SI3 = {0, si{7-0}}; + field bits<10> VI3 = {0, 0, vi{7-0}}; } -class vop1 si> : vop { - field bits<8> SI = si; +class vop1 si, bits<8> vi = si> : vop { + field bits<8> SI = si; + field bits<8> VI = vi; - field bits<9> SI3 = {1, 1, si{6-0}}; + field bits<9> SI3 = {1, 1, si{6-0}}; + field bits<10> VI3 = !add(0x140, vi); } -class vop2 si> : vop { +class vop2 si, bits<6> vi = si> : vop { field bits<6> SI = si; + field bits<6> VI = vi; + + field bits<9> SI3 = {1, 0, 0, si{5-0}}; + field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}}; +} + +class vop3 si, bits<10> vi = {0, si}> : vop { + let SI3 = si; + let VI3 = vi; +} + +class sop1 si, bits<8> vi = si> { + field bits<8> SI = si; + field bits<8> VI = vi; +} - field bits<9> SI3 = {1, 0, 0, si{5-0}}; +class sop2 si, bits<7> vi = si> { + field bits<7> SI = si; + field bits<7> VI = vi; } -class vop3 si> : vop { - field bits<9> SI3 = si; +class sopk si, bits<5> vi = si> { + field bits<5> SI = si; + field bits<5> VI = vi; } // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum @@ -38,6 +61,7 @@ class vop3 si> : vop { def SISubtarget { int NONE = -1; int SI = 0; + int VI = 1; } //===----------------------------------------------------------------------===// @@ -190,6 +214,7 @@ def sopp_brtarget : Operand { } include "SIInstrFormats.td" +include "VIInstrFormats.td" let OperandType = "OPERAND_IMMEDIATE" in { @@ -317,52 +342,145 @@ multiclass EXP_m { } def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe; + + def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi; } //===----------------------------------------------------------------------===// // Scalar classes //===----------------------------------------------------------------------===// -class SOP1_32 op, string opName, list pattern> : SOP1 < - op, (outs SReg_32:$dst), (ins SSrc_32:$src0), - opName#" $dst, $src0", pattern ->; +class SOP1_Pseudo pattern> : + SOP1 , + SIMCInstr { + let isPseudo = 1; +} -class SOP1_64 op, string opName, list pattern> : SOP1 < - op, (outs SReg_64:$dst), (ins SSrc_64:$src0), - opName#" $dst, $src0", pattern ->; +class SOP1_Real_si pattern> : + SOP1 , + SOP1e , + SIMCInstr; + +class SOP1_Real_vi pattern> : + SOP1 , + SOP1e , + SIMCInstr; + +multiclass SOP1_32 pattern> { + def "" : SOP1_Pseudo ; + + def _si : SOP1_Real_si ; + + def _vi : SOP1_Real_vi ; +} + +multiclass SOP1_64 pattern> { + def "" : SOP1_Pseudo ; + + def _si : SOP1_Real_si ; + + def _vi : SOP1_Real_vi ; +} + +// no input, 64-bit output. +multiclass SOP1_64_0 pattern> { + def "" : SOP1_Pseudo ; + + def _si : SOP1_Real_si { + let SSRC0 = 0; + } + + def _vi : SOP1_Real_vi { + let SSRC0 = 0; + } +} // 64-bit input, 32-bit output. -class SOP1_32_64 op, string opName, list pattern> : SOP1 < - op, (outs SReg_32:$dst), (ins SSrc_64:$src0), - opName#" $dst, $src0", pattern ->; +multiclass SOP1_32_64 pattern> { + def "" : SOP1_Pseudo ; -class SOP2_32 op, string opName, list pattern> : SOP2 < - op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1), - opName#" $dst, $src0, $src1", pattern ->; + def _si : SOP1_Real_si ; -class SOP2_SELECT_32 op, string opName, list pattern> : SOP2 < - op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), - opName#" $dst, $src0, $src1 [$scc]", pattern ->; + def _vi : SOP1_Real_vi ; +} -class SOP2_64 op, string opName, list pattern> : SOP2 < - op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), - opName#" $dst, $src0, $src1", pattern ->; +class SOP2_Pseudo pattern> : + SOP2, + SIMCInstr { + let isPseudo = 1; + let Size = 4; +} -class SOP2_64_32 op, string opName, list pattern> : SOP2 < - op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1), - opName#" $dst, $src0, $src1", pattern ->; +class SOP2_Real_si pattern> : + SOP2, + SOP2e, + SIMCInstr; -class SOP2_SHIFT_64 op, string opName, list pattern> : SOP2 < - op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1), - opName#" $dst, $src0, $src1", pattern ->; +class SOP2_Real_vi pattern> : + SOP2, + SOP2e, + SIMCInstr; + +multiclass SOP2_SELECT_32 pattern> { + def "" : SOP2_Pseudo ; + + def _si : SOP2_Real_si ; + + def _vi : SOP2_Real_vi ; +} + +multiclass SOP2_32 pattern> { + def "" : SOP2_Pseudo ; + + def _si : SOP2_Real_si ; + + def _vi : SOP2_Real_vi ; +} + +multiclass SOP2_64 pattern> { + def "" : SOP2_Pseudo ; + + def _si : SOP2_Real_si ; + + def _vi : SOP2_Real_vi ; +} + +multiclass SOP2_64_32 pattern> { + def "" : SOP2_Pseudo ; + + def _si : SOP2_Real_si ; + + def _vi : SOP2_Real_vi ; +} class SOPC_Helper op, RegisterClass rc, ValueType vt, @@ -376,15 +494,45 @@ class SOPC_32 op, string opName, PatLeaf cond = COND_NULL> class SOPC_64 op, string opName, PatLeaf cond = COND_NULL> : SOPC_Helper; -class SOPK_32 op, string opName, list pattern> : SOPK < - op, (outs SReg_32:$dst), (ins u16imm:$src0), - opName#" $dst, $src0", pattern ->; +class SOPK_Pseudo pattern> : + SOPK , + SIMCInstr { + let isPseudo = 1; +} -class SOPK_64 op, string opName, list pattern> : SOPK < - op, (outs SReg_64:$dst), (ins u16imm:$src0), - opName#" $dst, $src0", pattern ->; +class SOPK_Real_si pattern> : + SOPK , + SOPKe , + SIMCInstr; + +class SOPK_Real_vi pattern> : + SOPK , + SOPKe , + SIMCInstr; + +multiclass SOPK_32 pattern> { + def "" : SOPK_Pseudo ; + + def _si : SOPK_Real_si ; + + def _vi : SOPK_Real_vi ; +} + +multiclass SOPK_SCC pattern> { + def "" : SOPK_Pseudo ; + + def _si : SOPK_Real_si ; + + def _vi : SOPK_Real_vi ; +} //===----------------------------------------------------------------------===// // SMRD classes @@ -402,6 +550,12 @@ class SMRD_Real_si op, string opName, bit imm, dag outs, dag ins, SMRDe , SIMCInstr; +class SMRD_Real_vi op, string opName, bit imm, dag outs, dag ins, + string asm> : + SMRD , + SMEMe_vi , + SIMCInstr; + multiclass SMRD_m op, string opName, bit imm, dag outs, dag ins, string asm, list pattern> { @@ -409,6 +563,7 @@ multiclass SMRD_m op, string opName, bit imm, dag outs, dag ins, def _si : SMRD_Real_si ; + def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>; } multiclass SMRD_Helper op, string opName, RegisterClass baseClass, @@ -637,7 +792,8 @@ class AtomicNoRet { class VOP1_Pseudo pattern, string opName> : VOP1Common , - SIMCInstr { + VOP , + SIMCInstr { let isPseudo = 1; } @@ -646,7 +802,29 @@ multiclass VOP1_m pattern, def "" : VOP1_Pseudo ; def _si : VOP1, - SIMCInstr ; + SIMCInstr ; + def _vi : VOP1, + SIMCInstr ; +} + +class VOP2_Pseudo pattern, string opName> : + VOP2Common , + VOP , + SIMCInstr { + let isPseudo = 1; +} + +multiclass VOP2_m pattern, + string opName, string revOpSI, string revOpVI> { + def "" : VOP2_Pseudo , + VOP2_REV; + + def _si : VOP2 , + VOP2_REV, + SIMCInstr ; + def _vi : VOP2 , + VOP2_REV, + SIMCInstr ; } class VOP3DisableFields { @@ -663,15 +841,31 @@ class VOP3DisableFields { class VOP3_Pseudo pattern, string opName> : VOP3Common , VOP , - SIMCInstr { + SIMCInstr { let isPseudo = 1; } class VOP3_Real_si op, dag outs, dag ins, string asm, string opName> : - VOP3 , - SIMCInstr; + VOP3Common , + VOP3e , + SIMCInstr; + +class VOP3_Real_vi op, dag outs, dag ins, string asm, string opName> : + VOP3Common , + VOP3e_vi , + SIMCInstr ; + +// VI only instruction +class VOP3_vi op, string opName, dag outs, dag ins, string asm, + list pattern, int NumSrcArgs, bit HasMods = 1> : + VOP3Common , + VOP , + VOP3e_vi , + VOP3DisableFields; -multiclass VOP3_m pattern, +multiclass VOP3_m pattern, string opName, int NumSrcArgs, bit HasMods = 1> { def "" : VOP3_Pseudo ; @@ -680,7 +874,24 @@ multiclass VOP3_m pattern, VOP3DisableFields; + def _vi : VOP3_Real_vi , + VOP3DisableFields; +} + +// VOP3_m without source modifiers +multiclass VOP3_m_nosrcmod pattern, + string opName, int NumSrcArgs, bit HasMods = 1> { + def "" : VOP3_Pseudo ; + + let src0_modifiers = 0, + src1_modifiers = 0, + src2_modifiers = 0 in { + def _si : VOP3_Real_si ; + def _vi : VOP3_Real_vi ; + } } multiclass VOP3_1_m , VOP3DisableFields<0, 0, HasMods>; + + def _vi : VOP3_Real_vi , + VOP3DisableFields<0, 0, HasMods>; } multiclass VOP3_2_m pattern, string opName, string revOp, + list pattern, string opName, string revOpSI, string revOpVI, bit HasMods = 1, bit UseFullOp = 0> { def "" : VOP3_Pseudo , - VOP2_REV; + VOP2_REV; def _si : VOP3_Real_si , - VOP2_REV, + VOP2_REV, + VOP3DisableFields<1, 0, HasMods>; + + def _vi : VOP3_Real_vi , + VOP2_REV, VOP3DisableFields<1, 0, HasMods>; } @@ -717,8 +936,14 @@ multiclass VOP3b_2_m , VOP3DisableFields<1, 0, HasMods>, - SIMCInstr, + SIMCInstr, VOP2_REV; + + // TODO: Do we need this VI variant here? + /*def _vi : VOP3b_vi , + VOP3DisableFields<1, 0, HasMods>, + SIMCInstr, + VOP2_REV;*/ } // End sdst = SIOperand.VCC, Defs = [VCC] } @@ -729,7 +954,12 @@ multiclass VOP3_C_m ; def _si : VOP3_Real_si , - VOP3DisableFields<1, 0, HasMods> { + VOP3DisableFields<1, 0, HasMods> { + let Defs = !if(defExec, [EXEC], []); + } + + def _vi : VOP3_Real_vi , + VOP3DisableFields<1, 0, HasMods> { let Defs = !if(defExec, [EXEC], []); } } @@ -739,7 +969,7 @@ multiclass VOP1_Helper pat64, bit HasMods> { - def _e32 : VOP1 , VOP; + defm _e32 : VOP1_m ; defm _e64 : VOP3_1_m ; } @@ -756,26 +986,36 @@ multiclass VOP1Inst ; -class VOP2_e32 op, string opName, dag outs, dag ins, string asm, - list pattern, string revOp> : - VOP2 , - VOP , - VOP2_REV; +multiclass VOP1InstSI { + + def _e32 : VOP1 , + VOP ; + + def _e64 : VOP3Common , + VOP , + VOP3e , + VOP3DisableFields<0, 0, P.HasModifiers>; +} multiclass VOP2_Helper pat32, dag ins64, string asm64, list pat64, - string revOp, bit HasMods> { - def _e32 : VOP2_e32 ; + string revOpSI, string revOpVI, bit HasMods> { + defm _e32 : VOP2_m ; defm _e64 : VOP3_2_m ; } multiclass VOP2Inst : VOP2_Helper < + string revOpSI = opName, string revOpVI = revOpSI> : VOP2_Helper < op, opName, P.Outs, P.Ins32, P.Asm32, [], P.Ins64, P.Asm64, @@ -785,7 +1025,7 @@ multiclass VOP2Inst ; multiclass VOP2b_Helper pat64, string revOp, bit HasMods> { - def _e32 : VOP2_e32 ; + defm _e32 : VOP2_m ; defm _e64 : VOP3b_2_m ; +class VOPC_Pseudo pattern, string opName> : + VOPCCommon , + VOP , + SIMCInstr { + let isPseudo = 1; +} + +multiclass VOPC_m pattern, + string opName, bit DefExec> { + def "" : VOPC_Pseudo ; + + def _si : VOPC, + SIMCInstr { + let Defs = !if(DefExec, [EXEC], []); + } + + def _vi : VOPC, + SIMCInstr { + let Defs = !if(DefExec, [EXEC], []); + } +} + multiclass VOPC_Helper pat32, dag out64, dag ins64, string asm64, list pat64, bit HasMods, bit DefExec> { - def _e32 : VOPC , VOP { - let Defs = !if(DefExec, [EXEC], []); - } + defm _e32 : VOPC_m ; - defm _e64 : VOP3_C_m ; + defm _e64 : VOP3_C_m ; } multiclass VOPCInst ; +class VOP3InstVI op, string opName, VOPProfile P, + SDPatternOperator node = null_frag> : VOP3_vi < + op, opName#"_vi", P.Outs, P.Ins64, opName#P.Asm64, + !if(!eq(P.NumSrcArgs, 3), + !if(P.HasModifiers, + [(set P.DstVT:$dst, + (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, + i1:$clamp, i32:$omod)), + (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), + (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))], + [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1, + P.Src2VT:$src2))]), + !if(!eq(P.NumSrcArgs, 2), + !if(P.HasModifiers, + [(set P.DstVT:$dst, + (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, + i1:$clamp, i32:$omod)), + (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], + [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]) + /* P.NumSrcArgs == 1 */, + !if(P.HasModifiers, + [(set P.DstVT:$dst, + (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, + i1:$clamp, i32:$omod))))], + [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))), + P.NumSrcArgs, P.HasModifiers +>; + multiclass VOP3b_Helper pattern> : VOP3b_2_m < @@ -934,74 +1222,183 @@ class Vop3ModPat : Pat< i1:$clamp, i32:$omod)>; +//===----------------------------------------------------------------------===// +// Interpolation opcodes +//===----------------------------------------------------------------------===// + +class VINTRP_Pseudo pattern> : + VINTRPCommon , + SIMCInstr { + let isPseudo = 1; +} + +class VINTRP_Real_si op, string opName, dag outs, dag ins, + string asm, list pattern> : + VINTRPCommon , + VINTRPe , + SIMCInstr; + +class VINTRP_Real_vi op, string opName, dag outs, dag ins, + string asm, list pattern> : + VINTRPCommon , + VINTRPe_vi , + SIMCInstr; + +multiclass VINTRP_m op, string opName, dag outs, dag ins, string asm, + string disableEncoding = "", string constraints = "", + list pattern = []> { + let DisableEncoding = disableEncoding, + Constraints = constraints in { + def "" : VINTRP_Pseudo ; + + def _si : VINTRP_Real_si ; + + def _vi : VINTRP_Real_vi ; + } +} + //===----------------------------------------------------------------------===// // Vector I/O classes //===----------------------------------------------------------------------===// -class DS_1A op, dag outs, dag ins, string asm, list pat> : - DS { +class DS_Pseudo pattern> : + DS , + SIMCInstr { + let isPseudo = 1; +} + +class DS_Real_si op, string opName, dag outs, dag ins, string asm> : + DS , + DSe , + SIMCInstr ; + +class DS_Real_vi op, string opName, dag outs, dag ins, string asm> : + DS , + DSe_vi , + SIMCInstr ; + +class DS_1A_Real_si op, string opName, dag outs, dag ins, string asm> : + DS , + DSe , + SIMCInstr { + + // Single load interpret the 2 i8imm operands as a single i16 offset. bits<16> offset; + let offset0 = offset{7-0}; + let offset1 = offset{15-8}; +} + +class DS_1A_Real_vi op, string opName, dag outs, dag ins, string asm> : + DS , + DSe_vi , + SIMCInstr { // Single load interpret the 2 i8imm operands as a single i16 offset. + bits<16> offset; let offset0 = offset{7-0}; let offset1 = offset{15-8}; +} - let hasSideEffects = 0; +multiclass DS_1A_Load_m op, string opName, dag outs, dag ins, string asm, + list pat> { + let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { + def "" : DS_Pseudo ; + + let data0 = 0, data1 = 0 in { + def _si : DS_1A_Real_si ; + def _vi : DS_1A_Real_vi ; + } + } } -class DS_Load_Helper op, string asm, RegisterClass regClass> : DS_1A < +multiclass DS_Load_Helper op, string asm, RegisterClass regClass> + : DS_1A_Load_m < op, + asm, (outs regClass:$vdst), (ins i1imm:$gds, VReg_32:$addr, ds_offset:$offset, M0Reg:$m0), asm#" $vdst, $addr"#"$offset"#" [M0]", - []> { - let data0 = 0; - let data1 = 0; - let mayLoad = 1; - let mayStore = 0; + []>; + +multiclass DS_Load2_m op, string opName, dag outs, dag ins, string asm, + list pat> { + let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { + def "" : DS_Pseudo ; + + let data0 = 0, data1 = 0 in { + def _si : DS_Real_si ; + def _vi : DS_Real_vi ; + } + } } -class DS_Load2_Helper op, string asm, RegisterClass regClass> : DS < +multiclass DS_Load2_Helper op, string asm, RegisterClass regClass> + : DS_Load2_m < op, + asm, (outs regClass:$vdst), (ins i1imm:$gds, VReg_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0), asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]", - []> { - let data0 = 0; - let data1 = 0; - let mayLoad = 1; - let mayStore = 0; - let hasSideEffects = 0; + []>; + +multiclass DS_1A_Store_m op, string opName, dag outs, dag ins, + string asm, list pat> { + let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { + def "" : DS_Pseudo ; + + let data1 = 0, vdst = 0 in { + def _si : DS_1A_Real_si ; + def _vi : DS_1A_Real_vi ; + } + } } -class DS_Store_Helper op, string asm, RegisterClass regClass> : DS_1A < +multiclass DS_Store_Helper op, string asm, RegisterClass regClass> + : DS_1A_Store_m < op, + asm, (outs), (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0), asm#" $addr, $data0"#"$offset"#" [M0]", - []> { - let data1 = 0; - let mayStore = 1; - let mayLoad = 0; - let vdst = 0; + []>; + +multiclass DS_Store_m op, string opName, dag outs, dag ins, + string asm, list pat> { + let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { + def "" : DS_Pseudo ; + + let vdst = 0 in { + def _si : DS_Real_si ; + def _vi : DS_Real_vi ; + } + } } -class DS_Store2_Helper op, string asm, RegisterClass regClass> : DS < +multiclass DS_Store2_Helper op, string asm, RegisterClass regClass> + : DS_Store_m < op, + asm, (outs), (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1, ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0), asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]", - []> { - let mayStore = 1; - let mayLoad = 0; + []>; + +class DS_1A_si op, dag outs, dag ins, string asm, list pat> : + DS_si { + bits<16> offset; + + // Single load interpret the 2 i8imm operands as a single i16 offset. + let offset0 = offset{7-0}; + let offset1 = offset{15-8}; + let hasSideEffects = 0; - let vdst = 0; } // 1 address, 1 data. -class DS_1A1D_RET op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A < +class DS_1A1D_RET op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A_si < op, (outs rc:$vdst), (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0), @@ -1016,7 +1413,7 @@ class DS_1A1D_RET op, string asm, RegisterClass rc, string noRetOp = "" } // 1 address, 2 data. -class DS_1A2D_RET op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A < +class DS_1A2D_RET op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A_si < op, (outs rc:$vdst), (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0), @@ -1029,7 +1426,7 @@ class DS_1A2D_RET op, string asm, RegisterClass rc, string noRetOp = "" } // 1 address, 2 data. -class DS_1A2D_NORET op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A < +class DS_1A2D_NORET op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A_si < op, (outs), (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0), @@ -1041,7 +1438,7 @@ class DS_1A2D_NORET op, string asm, RegisterClass rc, string noRetOp = } // 1 address, 1 data. -class DS_1A1D_NORET op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A < +class DS_1A1D_NORET op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A_si < op, (outs), (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0), @@ -1070,6 +1467,11 @@ class MTBUF_Real_si op, string opName, dag outs, dag ins, MTBUFe , SIMCInstr; +class MTBUF_Real_vi op, string opName, dag outs, dag ins, string asm> : + MTBUF , + MTBUFe_vi , + SIMCInstr ; + multiclass MTBUF_m op, string opName, dag outs, dag ins, string asm, list pattern> { @@ -1077,6 +1479,8 @@ multiclass MTBUF_m op, string opName, dag outs, dag ins, string asm, def _si : MTBUF_Real_si ; + def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>; + } let mayStore = 1, mayLoad = 0 in { @@ -1107,6 +1511,16 @@ multiclass MTBUF_Load_Helper op, string opName, } // mayLoad = 1, mayStore = 0 +//===----------------------------------------------------------------------===// +// MUBUF classes +//===----------------------------------------------------------------------===// + +class MUBUF_si op, dag outs, dag ins, string asm, list pattern> : + MUBUF , MUBUFe ; + +class MUBUF_vi op, dag outs, dag ins, string asm, list pattern> : + MUBUF , MUBUFe_vi ; + class MUBUFAddr64Table { bit IsAddr64 = is_addr64; @@ -1114,7 +1528,7 @@ class MUBUFAddr64Table { } class MUBUFAtomicAddr64 op, dag outs, dag ins, string asm, list pattern> - : MUBUF { + : MUBUF_si { let offen = 0; let idxen = 0; @@ -1125,7 +1539,7 @@ class MUBUFAtomicAddr64 op, dag outs, dag ins, string asm, list pa } class MUBUFAtomicOffset op, dag outs, dag ins, string asm, list pattern> - : MUBUF { + : MUBUF_si { let offen = 0; let idxen = 0; @@ -1196,7 +1610,7 @@ multiclass MUBUF_Load_Helper op, string asm, RegisterClass regClass, let addr64 = 0 in { let offen = 0, idxen = 0, vaddr = 0 in { - def _OFFSET : MUBUF op, string asm, RegisterClass regClass, } let offen = 1, idxen = 0 in { - def _OFFEN : MUBUF op, string asm, RegisterClass regClass, } let offen = 0, idxen = 1 in { - def _IDXEN : MUBUF op, string asm, RegisterClass regClass, } let offen = 1, idxen = 1 in { - def _BOTHEN : MUBUF ; @@ -1232,7 +1646,7 @@ multiclass MUBUF_Load_Helper op, string asm, RegisterClass regClass, } let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in { - def _ADDR64 : MUBUF op, string asm, RegisterClass regClass, } } +multiclass MUBUF_Load_Helper_vi op, string asm, RegisterClass regClass, + ValueType load_vt = i32, + SDPatternOperator ld = null_frag> { + + let lds = 0, mayLoad = 1 in { + let offen = 0, idxen = 0, vaddr = 0 in { + def _OFFSET : MUBUF_vi , + MUBUFAddr64Table<0>; + } + + let offen = 1, idxen = 0 in { + def _OFFEN : MUBUF_vi ; + } + + let offen = 0, idxen = 1 in { + def _IDXEN : MUBUF_vi ; + } + + let offen = 1, idxen = 1 in { + def _BOTHEN : MUBUF_vi ; + } + } +} + multiclass MUBUF_Store_Helper op, string name, RegisterClass vdataClass, ValueType store_vt, SDPatternOperator st> { let addr64 = 0, lds = 0 in { - def "" : MUBUF < + def "" : MUBUF_si < op, (outs), (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset, mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc, @@ -1257,7 +1713,7 @@ multiclass MUBUF_Store_Helper op, string name, RegisterClass vdataClass >; let offen = 0, idxen = 0, vaddr = 0 in { - def _OFFSET : MUBUF < + def _OFFSET : MUBUF_si < op, (outs), (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe), @@ -1269,7 +1725,7 @@ multiclass MUBUF_Store_Helper op, string name, RegisterClass vdataClass } // offen = 0, idxen = 0, vaddr = 0 let offen = 1, idxen = 0 in { - def _OFFEN : MUBUF < + def _OFFEN : MUBUF_si < op, (outs), (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), @@ -1281,7 +1737,7 @@ multiclass MUBUF_Store_Helper op, string name, RegisterClass vdataClass } // End addr64 = 0, lds = 0 - def _ADDR64 : MUBUF < + def _ADDR64 : MUBUF_si < op, (outs), (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset), name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset", @@ -1501,12 +1957,12 @@ def getCommuteOrig : InstrMapping { let ValueCols = [["1"]]; } -def getMCOpcode : InstrMapping { +def getMCOpcodeGen : InstrMapping { let FilterClass = "SIMCInstr"; let RowFields = ["PseudoInstr"]; let ColFields = ["Subtarget"]; let KeyCol = [!cast(SISubtarget.NONE)]; - let ValueCols = [[!cast(SISubtarget.SI)]]; + let ValueCols = [[!cast(SISubtarget.SI)],[!cast(SISubtarget.VI)]]; } def getAddr64Inst : InstrMapping { @@ -1536,3 +1992,5 @@ def getAtomicNoRetOp : InstrMapping { } include "SIInstructions.td" +include "CIInstructions.td" +include "VIInstructions.td" diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 5260f9e6a8a..0e0e3626857 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -26,11 +26,15 @@ def SendMsgImm : Operand { let PrintMethod = "printSendMsg"; } -def isSI : Predicate<"Subtarget.getGeneration() " +def isGCN : Predicate<"Subtarget.getGeneration() " ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">; - +def isSICI : Predicate< + "Subtarget.getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||" + "Subtarget.getGeneration() == AMDGPUSubtarget::SEA_ISLANDS" +>; def isCI : Predicate<"Subtarget.getGeneration() " ">= AMDGPUSubtarget::SEA_ISLANDS">; + def HasFlatAddressSpace : Predicate<"Subtarget.hasFlatAddressSpace()">; def SWaitMatchClass : AsmOperandClass { @@ -43,7 +47,7 @@ def WAIT_FLAG : InstFlag<"printWaitFlag"> { let ParserMatchClass = SWaitMatchClass; } -let SubtargetPredicate = isSI in { +let SubtargetPredicate = isGCN in { //===----------------------------------------------------------------------===// // EXP Instructions @@ -97,102 +101,98 @@ defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < let isMoveImm = 1 in { let isReMaterializable = 1 in { - def S_MOV_B32 : SOP1_32 <0x00000003, "s_mov_b32", []>; - def S_MOV_B64 : SOP1_64 <0x00000004, "s_mov_b64", []>; + defm S_MOV_B32 : SOP1_32 , "s_mov_b32", []>; + defm S_MOV_B64 : SOP1_64 , "s_mov_b64", []>; } // let isRematerializeable = 1 let Uses = [SCC] in { - def S_CMOV_B32 : SOP1_32 <0x00000005, "s_cmov_b32", []>; - def S_CMOV_B64 : SOP1_64 <0x00000006, "s_cmov_b64", []>; + defm S_CMOV_B32 : SOP1_32 , "s_cmov_b32", []>; + defm S_CMOV_B64 : SOP1_64 , "s_cmov_b64", []>; } // End Uses = [SCC] } // End isMoveImm = 1 let Defs = [SCC] in { - def S_NOT_B32 : SOP1_32 <0x00000007, "s_not_b32", + defm S_NOT_B32 : SOP1_32 , "s_not_b32", [(set i32:$dst, (not i32:$src0))] >; - def S_NOT_B64 : SOP1_64 <0x00000008, "s_not_b64", + defm S_NOT_B64 : SOP1_64 , "s_not_b64", [(set i64:$dst, (not i64:$src0))] >; - def S_WQM_B32 : SOP1_32 <0x00000009, "s_wqm_b32", []>; - def S_WQM_B64 : SOP1_64 <0x0000000a, "s_wqm_b64", []>; + defm S_WQM_B32 : SOP1_32 , "s_wqm_b32", []>; + defm S_WQM_B64 : SOP1_64 , "s_wqm_b64", []>; } // End Defs = [SCC] -def S_BREV_B32 : SOP1_32 <0x0000000b, "s_brev_b32", +defm S_BREV_B32 : SOP1_32 , "s_brev_b32", [(set i32:$dst, (AMDGPUbrev i32:$src0))] >; -def S_BREV_B64 : SOP1_64 <0x0000000c, "s_brev_b64", []>; +defm S_BREV_B64 : SOP1_64 , "s_brev_b64", []>; let Defs = [SCC] in { - //def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "s_bcnt0_i32_b32", []>; - //def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "s_bcnt0_i32_b64", []>; - def S_BCNT1_I32_B32 : SOP1_32 <0x0000000f, "s_bcnt1_i32_b32", + //defm S_BCNT0_I32_B32 : SOP1_BCNT0 , "s_bcnt0_i32_b32", []>; + //defm S_BCNT0_I32_B64 : SOP1_BCNT0 , "s_bcnt0_i32_b64", []>; + defm S_BCNT1_I32_B32 : SOP1_32 , "s_bcnt1_i32_b32", [(set i32:$dst, (ctpop i32:$src0))] >; - def S_BCNT1_I32_B64 : SOP1_32_64 <0x00000010, "s_bcnt1_i32_b64", []>; + defm S_BCNT1_I32_B64 : SOP1_32_64 , "s_bcnt1_i32_b64", []>; } // End Defs = [SCC] -//def S_FF0_I32_B32 : SOP1_32 <0x00000011, "s_ff0_i32_b32", []>; -//def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "s_ff0_i32_b64", []>; -def S_FF1_I32_B32 : SOP1_32 <0x00000013, "s_ff1_i32_b32", +//defm S_FF0_I32_B32 : SOP1_32 , "s_ff0_i32_b32", []>; +//defm S_FF0_I32_B64 : SOP1_FF0 , "s_ff0_i32_b64", []>; +defm S_FF1_I32_B32 : SOP1_32 , "s_ff1_i32_b32", [(set i32:$dst, (cttz_zero_undef i32:$src0))] >; -////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "s_ff1_i32_b64", []>; +////defm S_FF1_I32_B64 : SOP1_FF1 , "s_ff1_i32_b64", []>; -def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "s_flbit_i32_b32", +defm S_FLBIT_I32_B32 : SOP1_32 , "s_flbit_i32_b32", [(set i32:$dst, (ctlz_zero_undef i32:$src0))] >; -//def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "s_flbit_i32_b64", []>; -def S_FLBIT_I32 : SOP1_32 <0x00000017, "s_flbit_i32", []>; -//def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "s_flbit_i32_i64", []>; -def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "s_sext_i32_i8", +//defm S_FLBIT_I32_B64 : SOP1_32 , "s_flbit_i32_b64", []>; +defm S_FLBIT_I32 : SOP1_32 , "s_flbit_i32", []>; +//defm S_FLBIT_I32_I64 : SOP1_32 , "s_flbit_i32_i64", []>; +defm S_SEXT_I32_I8 : SOP1_32 , "s_sext_i32_i8", [(set i32:$dst, (sext_inreg i32:$src0, i8))] >; -def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "s_sext_i32_i16", +defm S_SEXT_I32_I16 : SOP1_32 , "s_sext_i32_i16", [(set i32:$dst, (sext_inreg i32:$src0, i16))] >; -////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "s_bitset0_b32", []>; -////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "s_bitset0_b64", []>; -////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "s_bitset1_b32", []>; -////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "s_bitset1_b64", []>; -def S_GETPC_B64 : SOP1 < - 0x0000001f, (outs SReg_64:$dst), (ins), "s_getpc_b64 $dst", [] -> { - let SSRC0 = 0; -} -def S_SETPC_B64 : SOP1_64 <0x00000020, "s_setpc_b64", []>; -def S_SWAPPC_B64 : SOP1_64 <0x00000021, "s_swappc_b64", []>; -def S_RFE_B64 : SOP1_64 <0x00000022, "s_rfe_b64", []>; +////defm S_BITSET0_B32 : SOP1_BITSET0 , "s_bitset0_b32", []>; +////defm S_BITSET0_B64 : SOP1_BITSET0 , "s_bitset0_b64", []>; +////defm S_BITSET1_B32 : SOP1_BITSET1 , "s_bitset1_b32", []>; +////defm S_BITSET1_B64 : SOP1_BITSET1 , "s_bitset1_b64", []>; +defm S_GETPC_B64 : SOP1_64_0 , "s_getpc_b64", []>; +defm S_SETPC_B64 : SOP1_64 , "s_setpc_b64", []>; +defm S_SWAPPC_B64 : SOP1_64 , "s_swappc_b64", []>; +defm S_RFE_B64 : SOP1_64 , "s_rfe_b64", []>; let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in { -def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "s_and_saveexec_b64", []>; -def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "s_or_saveexec_b64", []>; -def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "s_xor_saveexec_b64", []>; -def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "s_andn2_saveexec_b64", []>; -def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "s_orn2_saveexec_b64", []>; -def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "s_nand_saveexec_b64", []>; -def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "s_nor_saveexec_b64", []>; -def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "s_xnor_saveexec_b64", []>; +defm S_AND_SAVEEXEC_B64 : SOP1_64 , "s_and_saveexec_b64", []>; +defm S_OR_SAVEEXEC_B64 : SOP1_64 , "s_or_saveexec_b64", []>; +defm S_XOR_SAVEEXEC_B64 : SOP1_64 , "s_xor_saveexec_b64", []>; +defm S_ANDN2_SAVEEXEC_B64 : SOP1_64 , "s_andn2_saveexec_b64", []>; +defm S_ORN2_SAVEEXEC_B64 : SOP1_64 , "s_orn2_saveexec_b64", []>; +defm S_NAND_SAVEEXEC_B64 : SOP1_64 , "s_nand_saveexec_b64", []>; +defm S_NOR_SAVEEXEC_B64 : SOP1_64 , "s_nor_saveexec_b64", []>; +defm S_XNOR_SAVEEXEC_B64 : SOP1_64 , "s_xnor_saveexec_b64", []>; } // End hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] -def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "s_quadmask_b32", []>; -def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "s_quadmask_b64", []>; -def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "s_movrels_b32", []>; -def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "s_movrels_b64", []>; -def S_MOVRELD_B32 : SOP1_32 <0x00000030, "s_movreld_b32", []>; -def S_MOVRELD_B64 : SOP1_64 <0x00000031, "s_movreld_b64", []>; -//def S_CBRANCH_JOIN : SOP1_ <0x00000032, "s_cbranch_join", []>; -def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "s_mov_regrd_b32", []>; +defm S_QUADMASK_B32 : SOP1_32 , "s_quadmask_b32", []>; +defm S_QUADMASK_B64 : SOP1_64 , "s_quadmask_b64", []>; +defm S_MOVRELS_B32 : SOP1_32 , "s_movrels_b32", []>; +defm S_MOVRELS_B64 : SOP1_64 , "s_movrels_b64", []>; +defm S_MOVRELD_B32 : SOP1_32 , "s_movreld_b32", []>; +defm S_MOVRELD_B64 : SOP1_64 , "s_movreld_b64", []>; +//defm S_CBRANCH_JOIN : SOP1_ , "s_cbranch_join", []>; +defm S_MOV_REGRD_B32 : SOP1_32 , "s_mov_regrd_b32", []>; let Defs = [SCC] in { - def S_ABS_I32 : SOP1_32 <0x00000034, "s_abs_i32", []>; + defm S_ABS_I32 : SOP1_32 , "s_abs_i32", []>; } // End Defs = [SCC] -def S_MOV_FED_B32 : SOP1_32 <0x00000035, "s_mov_fed_b32", []>; +defm S_MOV_FED_B32 : SOP1_32 , "s_mov_fed_b32", []>; //===----------------------------------------------------------------------===// // SOP2 Instructions @@ -200,128 +200,125 @@ def S_MOV_FED_B32 : SOP1_32 <0x00000035, "s_mov_fed_b32", []>; let Defs = [SCC] in { // Carry out goes to SCC let isCommutable = 1 in { -def S_ADD_U32 : SOP2_32 <0x00000000, "s_add_u32", []>; -def S_ADD_I32 : SOP2_32 <0x00000002, "s_add_i32", +defm S_ADD_U32 : SOP2_32 , "s_add_u32", []>; +defm S_ADD_I32 : SOP2_32 , "s_add_i32", [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))] >; } // End isCommutable = 1 -def S_SUB_U32 : SOP2_32 <0x00000001, "s_sub_u32", []>; -def S_SUB_I32 : SOP2_32 <0x00000003, "s_sub_i32", +defm S_SUB_U32 : SOP2_32 , "s_sub_u32", []>; +defm S_SUB_I32 : SOP2_32 , "s_sub_i32", [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))] >; let Uses = [SCC] in { // Carry in comes from SCC let isCommutable = 1 in { -def S_ADDC_U32 : SOP2_32 <0x00000004, "s_addc_u32", +defm S_ADDC_U32 : SOP2_32 , "s_addc_u32", [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; } // End isCommutable = 1 -def S_SUBB_U32 : SOP2_32 <0x00000005, "s_subb_u32", +defm S_SUBB_U32 : SOP2_32 , "s_subb_u32", [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; } // End Uses = [SCC] -def S_MIN_I32 : SOP2_32 <0x00000006, "s_min_i32", +defm S_MIN_I32 : SOP2_32 , "s_min_i32", [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))] >; -def S_MIN_U32 : SOP2_32 <0x00000007, "s_min_u32", +defm S_MIN_U32 : SOP2_32 , "s_min_u32", [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))] >; -def S_MAX_I32 : SOP2_32 <0x00000008, "s_max_i32", +defm S_MAX_I32 : SOP2_32 , "s_max_i32", [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))] >; -def S_MAX_U32 : SOP2_32 <0x00000009, "s_max_u32", +defm S_MAX_U32 : SOP2_32 , "s_max_u32", [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))] >; } // End Defs = [SCC] -def S_CSELECT_B32 : SOP2_SELECT_32 < - 0x0000000a, "s_cselect_b32", - [] ->; +defm S_CSELECT_B32 : SOP2_SELECT_32 , "s_cselect_b32", []>; let Uses = [SCC] in { - def S_CSELECT_B64 : SOP2_64 <0x0000000b, "s_cselect_b64", []>; + defm S_CSELECT_B64 : SOP2_64 , "s_cselect_b64", []>; } // End Uses = [SCC] let Defs = [SCC] in { -def S_AND_B32 : SOP2_32 <0x0000000e, "s_and_b32", +defm S_AND_B32 : SOP2_32 , "s_and_b32", [(set i32:$dst, (and i32:$src0, i32:$src1))] >; -def S_AND_B64 : SOP2_64 <0x0000000f, "s_and_b64", +defm S_AND_B64 : SOP2_64 , "s_and_b64", [(set i64:$dst, (and i64:$src0, i64:$src1))] >; -def S_OR_B32 : SOP2_32 <0x00000010, "s_or_b32", +defm S_OR_B32 : SOP2_32 , "s_or_b32", [(set i32:$dst, (or i32:$src0, i32:$src1))] >; -def S_OR_B64 : SOP2_64 <0x00000011, "s_or_b64", +defm S_OR_B64 : SOP2_64 , "s_or_b64", [(set i64:$dst, (or i64:$src0, i64:$src1))] >; -def S_XOR_B32 : SOP2_32 <0x00000012, "s_xor_b32", +defm S_XOR_B32 : SOP2_32 , "s_xor_b32", [(set i32:$dst, (xor i32:$src0, i32:$src1))] >; -def S_XOR_B64 : SOP2_64 <0x00000013, "s_xor_b64", +defm S_XOR_B64 : SOP2_64 , "s_xor_b64", [(set i64:$dst, (xor i64:$src0, i64:$src1))] >; -def S_ANDN2_B32 : SOP2_32 <0x00000014, "s_andn2_b32", []>; -def S_ANDN2_B64 : SOP2_64 <0x00000015, "s_andn2_b64", []>; -def S_ORN2_B32 : SOP2_32 <0x00000016, "s_orn2_b32", []>; -def S_ORN2_B64 : SOP2_64 <0x00000017, "s_orn2_b64", []>; -def S_NAND_B32 : SOP2_32 <0x00000018, "s_nand_b32", []>; -def S_NAND_B64 : SOP2_64 <0x00000019, "s_nand_b64", []>; -def S_NOR_B32 : SOP2_32 <0x0000001a, "s_nor_b32", []>; -def S_NOR_B64 : SOP2_64 <0x0000001b, "s_nor_b64", []>; -def S_XNOR_B32 : SOP2_32 <0x0000001c, "s_xnor_b32", []>; -def S_XNOR_B64 : SOP2_64 <0x0000001d, "s_xnor_b64", []>; +defm S_ANDN2_B32 : SOP2_32 , "s_andn2_b32", []>; +defm S_ANDN2_B64 : SOP2_64 , "s_andn2_b64", []>; +defm S_ORN2_B32 : SOP2_32 , "s_orn2_b32", []>; +defm S_ORN2_B64 : SOP2_64 , "s_orn2_b64", []>; +defm S_NAND_B32 : SOP2_32 , "s_nand_b32", []>; +defm S_NAND_B64 : SOP2_64 , "s_nand_b64", []>; +defm S_NOR_B32 : SOP2_32 , "s_nor_b32", []>; +defm S_NOR_B64 : SOP2_64 , "s_nor_b64", []>; +defm S_XNOR_B32 : SOP2_32 , "s_xnor_b32", []>; +defm S_XNOR_B64 : SOP2_64 , "s_xnor_b64", []>; } // End Defs = [SCC] // Use added complexity so these patterns are preferred to the VALU patterns. let AddedComplexity = 1 in { let Defs = [SCC] in { -def S_LSHL_B32 : SOP2_32 <0x0000001e, "s_lshl_b32", +defm S_LSHL_B32 : SOP2_32 , "s_lshl_b32", [(set i32:$dst, (shl i32:$src0, i32:$src1))] >; -def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "s_lshl_b64", +defm S_LSHL_B64 : SOP2_64_32 , "s_lshl_b64", [(set i64:$dst, (shl i64:$src0, i32:$src1))] >; -def S_LSHR_B32 : SOP2_32 <0x00000020, "s_lshr_b32", +defm S_LSHR_B32 : SOP2_32 , "s_lshr_b32", [(set i32:$dst, (srl i32:$src0, i32:$src1))] >; -def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "s_lshr_b64", +defm S_LSHR_B64 : SOP2_64_32 , "s_lshr_b64", [(set i64:$dst, (srl i64:$src0, i32:$src1))] >; -def S_ASHR_I32 : SOP2_32 <0x00000022, "s_ashr_i32", +defm S_ASHR_I32 : SOP2_32 , "s_ashr_i32", [(set i32:$dst, (sra i32:$src0, i32:$src1))] >; -def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "s_ashr_i64", +defm S_ASHR_I64 : SOP2_64_32 , "s_ashr_i64", [(set i64:$dst, (sra i64:$src0, i32:$src1))] >; } // End Defs = [SCC] -def S_BFM_B32 : SOP2_32 <0x00000024, "s_bfm_b32", []>; -def S_BFM_B64 : SOP2_64 <0x00000025, "s_bfm_b64", []>; -def S_MUL_I32 : SOP2_32 <0x00000026, "s_mul_i32", +defm S_BFM_B32 : SOP2_32 , "s_bfm_b32", []>; +defm S_BFM_B64 : SOP2_64 , "s_bfm_b64", []>; +defm S_MUL_I32 : SOP2_32 , "s_mul_i32", [(set i32:$dst, (mul i32:$src0, i32:$src1))] >; } // End AddedComplexity = 1 let Defs = [SCC] in { -def S_BFE_U32 : SOP2_32 <0x00000027, "s_bfe_u32", []>; -def S_BFE_I32 : SOP2_32 <0x00000028, "s_bfe_i32", []>; -def S_BFE_U64 : SOP2_64 <0x00000029, "s_bfe_u64", []>; -def S_BFE_I64 : SOP2_64_32 <0x0000002a, "s_bfe_i64", []>; +defm S_BFE_U32 : SOP2_32 , "s_bfe_u32", []>; +defm S_BFE_I32 : SOP2_32 , "s_bfe_i32", []>; +defm S_BFE_U64 : SOP2_64 , "s_bfe_u64", []>; +defm S_BFE_I64 : SOP2_64_32 , "s_bfe_i64", []>; } // End Defs = [SCC] -//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "s_cbranch_g_fork", []>; +//defm S_CBRANCH_G_FORK : SOP2_ , "s_cbranch_g_fork", []>; let Defs = [SCC] in { -def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "s_absdiff_i32", []>; +defm S_ABSDIFF_I32 : SOP2_32 , "s_absdiff_i32", []>; } // End Defs = [SCC] //===----------------------------------------------------------------------===// @@ -351,9 +348,13 @@ def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "s_cmp_le_u32">; //===----------------------------------------------------------------------===// let isReMaterializable = 1 in { -def S_MOVK_I32 : SOPK_32 <0x00000000, "s_movk_i32", []>; +defm S_MOVK_I32 : SOPK_32 , "s_movk_i32", []>; } // End isReMaterializable = 1 -def S_CMOVK_I32 : SOPK_32 <0x00000002, "s_cmovk_i32", []>; +let Uses = [SCC] in { + defm S_CMOVK_I32 : SOPK_32 , "s_cmovk_i32", []>; +} + +let isCompare = 1 in { /* This instruction is disabled for now until we can figure out how to teach @@ -367,38 +368,36 @@ SCC = S_CMPK_EQ_I32 SGPR0, imm VCC = COPY SCC VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 -def S_CMPK_EQ_I32 : SOPK < - 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1), - "s_cmpk_eq_i32", +defm S_CMPK_EQ_I32 : SOPK_SCC , "s_cmpk_eq_i32", [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))] >; */ -let isCompare = 1, Defs = [SCC] in { -def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "s_cmpk_lg_i32", []>; -def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "s_cmpk_gt_i32", []>; -def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "s_cmpk_ge_i32", []>; -def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "s_cmpk_lt_i32", []>; -def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "s_cmpk_le_i32", []>; -def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "s_cmpk_eq_u32", []>; -def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "s_cmpk_lg_u32", []>; -def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "s_cmpk_gt_u32", []>; -def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "s_cmpk_ge_u32", []>; -def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "s_cmpk_lt_u32", []>; -def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "s_cmpk_le_u32", []>; -} // End isCompare = 1, Defs = [SCC] - -let Defs = [SCC], isCommutable = 1 in { - def S_ADDK_I32 : SOPK_32 <0x0000000f, "s_addk_i32", []>; - def S_MULK_I32 : SOPK_32 <0x00000010, "s_mulk_i32", []>; +defm S_CMPK_LG_I32 : SOPK_SCC , "s_cmpk_lg_i32", []>; +defm S_CMPK_GT_I32 : SOPK_SCC , "s_cmpk_gt_i32", []>; +defm S_CMPK_GE_I32 : SOPK_SCC , "s_cmpk_ge_i32", []>; +defm S_CMPK_LT_I32 : SOPK_SCC , "s_cmpk_lt_i32", []>; +defm S_CMPK_LE_I32 : SOPK_SCC , "s_cmpk_le_i32", []>; +defm S_CMPK_EQ_U32 : SOPK_SCC , "s_cmpk_eq_u32", []>; +defm S_CMPK_LG_U32 : SOPK_SCC , "s_cmpk_lg_u32", []>; +defm S_CMPK_GT_U32 : SOPK_SCC , "s_cmpk_gt_u32", []>; +defm S_CMPK_GE_U32 : SOPK_SCC , "s_cmpk_ge_u32", []>; +defm S_CMPK_LT_U32 : SOPK_SCC , "s_cmpk_lt_u32", []>; +defm S_CMPK_LE_U32 : SOPK_SCC , "s_cmpk_le_u32", []>; +} // End isCompare = 1 + +let isCommutable = 1 in { + let Defs = [SCC], isCommutable = 1 in { + defm S_ADDK_I32 : SOPK_32 , "s_addk_i32", []>; + } + defm S_MULK_I32 : SOPK_32 , "s_mulk_i32", []>; } -//def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "s_cbranch_i_fork", []>; -def S_GETREG_B32 : SOPK_32 <0x00000012, "s_getreg_b32", []>; -def S_SETREG_B32 : SOPK_32 <0x00000013, "s_setreg_b32", []>; -def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "s_getreg_regrd_b32", []>; -//def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "s_setreg_imm32_b32", []>; -//def EXP : EXP_ <0x00000000, "exp", []>; +//defm S_CBRANCH_I_FORK : SOPK_ , "s_cbranch_i_fork", []>; +defm S_GETREG_B32 : SOPK_32 , "s_getreg_b32", []>; +defm S_SETREG_B32 : SOPK_32 , "s_setreg_b32", []>; +defm S_GETREG_REGRD_B32 : SOPK_32 , "s_getreg_regrd_b32", []>; +//defm S_SETREG_IMM32_B32 : SOPK_32 , "s_setreg_imm32_b32", []>; //===----------------------------------------------------------------------===// // SOPP Instructions @@ -499,82 +498,84 @@ def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> { let isCompare = 1 in { -defm V_CMP_F_F32 : VOPC_F32 , "v_cmp_f_f32">; -defm V_CMP_LT_F32 : VOPC_F32 , "v_cmp_lt_f32", COND_OLT>; -defm V_CMP_EQ_F32 : VOPC_F32 , "v_cmp_eq_f32", COND_OEQ>; -defm V_CMP_LE_F32 : VOPC_F32 , "v_cmp_le_f32", COND_OLE>; -defm V_CMP_GT_F32 : VOPC_F32 , "v_cmp_gt_f32", COND_OGT>; -defm V_CMP_LG_F32 : VOPC_F32 , "v_cmp_lg_f32">; -defm V_CMP_GE_F32 : VOPC_F32 , "v_cmp_ge_f32", COND_OGE>; -defm V_CMP_O_F32 : VOPC_F32 , "v_cmp_o_f32", COND_O>; -defm V_CMP_U_F32 : VOPC_F32 , "v_cmp_u_f32", COND_UO>; -defm V_CMP_NGE_F32 : VOPC_F32 , "v_cmp_nge_f32">; -defm V_CMP_NLG_F32 : VOPC_F32 , "v_cmp_nlg_f32">; -defm V_CMP_NGT_F32 : VOPC_F32 , "v_cmp_ngt_f32">; -defm V_CMP_NLE_F32 : VOPC_F32 , "v_cmp_nle_f32">; -defm V_CMP_NEQ_F32 : VOPC_F32 , "v_cmp_neq_f32", COND_UNE>; -defm V_CMP_NLT_F32 : VOPC_F32 , "v_cmp_nlt_f32">; -defm V_CMP_TRU_F32 : VOPC_F32 , "v_cmp_tru_f32">; +defm V_CMP_F_F32 : VOPC_F32 , "v_cmp_f_f32">; +defm V_CMP_LT_F32 : VOPC_F32 , "v_cmp_lt_f32", COND_OLT>; +defm V_CMP_EQ_F32 : VOPC_F32 , "v_cmp_eq_f32", COND_OEQ>; +defm V_CMP_LE_F32 : VOPC_F32 , "v_cmp_le_f32", COND_OLE>; +defm V_CMP_GT_F32 : VOPC_F32 , "v_cmp_gt_f32", COND_OGT>; +defm V_CMP_LG_F32 : VOPC_F32 , "v_cmp_lg_f32">; +defm V_CMP_GE_F32 : VOPC_F32 , "v_cmp_ge_f32", COND_OGE>; +defm V_CMP_O_F32 : VOPC_F32 , "v_cmp_o_f32", COND_O>; +defm V_CMP_U_F32 : VOPC_F32 , "v_cmp_u_f32", COND_UO>; +defm V_CMP_NGE_F32 : VOPC_F32 , "v_cmp_nge_f32">; +defm V_CMP_NLG_F32 : VOPC_F32 , "v_cmp_nlg_f32">; +defm V_CMP_NGT_F32 : VOPC_F32 , "v_cmp_ngt_f32">; +defm V_CMP_NLE_F32 : VOPC_F32 , "v_cmp_nle_f32">; +defm V_CMP_NEQ_F32 : VOPC_F32 , "v_cmp_neq_f32", COND_UNE>; +defm V_CMP_NLT_F32 : VOPC_F32 , "v_cmp_nlt_f32">; +defm V_CMP_TRU_F32 : VOPC_F32 , "v_cmp_tru_f32">; let hasSideEffects = 1 in { -defm V_CMPX_F_F32 : VOPCX_F32 , "v_cmpx_f_f32">; -defm V_CMPX_LT_F32 : VOPCX_F32 , "v_cmpx_lt_f32">; -defm V_CMPX_EQ_F32 : VOPCX_F32 , "v_cmpx_eq_f32">; -defm V_CMPX_LE_F32 : VOPCX_F32 , "v_cmpx_le_f32">; -defm V_CMPX_GT_F32 : VOPCX_F32 , "v_cmpx_gt_f32">; -defm V_CMPX_LG_F32 : VOPCX_F32 , "v_cmpx_lg_f32">; -defm V_CMPX_GE_F32 : VOPCX_F32 , "v_cmpx_ge_f32">; -defm V_CMPX_O_F32 : VOPCX_F32 , "v_cmpx_o_f32">; -defm V_CMPX_U_F32 : VOPCX_F32 , "v_cmpx_u_f32">; -defm V_CMPX_NGE_F32 : VOPCX_F32 , "v_cmpx_nge_f32">; -defm V_CMPX_NLG_F32 : VOPCX_F32 , "v_cmpx_nlg_f32">; -defm V_CMPX_NGT_F32 : VOPCX_F32 , "v_cmpx_ngt_f32">; -defm V_CMPX_NLE_F32 : VOPCX_F32 , "v_cmpx_nle_f32">; -defm V_CMPX_NEQ_F32 : VOPCX_F32 , "v_cmpx_neq_f32">; -defm V_CMPX_NLT_F32 : VOPCX_F32 , "v_cmpx_nlt_f32">; -defm V_CMPX_TRU_F32 : VOPCX_F32 , "v_cmpx_tru_f32">; +defm V_CMPX_F_F32 : VOPCX_F32 , "v_cmpx_f_f32">; +defm V_CMPX_LT_F32 : VOPCX_F32 , "v_cmpx_lt_f32">; +defm V_CMPX_EQ_F32 : VOPCX_F32 , "v_cmpx_eq_f32">; +defm V_CMPX_LE_F32 : VOPCX_F32 , "v_cmpx_le_f32">; +defm V_CMPX_GT_F32 : VOPCX_F32 , "v_cmpx_gt_f32">; +defm V_CMPX_LG_F32 : VOPCX_F32 , "v_cmpx_lg_f32">; +defm V_CMPX_GE_F32 : VOPCX_F32 , "v_cmpx_ge_f32">; +defm V_CMPX_O_F32 : VOPCX_F32 , "v_cmpx_o_f32">; +defm V_CMPX_U_F32 : VOPCX_F32 , "v_cmpx_u_f32">; +defm V_CMPX_NGE_F32 : VOPCX_F32 , "v_cmpx_nge_f32">; +defm V_CMPX_NLG_F32 : VOPCX_F32 , "v_cmpx_nlg_f32">; +defm V_CMPX_NGT_F32 : VOPCX_F32 , "v_cmpx_ngt_f32">; +defm V_CMPX_NLE_F32 : VOPCX_F32 , "v_cmpx_nle_f32">; +defm V_CMPX_NEQ_F32 : VOPCX_F32 , "v_cmpx_neq_f32">; +defm V_CMPX_NLT_F32 : VOPCX_F32 , "v_cmpx_nlt_f32">; +defm V_CMPX_TRU_F32 : VOPCX_F32 , "v_cmpx_tru_f32">; } // End hasSideEffects = 1 -defm V_CMP_F_F64 : VOPC_F64 , "v_cmp_f_f64">; -defm V_CMP_LT_F64 : VOPC_F64 , "v_cmp_lt_f64", COND_OLT>; -defm V_CMP_EQ_F64 : VOPC_F64 , "v_cmp_eq_f64", COND_OEQ>; -defm V_CMP_LE_F64 : VOPC_F64 , "v_cmp_le_f64", COND_OLE>; -defm V_CMP_GT_F64 : VOPC_F64 , "v_cmp_gt_f64", COND_OGT>; -defm V_CMP_LG_F64 : VOPC_F64 , "v_cmp_lg_f64">; -defm V_CMP_GE_F64 : VOPC_F64 , "v_cmp_ge_f64", COND_OGE>; -defm V_CMP_O_F64 : VOPC_F64 , "v_cmp_o_f64", COND_O>; -defm V_CMP_U_F64 : VOPC_F64 , "v_cmp_u_f64", COND_UO>; -defm V_CMP_NGE_F64 : VOPC_F64 , "v_cmp_nge_f64">; -defm V_CMP_NLG_F64 : VOPC_F64 , "v_cmp_nlg_f64">; -defm V_CMP_NGT_F64 : VOPC_F64 , "v_cmp_ngt_f64">; -defm V_CMP_NLE_F64 : VOPC_F64 , "v_cmp_nle_f64">; -defm V_CMP_NEQ_F64 : VOPC_F64 , "v_cmp_neq_f64", COND_UNE>; -defm V_CMP_NLT_F64 : VOPC_F64 , "v_cmp_nlt_f64">; -defm V_CMP_TRU_F64 : VOPC_F64 , "v_cmp_tru_f64">; +defm V_CMP_F_F64 : VOPC_F64 , "v_cmp_f_f64">; +defm V_CMP_LT_F64 : VOPC_F64 , "v_cmp_lt_f64", COND_OLT>; +defm V_CMP_EQ_F64 : VOPC_F64 , "v_cmp_eq_f64", COND_OEQ>; +defm V_CMP_LE_F64 : VOPC_F64 , "v_cmp_le_f64", COND_OLE>; +defm V_CMP_GT_F64 : VOPC_F64 , "v_cmp_gt_f64", COND_OGT>; +defm V_CMP_LG_F64 : VOPC_F64 , "v_cmp_lg_f64">; +defm V_CMP_GE_F64 : VOPC_F64 , "v_cmp_ge_f64", COND_OGE>; +defm V_CMP_O_F64 : VOPC_F64 , "v_cmp_o_f64", COND_O>; +defm V_CMP_U_F64 : VOPC_F64 , "v_cmp_u_f64", COND_UO>; +defm V_CMP_NGE_F64 : VOPC_F64 , "v_cmp_nge_f64">; +defm V_CMP_NLG_F64 : VOPC_F64 , "v_cmp_nlg_f64">; +defm V_CMP_NGT_F64 : VOPC_F64 , "v_cmp_ngt_f64">; +defm V_CMP_NLE_F64 : VOPC_F64 , "v_cmp_nle_f64">; +defm V_CMP_NEQ_F64 : VOPC_F64 , "v_cmp_neq_f64", COND_UNE>; +defm V_CMP_NLT_F64 : VOPC_F64 , "v_cmp_nlt_f64">; +defm V_CMP_TRU_F64 : VOPC_F64 , "v_cmp_tru_f64">; let hasSideEffects = 1 in { -defm V_CMPX_F_F64 : VOPCX_F64 , "v_cmpx_f_f64">; -defm V_CMPX_LT_F64 : VOPCX_F64 , "v_cmpx_lt_f64">; -defm V_CMPX_EQ_F64 : VOPCX_F64 , "v_cmpx_eq_f64">; -defm V_CMPX_LE_F64 : VOPCX_F64 , "v_cmpx_le_f64">; -defm V_CMPX_GT_F64 : VOPCX_F64 , "v_cmpx_gt_f64">; -defm V_CMPX_LG_F64 : VOPCX_F64 , "v_cmpx_lg_f64">; -defm V_CMPX_GE_F64 : VOPCX_F64 , "v_cmpx_ge_f64">; -defm V_CMPX_O_F64 : VOPCX_F64 , "v_cmpx_o_f64">; -defm V_CMPX_U_F64 : VOPCX_F64 , "v_cmpx_u_f64">; -defm V_CMPX_NGE_F64 : VOPCX_F64 , "v_cmpx_nge_f64">; -defm V_CMPX_NLG_F64 : VOPCX_F64 , "v_cmpx_nlg_f64">; -defm V_CMPX_NGT_F64 : VOPCX_F64 , "v_cmpx_ngt_f64">; -defm V_CMPX_NLE_F64 : VOPCX_F64 , "v_cmpx_nle_f64">; -defm V_CMPX_NEQ_F64 : VOPCX_F64 , "v_cmpx_neq_f64">; -defm V_CMPX_NLT_F64 : VOPCX_F64 , "v_cmpx_nlt_f64">; -defm V_CMPX_TRU_F64 : VOPCX_F64 , "v_cmpx_tru_f64">; +defm V_CMPX_F_F64 : VOPCX_F64 , "v_cmpx_f_f64">; +defm V_CMPX_LT_F64 : VOPCX_F64 , "v_cmpx_lt_f64">; +defm V_CMPX_EQ_F64 : VOPCX_F64 , "v_cmpx_eq_f64">; +defm V_CMPX_LE_F64 : VOPCX_F64 , "v_cmpx_le_f64">; +defm V_CMPX_GT_F64 : VOPCX_F64 , "v_cmpx_gt_f64">; +defm V_CMPX_LG_F64 : VOPCX_F64 , "v_cmpx_lg_f64">; +defm V_CMPX_GE_F64 : VOPCX_F64 , "v_cmpx_ge_f64">; +defm V_CMPX_O_F64 : VOPCX_F64 , "v_cmpx_o_f64">; +defm V_CMPX_U_F64 : VOPCX_F64 , "v_cmpx_u_f64">; +defm V_CMPX_NGE_F64 : VOPCX_F64 , "v_cmpx_nge_f64">; +defm V_CMPX_NLG_F64 : VOPCX_F64 , "v_cmpx_nlg_f64">; +defm V_CMPX_NGT_F64 : VOPCX_F64 , "v_cmpx_ngt_f64">; +defm V_CMPX_NLE_F64 : VOPCX_F64 , "v_cmpx_nle_f64">; +defm V_CMPX_NEQ_F64 : VOPCX_F64 , "v_cmpx_neq_f64">; +defm V_CMPX_NLT_F64 : VOPCX_F64 , "v_cmpx_nlt_f64">; +defm V_CMPX_TRU_F64 : VOPCX_F64 , "v_cmpx_tru_f64">; } // End hasSideEffects = 1 +let SubtargetPredicate = isSICI in { + defm V_CMPS_F_F32 : VOPC_F32 , "v_cmps_f_f32">; defm V_CMPS_LT_F32 : VOPC_F32 , "v_cmps_lt_f32">; defm V_CMPS_EQ_F32 : VOPC_F32 , "v_cmps_eq_f32">; @@ -651,104 +652,106 @@ defm V_CMPSX_TRU_F64 : VOPC_F64 , "v_cmpsx_tru_f64">; } // End hasSideEffects = 1, Defs = [EXEC] -defm V_CMP_F_I32 : VOPC_I32 , "v_cmp_f_i32">; -defm V_CMP_LT_I32 : VOPC_I32 , "v_cmp_lt_i32", COND_SLT>; -defm V_CMP_EQ_I32 : VOPC_I32 , "v_cmp_eq_i32", COND_EQ>; -defm V_CMP_LE_I32 : VOPC_I32 , "v_cmp_le_i32", COND_SLE>; -defm V_CMP_GT_I32 : VOPC_I32 , "v_cmp_gt_i32", COND_SGT>; -defm V_CMP_NE_I32 : VOPC_I32 , "v_cmp_ne_i32", COND_NE>; -defm V_CMP_GE_I32 : VOPC_I32 , "v_cmp_ge_i32", COND_SGE>; -defm V_CMP_T_I32 : VOPC_I32 , "v_cmp_t_i32">; +} // End SubtargetPredicate = isSICI + +defm V_CMP_F_I32 : VOPC_I32 , "v_cmp_f_i32">; +defm V_CMP_LT_I32 : VOPC_I32 , "v_cmp_lt_i32", COND_SLT>; +defm V_CMP_EQ_I32 : VOPC_I32 , "v_cmp_eq_i32", COND_EQ>; +defm V_CMP_LE_I32 : VOPC_I32 , "v_cmp_le_i32", COND_SLE>; +defm V_CMP_GT_I32 : VOPC_I32 , "v_cmp_gt_i32", COND_SGT>; +defm V_CMP_NE_I32 : VOPC_I32 , "v_cmp_ne_i32", COND_NE>; +defm V_CMP_GE_I32 : VOPC_I32 , "v_cmp_ge_i32", COND_SGE>; +defm V_CMP_T_I32 : VOPC_I32 , "v_cmp_t_i32">; let hasSideEffects = 1 in { -defm V_CMPX_F_I32 : VOPCX_I32 , "v_cmpx_f_i32">; -defm V_CMPX_LT_I32 : VOPCX_I32 , "v_cmpx_lt_i32">; -defm V_CMPX_EQ_I32 : VOPCX_I32 , "v_cmpx_eq_i32">; -defm V_CMPX_LE_I32 : VOPCX_I32 , "v_cmpx_le_i32">; -defm V_CMPX_GT_I32 : VOPCX_I32 , "v_cmpx_gt_i32">; -defm V_CMPX_NE_I32 : VOPCX_I32 , "v_cmpx_ne_i32">; -defm V_CMPX_GE_I32 : VOPCX_I32 , "v_cmpx_ge_i32">; -defm V_CMPX_T_I32 : VOPCX_I32 , "v_cmpx_t_i32">; +defm V_CMPX_F_I32 : VOPCX_I32 , "v_cmpx_f_i32">; +defm V_CMPX_LT_I32 : VOPCX_I32 , "v_cmpx_lt_i32">; +defm V_CMPX_EQ_I32 : VOPCX_I32 , "v_cmpx_eq_i32">; +defm V_CMPX_LE_I32 : VOPCX_I32 , "v_cmpx_le_i32">; +defm V_CMPX_GT_I32 : VOPCX_I32 , "v_cmpx_gt_i32">; +defm V_CMPX_NE_I32 : VOPCX_I32 , "v_cmpx_ne_i32">; +defm V_CMPX_GE_I32 : VOPCX_I32 , "v_cmpx_ge_i32">; +defm V_CMPX_T_I32 : VOPCX_I32 , "v_cmpx_t_i32">; } // End hasSideEffects = 1 -defm V_CMP_F_I64 : VOPC_I64 , "v_cmp_f_i64">; -defm V_CMP_LT_I64 : VOPC_I64 , "v_cmp_lt_i64", COND_SLT>; -defm V_CMP_EQ_I64 : VOPC_I64 , "v_cmp_eq_i64", COND_EQ>; -defm V_CMP_LE_I64 : VOPC_I64 , "v_cmp_le_i64", COND_SLE>; -defm V_CMP_GT_I64 : VOPC_I64 , "v_cmp_gt_i64", COND_SGT>; -defm V_CMP_NE_I64 : VOPC_I64 , "v_cmp_ne_i64", COND_NE>; -defm V_CMP_GE_I64 : VOPC_I64 , "v_cmp_ge_i64", COND_SGE>; -defm V_CMP_T_I64 : VOPC_I64 , "v_cmp_t_i64">; +defm V_CMP_F_I64 : VOPC_I64 , "v_cmp_f_i64">; +defm V_CMP_LT_I64 : VOPC_I64 , "v_cmp_lt_i64", COND_SLT>; +defm V_CMP_EQ_I64 : VOPC_I64 , "v_cmp_eq_i64", COND_EQ>; +defm V_CMP_LE_I64 : VOPC_I64 , "v_cmp_le_i64", COND_SLE>; +defm V_CMP_GT_I64 : VOPC_I64 , "v_cmp_gt_i64", COND_SGT>; +defm V_CMP_NE_I64 : VOPC_I64 , "v_cmp_ne_i64", COND_NE>; +defm V_CMP_GE_I64 : VOPC_I64 , "v_cmp_ge_i64", COND_SGE>; +defm V_CMP_T_I64 : VOPC_I64 , "v_cmp_t_i64">; let hasSideEffects = 1 in { -defm V_CMPX_F_I64 : VOPCX_I64 , "v_cmpx_f_i64">; -defm V_CMPX_LT_I64 : VOPCX_I64 , "v_cmpx_lt_i64">; -defm V_CMPX_EQ_I64 : VOPCX_I64 , "v_cmpx_eq_i64">; -defm V_CMPX_LE_I64 : VOPCX_I64 , "v_cmpx_le_i64">; -defm V_CMPX_GT_I64 : VOPCX_I64 , "v_cmpx_gt_i64">; -defm V_CMPX_NE_I64 : VOPCX_I64 , "v_cmpx_ne_i64">; -defm V_CMPX_GE_I64 : VOPCX_I64 , "v_cmpx_ge_i64">; -defm V_CMPX_T_I64 : VOPCX_I64 , "v_cmpx_t_i64">; +defm V_CMPX_F_I64 : VOPCX_I64 , "v_cmpx_f_i64">; +defm V_CMPX_LT_I64 : VOPCX_I64 , "v_cmpx_lt_i64">; +defm V_CMPX_EQ_I64 : VOPCX_I64 , "v_cmpx_eq_i64">; +defm V_CMPX_LE_I64 : VOPCX_I64 , "v_cmpx_le_i64">; +defm V_CMPX_GT_I64 : VOPCX_I64 , "v_cmpx_gt_i64">; +defm V_CMPX_NE_I64 : VOPCX_I64 , "v_cmpx_ne_i64">; +defm V_CMPX_GE_I64 : VOPCX_I64 , "v_cmpx_ge_i64">; +defm V_CMPX_T_I64 : VOPCX_I64 , "v_cmpx_t_i64">; } // End hasSideEffects = 1 -defm V_CMP_F_U32 : VOPC_I32 , "v_cmp_f_u32">; -defm V_CMP_LT_U32 : VOPC_I32 , "v_cmp_lt_u32", COND_ULT>; -defm V_CMP_EQ_U32 : VOPC_I32 , "v_cmp_eq_u32", COND_EQ>; -defm V_CMP_LE_U32 : VOPC_I32 , "v_cmp_le_u32", COND_ULE>; -defm V_CMP_GT_U32 : VOPC_I32 , "v_cmp_gt_u32", COND_UGT>; -defm V_CMP_NE_U32 : VOPC_I32 , "v_cmp_ne_u32", COND_NE>; -defm V_CMP_GE_U32 : VOPC_I32 , "v_cmp_ge_u32", COND_UGE>; -defm V_CMP_T_U32 : VOPC_I32 , "v_cmp_t_u32">; +defm V_CMP_F_U32 : VOPC_I32 , "v_cmp_f_u32">; +defm V_CMP_LT_U32 : VOPC_I32 , "v_cmp_lt_u32", COND_ULT>; +defm V_CMP_EQ_U32 : VOPC_I32 , "v_cmp_eq_u32", COND_EQ>; +defm V_CMP_LE_U32 : VOPC_I32 , "v_cmp_le_u32", COND_ULE>; +defm V_CMP_GT_U32 : VOPC_I32 , "v_cmp_gt_u32", COND_UGT>; +defm V_CMP_NE_U32 : VOPC_I32 , "v_cmp_ne_u32", COND_NE>; +defm V_CMP_GE_U32 : VOPC_I32 , "v_cmp_ge_u32", COND_UGE>; +defm V_CMP_T_U32 : VOPC_I32 , "v_cmp_t_u32">; let hasSideEffects = 1 in { -defm V_CMPX_F_U32 : VOPCX_I32 , "v_cmpx_f_u32">; -defm V_CMPX_LT_U32 : VOPCX_I32 , "v_cmpx_lt_u32">; -defm V_CMPX_EQ_U32 : VOPCX_I32 , "v_cmpx_eq_u32">; -defm V_CMPX_LE_U32 : VOPCX_I32 , "v_cmpx_le_u32">; -defm V_CMPX_GT_U32 : VOPCX_I32 , "v_cmpx_gt_u32">; -defm V_CMPX_NE_U32 : VOPCX_I32 , "v_cmpx_ne_u32">; -defm V_CMPX_GE_U32 : VOPCX_I32 , "v_cmpx_ge_u32">; -defm V_CMPX_T_U32 : VOPCX_I32 , "v_cmpx_t_u32">; +defm V_CMPX_F_U32 : VOPCX_I32 , "v_cmpx_f_u32">; +defm V_CMPX_LT_U32 : VOPCX_I32 , "v_cmpx_lt_u32">; +defm V_CMPX_EQ_U32 : VOPCX_I32 , "v_cmpx_eq_u32">; +defm V_CMPX_LE_U32 : VOPCX_I32 , "v_cmpx_le_u32">; +defm V_CMPX_GT_U32 : VOPCX_I32 , "v_cmpx_gt_u32">; +defm V_CMPX_NE_U32 : VOPCX_I32 , "v_cmpx_ne_u32">; +defm V_CMPX_GE_U32 : VOPCX_I32 , "v_cmpx_ge_u32">; +defm V_CMPX_T_U32 : VOPCX_I32 , "v_cmpx_t_u32">; } // End hasSideEffects = 1 -defm V_CMP_F_U64 : VOPC_I64 , "v_cmp_f_u64">; -defm V_CMP_LT_U64 : VOPC_I64 , "v_cmp_lt_u64", COND_ULT>; -defm V_CMP_EQ_U64 : VOPC_I64 , "v_cmp_eq_u64", COND_EQ>; -defm V_CMP_LE_U64 : VOPC_I64 , "v_cmp_le_u64", COND_ULE>; -defm V_CMP_GT_U64 : VOPC_I64 , "v_cmp_gt_u64", COND_UGT>; -defm V_CMP_NE_U64 : VOPC_I64 , "v_cmp_ne_u64", COND_NE>; -defm V_CMP_GE_U64 : VOPC_I64 , "v_cmp_ge_u64", COND_UGE>; -defm V_CMP_T_U64 : VOPC_I64 , "v_cmp_t_u64">; +defm V_CMP_F_U64 : VOPC_I64 , "v_cmp_f_u64">; +defm V_CMP_LT_U64 : VOPC_I64 , "v_cmp_lt_u64", COND_ULT>; +defm V_CMP_EQ_U64 : VOPC_I64 , "v_cmp_eq_u64", COND_EQ>; +defm V_CMP_LE_U64 : VOPC_I64 , "v_cmp_le_u64", COND_ULE>; +defm V_CMP_GT_U64 : VOPC_I64 , "v_cmp_gt_u64", COND_UGT>; +defm V_CMP_NE_U64 : VOPC_I64 , "v_cmp_ne_u64", COND_NE>; +defm V_CMP_GE_U64 : VOPC_I64 , "v_cmp_ge_u64", COND_UGE>; +defm V_CMP_T_U64 : VOPC_I64 , "v_cmp_t_u64">; let hasSideEffects = 1 in { -defm V_CMPX_F_U64 : VOPCX_I64 , "v_cmpx_f_u64">; -defm V_CMPX_LT_U64 : VOPCX_I64 , "v_cmpx_lt_u64">; -defm V_CMPX_EQ_U64 : VOPCX_I64 , "v_cmpx_eq_u64">; -defm V_CMPX_LE_U64 : VOPCX_I64 , "v_cmpx_le_u64">; -defm V_CMPX_GT_U64 : VOPCX_I64 , "v_cmpx_gt_u64">; -defm V_CMPX_NE_U64 : VOPCX_I64 , "v_cmpx_ne_u64">; -defm V_CMPX_GE_U64 : VOPCX_I64 , "v_cmpx_ge_u64">; -defm V_CMPX_T_U64 : VOPCX_I64 , "v_cmpx_t_u64">; +defm V_CMPX_F_U64 : VOPCX_I64 , "v_cmpx_f_u64">; +defm V_CMPX_LT_U64 : VOPCX_I64 , "v_cmpx_lt_u64">; +defm V_CMPX_EQ_U64 : VOPCX_I64 , "v_cmpx_eq_u64">; +defm V_CMPX_LE_U64 : VOPCX_I64 , "v_cmpx_le_u64">; +defm V_CMPX_GT_U64 : VOPCX_I64 , "v_cmpx_gt_u64">; +defm V_CMPX_NE_U64 : VOPCX_I64 , "v_cmpx_ne_u64">; +defm V_CMPX_GE_U64 : VOPCX_I64 , "v_cmpx_ge_u64">; +defm V_CMPX_T_U64 : VOPCX_I64 , "v_cmpx_t_u64">; } // End hasSideEffects = 1 -defm V_CMP_CLASS_F32 : VOPC_F32 , "v_cmp_class_f32">; +defm V_CMP_CLASS_F32 : VOPC_F32 , "v_cmp_class_f32">; let hasSideEffects = 1 in { -defm V_CMPX_CLASS_F32 : VOPCX_F32 , "v_cmpx_class_f32">; +defm V_CMPX_CLASS_F32 : VOPCX_F32 , "v_cmpx_class_f32">; } // End hasSideEffects = 1 -defm V_CMP_CLASS_F64 : VOPC_F64 , "v_cmp_class_f64">; +defm V_CMP_CLASS_F64 : VOPC_F64 , "v_cmp_class_f64">; let hasSideEffects = 1 in { -defm V_CMPX_CLASS_F64 : VOPCX_F64 , "v_cmpx_class_f64">; +defm V_CMPX_CLASS_F64 : VOPCX_F64 , "v_cmpx_class_f64">; } // End hasSideEffects = 1 } // End isCompare = 1 @@ -848,33 +851,35 @@ def DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "ds_max_f64", VReg_64, "ds_max_f64">; // TODO: _SRC2_* forms -def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "ds_write_b32", VReg_32>; -def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "ds_write_b8", VReg_32>; -def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "ds_write_b16", VReg_32>; -def DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "ds_write_b64", VReg_64>; +defm DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "ds_write_b32", VReg_32>; +defm DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "ds_write_b8", VReg_32>; +defm DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "ds_write_b16", VReg_32>; +defm DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "ds_write_b64", VReg_64>; -def DS_READ_B32 : DS_Load_Helper <0x00000036, "ds_read_b32", VReg_32>; -def DS_READ_I8 : DS_Load_Helper <0x00000039, "ds_read_i8", VReg_32>; -def DS_READ_U8 : DS_Load_Helper <0x0000003a, "ds_read_u8", VReg_32>; -def DS_READ_I16 : DS_Load_Helper <0x0000003b, "ds_read_i16", VReg_32>; -def DS_READ_U16 : DS_Load_Helper <0x0000003c, "ds_read_u16", VReg_32>; -def DS_READ_B64 : DS_Load_Helper <0x00000076, "ds_read_b64", VReg_64>; +defm DS_READ_B32 : DS_Load_Helper <0x00000036, "ds_read_b32", VReg_32>; +defm DS_READ_I8 : DS_Load_Helper <0x00000039, "ds_read_i8", VReg_32>; +defm DS_READ_U8 : DS_Load_Helper <0x0000003a, "ds_read_u8", VReg_32>; +defm DS_READ_I16 : DS_Load_Helper <0x0000003b, "ds_read_i16", VReg_32>; +defm DS_READ_U16 : DS_Load_Helper <0x0000003c, "ds_read_u16", VReg_32>; +defm DS_READ_B64 : DS_Load_Helper <0x00000076, "ds_read_b64", VReg_64>; // 2 forms. -def DS_WRITE2_B32 : DS_Store2_Helper <0x0000000E, "ds_write2_b32", VReg_32>; -def DS_WRITE2ST64_B32 : DS_Store2_Helper <0x0000000F, "ds_write2st64_b32", VReg_32>; -def DS_WRITE2_B64 : DS_Store2_Helper <0x0000004E, "ds_write2_b64", VReg_64>; -def DS_WRITE2ST64_B64 : DS_Store2_Helper <0x0000004F, "ds_write2st64_b64", VReg_64>; +defm DS_WRITE2_B32 : DS_Store2_Helper <0x0000000E, "ds_write2_b32", VReg_32>; +defm DS_WRITE2ST64_B32 : DS_Store2_Helper <0x0000000F, "ds_write2st64_b32", VReg_32>; +defm DS_WRITE2_B64 : DS_Store2_Helper <0x0000004E, "ds_write2_b64", VReg_64>; +defm DS_WRITE2ST64_B64 : DS_Store2_Helper <0x0000004F, "ds_write2st64_b64", VReg_64>; -def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "ds_read2_b32", VReg_64>; -def DS_READ2ST64_B32 : DS_Load2_Helper <0x00000038, "ds_read2st64_b32", VReg_64>; -def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "ds_read2_b64", VReg_128>; -def DS_READ2ST64_B64 : DS_Load2_Helper <0x00000076, "ds_read2st64_b64", VReg_128>; +defm DS_READ2_B32 : DS_Load2_Helper <0x00000037, "ds_read2_b32", VReg_64>; +defm DS_READ2ST64_B32 : DS_Load2_Helper <0x00000038, "ds_read2st64_b32", VReg_64>; +defm DS_READ2_B64 : DS_Load2_Helper <0x00000075, "ds_read2_b64", VReg_128>; +defm DS_READ2ST64_B64 : DS_Load2_Helper <0x00000076, "ds_read2st64_b64", VReg_128>; //===----------------------------------------------------------------------===// // MUBUF Instructions //===----------------------------------------------------------------------===// +let SubtargetPredicate = isSICI in { + //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "buffer_load_format_x", []>; //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "buffer_load_format_xy", []>; //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "buffer_load_format_xyz", []>; @@ -982,6 +987,8 @@ defm BUFFER_ATOMIC_XOR : MUBUF_Atomic < //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "buffer_wbinvl1_sc", []>; //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "buffer_wbinvl1", []>; +} // End SubtargetPredicate = isSICI + //===----------------------------------------------------------------------===// // MTBUF Instructions //===----------------------------------------------------------------------===// @@ -1243,291 +1250,299 @@ defm V_CVT_U32_F64 : VOP1Inst , "v_cvt_u32_f64", defm V_CVT_F64_U32 : VOP1Inst , "v_cvt_f64_u32", VOP_F64_I32, uint_to_fp >; - -defm V_FRACT_F32 : VOP1Inst , "v_fract_f32", +defm V_FRACT_F32 : VOP1Inst , "v_fract_f32", VOP_F32_F32, AMDGPUfract >; -defm V_TRUNC_F32 : VOP1Inst , "v_trunc_f32", +defm V_TRUNC_F32 : VOP1Inst , "v_trunc_f32", VOP_F32_F32, ftrunc >; -defm V_CEIL_F32 : VOP1Inst , "v_ceil_f32", +defm V_CEIL_F32 : VOP1Inst , "v_ceil_f32", VOP_F32_F32, fceil >; -defm V_RNDNE_F32 : VOP1Inst , "v_rndne_f32", +defm V_RNDNE_F32 : VOP1Inst , "v_rndne_f32", VOP_F32_F32, frint >; -defm V_FLOOR_F32 : VOP1Inst , "v_floor_f32", +defm V_FLOOR_F32 : VOP1Inst , "v_floor_f32", VOP_F32_F32, ffloor >; -defm V_EXP_F32 : VOP1Inst , "v_exp_f32", +defm V_EXP_F32 : VOP1Inst , "v_exp_f32", VOP_F32_F32, fexp2 >; -defm V_LOG_CLAMP_F32 : VOP1Inst , "v_log_clamp_f32", VOP_F32_F32>; -defm V_LOG_F32 : VOP1Inst , "v_log_f32", +defm V_LOG_F32 : VOP1Inst , "v_log_f32", VOP_F32_F32, flog2 >; - -defm V_RCP_CLAMP_F32 : VOP1Inst , "v_rcp_clamp_f32", VOP_F32_F32>; -defm V_RCP_LEGACY_F32 : VOP1Inst , "v_rcp_legacy_f32", VOP_F32_F32>; -defm V_RCP_F32 : VOP1Inst , "v_rcp_f32", +defm V_RCP_F32 : VOP1Inst , "v_rcp_f32", VOP_F32_F32, AMDGPUrcp >; -defm V_RCP_IFLAG_F32 : VOP1Inst , "v_rcp_iflag_f32", VOP_F32_F32>; -defm V_RSQ_CLAMP_F32 : VOP1Inst , "v_rsq_clamp_f32", - VOP_F32_F32, AMDGPUrsq_clamped +defm V_RCP_IFLAG_F32 : VOP1Inst , "v_rcp_iflag_f32", + VOP_F32_F32 >; -defm V_RSQ_LEGACY_F32 : VOP1Inst , "v_rsq_legacy_f32", - VOP_F32_F32, AMDGPUrsq_legacy ->; -defm V_RSQ_F32 : VOP1Inst , "v_rsq_f32", +defm V_RSQ_F32 : VOP1Inst , "v_rsq_f32", VOP_F32_F32, AMDGPUrsq >; -defm V_RCP_F64 : VOP1Inst , "v_rcp_f64", +defm V_RCP_F64 : VOP1Inst , "v_rcp_f64", VOP_F64_F64, AMDGPUrcp >; -defm V_RCP_CLAMP_F64 : VOP1Inst , "v_rcp_clamp_f64", VOP_F64_F64>; -defm V_RSQ_F64 : VOP1Inst , "v_rsq_f64", +defm V_RSQ_F64 : VOP1Inst , "v_rsq_f64", VOP_F64_F64, AMDGPUrsq >; -defm V_RSQ_CLAMP_F64 : VOP1Inst , "v_rsq_clamp_f64", - VOP_F64_F64, AMDGPUrsq_clamped ->; -defm V_SQRT_F32 : VOP1Inst , "v_sqrt_f32", +defm V_SQRT_F32 : VOP1Inst , "v_sqrt_f32", VOP_F32_F32, fsqrt >; -defm V_SQRT_F64 : VOP1Inst , "v_sqrt_f64", +defm V_SQRT_F64 : VOP1Inst , "v_sqrt_f64", VOP_F64_F64, fsqrt >; -defm V_SIN_F32 : VOP1Inst , "v_sin_f32", +defm V_SIN_F32 : VOP1Inst , "v_sin_f32", VOP_F32_F32, AMDGPUsin >; -defm V_COS_F32 : VOP1Inst , "v_cos_f32", +defm V_COS_F32 : VOP1Inst , "v_cos_f32", VOP_F32_F32, AMDGPUcos >; -defm V_NOT_B32 : VOP1Inst , "v_not_b32", VOP_I32_I32>; -defm V_BFREV_B32 : VOP1Inst , "v_bfrev_b32", VOP_I32_I32>; -defm V_FFBH_U32 : VOP1Inst , "v_ffbh_u32", VOP_I32_I32>; -defm V_FFBL_B32 : VOP1Inst , "v_ffbl_b32", VOP_I32_I32>; -defm V_FFBH_I32 : VOP1Inst , "v_ffbh_i32", VOP_I32_I32>; +defm V_NOT_B32 : VOP1Inst , "v_not_b32", VOP_I32_I32>; +defm V_BFREV_B32 : VOP1Inst , "v_bfrev_b32", VOP_I32_I32>; +defm V_FFBH_U32 : VOP1Inst , "v_ffbh_u32", VOP_I32_I32>; +defm V_FFBL_B32 : VOP1Inst , "v_ffbl_b32", VOP_I32_I32>; +defm V_FFBH_I32 : VOP1Inst , "v_ffbh_i32", VOP_I32_I32>; //defm V_FREXP_EXP_I32_F64 : VOPInst <0x0000003c, "v_frexp_exp_i32_f64", VOP_I32_F32>; -defm V_FREXP_MANT_F64 : VOP1Inst , "v_frexp_mant_f64", VOP_F64_F64>; -defm V_FRACT_F64 : VOP1Inst , "v_fract_f64", VOP_F64_F64>; +defm V_FREXP_MANT_F64 : VOP1Inst , "v_frexp_mant_f64", + VOP_F64_F64 +>; +defm V_FRACT_F64 : VOP1Inst , "v_fract_f64", VOP_F64_F64>; //defm V_FREXP_EXP_I32_F32 : VOPInst <0x0000003f, "v_frexp_exp_i32_f32", VOP_I32_F32>; -defm V_FREXP_MANT_F32 : VOP1Inst , "v_frexp_mant_f32", VOP_F32_F32>; +defm V_FREXP_MANT_F32 : VOP1Inst , "v_frexp_mant_f32", + VOP_F32_F32 +>; //def V_CLREXCP : VOP1_ <0x00000041, "v_clrexcp", []>; -defm V_MOVRELD_B32 : VOP1Inst , "v_movreld_b32", VOP_I32_I32>; -defm V_MOVRELS_B32 : VOP1Inst , "v_movrels_b32", VOP_I32_I32>; -defm V_MOVRELSD_B32 : VOP1Inst , "v_movrelsd_b32", VOP_I32_I32>; +defm V_MOVRELD_B32 : VOP1Inst , "v_movreld_b32", VOP_I32_I32>; +defm V_MOVRELS_B32 : VOP1Inst , "v_movrels_b32", VOP_I32_I32>; +defm V_MOVRELSD_B32 : VOP1Inst , "v_movrelsd_b32", VOP_I32_I32>; +// These instruction only exist on SI and CI +let SubtargetPredicate = isSICI in { + +defm V_LOG_CLAMP_F32 : VOP1InstSI , "v_log_clamp_f32", VOP_F32_F32>; +defm V_RCP_CLAMP_F32 : VOP1InstSI , "v_rcp_clamp_f32", VOP_F32_F32>; +defm V_RCP_LEGACY_F32 : VOP1InstSI , "v_rcp_legacy_f32", VOP_F32_F32>; +defm V_RSQ_CLAMP_F32 : VOP1InstSI , "v_rsq_clamp_f32", + VOP_F32_F32, AMDGPUrsq_clamped +>; +defm V_RSQ_LEGACY_F32 : VOP1InstSI , "v_rsq_legacy_f32", + VOP_F32_F32, AMDGPUrsq_legacy +>; +defm V_RCP_CLAMP_F64 : VOP1InstSI , "v_rcp_clamp_f64", VOP_F64_F64>; +defm V_RSQ_CLAMP_F64 : VOP1InstSI , "v_rsq_clamp_f64", + VOP_F64_F64, AMDGPUrsq_clamped +>; + +} // End SubtargetPredicate = isSICI //===----------------------------------------------------------------------===// // VINTRP Instructions //===----------------------------------------------------------------------===// -def V_INTERP_P1_F32 : VINTRP < - 0x00000000, +defm V_INTERP_P1_F32 : VINTRP_m < + 0x00000000, "v_interp_p1_f32", (outs VReg_32:$dst), (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), "v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [$m0]", - []> { - let DisableEncoding = "$m0"; -} + "$m0">; -def V_INTERP_P2_F32 : VINTRP < - 0x00000001, +defm V_INTERP_P2_F32 : VINTRP_m < + 0x00000001, "v_interp_p2_f32", (outs VReg_32:$dst), (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]", - []> { + "$src0,$m0", + "$src0 = $dst">; - let Constraints = "$src0 = $dst"; - let DisableEncoding = "$src0,$m0"; - -} - -def V_INTERP_MOV_F32 : VINTRP < - 0x00000002, +defm V_INTERP_MOV_F32 : VINTRP_m < + 0x00000002, "v_interp_mov_f32", (outs VReg_32:$dst), (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), "v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [$m0]", - []> { - let DisableEncoding = "$m0"; -} + "$m0">; //===----------------------------------------------------------------------===// // VOP2 Instructions //===----------------------------------------------------------------------===// -def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst), - (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc), - "v_cndmask_b32_e32 $dst, $src0, $src1, [$vcc]", - [] ->{ - let DisableEncoding = "$vcc"; -} - -def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst), +defm V_CNDMASK_B32_e64 : VOP3_m_nosrcmod , (outs VReg_32:$dst), (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2), "v_cndmask_b32_e64 $dst, $src0, $src1, $src2", - [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))] -> { - let src0_modifiers = 0; - let src1_modifiers = 0; - let src2_modifiers = 0; -} - -def V_READLANE_B32 : VOP2 < - 0x00000001, - (outs SReg_32:$vdst), - (ins VReg_32:$src0, SSrc_32:$vsrc1), - "v_readlane_b32 $vdst, $src0, $vsrc1", - [] + [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))], + "v_cndmask_b32_e64", 3 >; -def V_WRITELANE_B32 : VOP2 < - 0x00000002, - (outs VReg_32:$vdst), - (ins SReg_32:$src0, SSrc_32:$vsrc1), - "v_writelane_b32 $vdst, $src0, $vsrc1", - [] ->; let isCommutable = 1 in { -defm V_ADD_F32 : VOP2Inst , "v_add_f32", +defm V_ADD_F32 : VOP2Inst , "v_add_f32", VOP_F32_F32_F32, fadd >; -defm V_SUB_F32 : VOP2Inst , "v_sub_f32", VOP_F32_F32_F32, fsub>; -defm V_SUBREV_F32 : VOP2Inst , "v_subrev_f32", +defm V_SUB_F32 : VOP2Inst , "v_sub_f32", VOP_F32_F32_F32, fsub>; +defm V_SUBREV_F32 : VOP2Inst , "v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32" >; } // End isCommutable = 1 let isCommutable = 1 in { -defm V_MAC_LEGACY_F32 : VOP2Inst , "v_mac_legacy_f32", - VOP_F32_F32_F32 ->; - -defm V_MUL_LEGACY_F32 : VOP2Inst , "v_mul_legacy_f32", +defm V_MUL_LEGACY_F32 : VOP2Inst , "v_mul_legacy_f32", VOP_F32_F32_F32, int_AMDGPU_mul >; -defm V_MUL_F32 : VOP2Inst , "v_mul_f32", +defm V_MUL_F32 : VOP2Inst , "v_mul_f32", VOP_F32_F32_F32, fmul >; -defm V_MUL_I32_I24 : VOP2Inst , "v_mul_i32_i24", +defm V_MUL_I32_I24 : VOP2Inst , "v_mul_i32_i24", VOP_I32_I32_I32, AMDGPUmul_i24 >; //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "v_mul_hi_i32_i24", []>; -defm V_MUL_U32_U24 : VOP2Inst , "v_mul_u32_u24", +defm V_MUL_U32_U24 : VOP2Inst , "v_mul_u32_u24", VOP_I32_I32_I32, AMDGPUmul_u24 >; //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "v_mul_hi_u32_u24", []>; - -defm V_MIN_LEGACY_F32 : VOP2Inst , "v_min_legacy_f32", - VOP_F32_F32_F32, AMDGPUfmin_legacy +defm V_MIN_F32 : VOP2Inst , "v_min_f32", VOP_F32_F32_F32, + fminnum>; +defm V_MAX_F32 : VOP2Inst , "v_max_f32", VOP_F32_F32_F32, + fmaxnum>; +defm V_MIN_I32 : VOP2Inst , "v_min_i32", VOP_I32_I32_I32, + AMDGPUsmin >; - -defm V_MAX_LEGACY_F32 : VOP2Inst , "v_max_legacy_f32", - VOP_F32_F32_F32, AMDGPUfmax_legacy +defm V_MAX_I32 : VOP2Inst , "v_max_i32", VOP_I32_I32_I32, + AMDGPUsmax +>; +defm V_MIN_U32 : VOP2Inst , "v_min_u32", VOP_I32_I32_I32, + AMDGPUumin +>; +defm V_MAX_U32 : VOP2Inst , "v_max_u32", VOP_I32_I32_I32, + AMDGPUumax >; -defm V_MIN_F32 : VOP2Inst , "v_min_f32", VOP_F32_F32_F32, fminnum>; -defm V_MAX_F32 : VOP2Inst , "v_max_f32", VOP_F32_F32_F32, fmaxnum>; -defm V_MIN_I32 : VOP2Inst , "v_min_i32", VOP_I32_I32_I32, AMDGPUsmin>; -defm V_MAX_I32 : VOP2Inst , "v_max_i32", VOP_I32_I32_I32, AMDGPUsmax>; -defm V_MIN_U32 : VOP2Inst , "v_min_u32", VOP_I32_I32_I32, AMDGPUumin>; -defm V_MAX_U32 : VOP2Inst , "v_max_u32", VOP_I32_I32_I32, AMDGPUumax>; - -defm V_LSHR_B32 : VOP2Inst , "v_lshr_b32", VOP_I32_I32_I32, srl>; - +// No non-Rev Op on VI defm V_LSHRREV_B32 : VOP2Inst < - vop2<0x16>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag, "v_lshr_b32" + vop2<0x16, 0x10>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag, + "v_lshr_b32", "v_lshrrev_b32" >; -defm V_ASHR_I32 : VOP2Inst , "v_ashr_i32", - VOP_I32_I32_I32, sra ->; +// No non-Rev OP on VI defm V_ASHRREV_I32 : VOP2Inst < - vop2<0x18>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag, "v_ashr_i32" + vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag, + "v_ashr_i32", "v_ashrrev_i32" >; -let hasPostISelHook = 1 in { - -defm V_LSHL_B32 : VOP2Inst , "v_lshl_b32", VOP_I32_I32_I32, shl>; - -} +// No non-Rev OP on VI defm V_LSHLREV_B32 : VOP2Inst < - vop2<0x1a>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag, "v_lshl_b32" + vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag, + "v_lshl_b32", "v_lshlrev_b32" >; -defm V_AND_B32 : VOP2Inst , "v_and_b32", +defm V_AND_B32 : VOP2Inst , "v_and_b32", VOP_I32_I32_I32, and>; -defm V_OR_B32 : VOP2Inst , "v_or_b32", +defm V_OR_B32 : VOP2Inst , "v_or_b32", VOP_I32_I32_I32, or >; -defm V_XOR_B32 : VOP2Inst , "v_xor_b32", +defm V_XOR_B32 : VOP2Inst , "v_xor_b32", VOP_I32_I32_I32, xor >; +defm V_MAC_F32 : VOP2Inst , "v_mac_f32", VOP_F32_F32_F32>; } // End isCommutable = 1 -defm V_BFM_B32 : VOP2Inst , "v_bfm_b32", - VOP_I32_I32_I32, AMDGPUbfm>; +defm V_MADMK_F32 : VOP2Inst , "v_madmk_f32", VOP_F32_F32_F32>; let isCommutable = 1 in { -defm V_MAC_F32 : VOP2Inst , "v_mac_f32", VOP_F32_F32_F32>; +defm V_MADAK_F32 : VOP2Inst , "v_madak_f32", VOP_F32_F32_F32>; } // End isCommutable = 1 -defm V_MADMK_F32 : VOP2Inst , "v_madmk_f32", VOP_F32_F32_F32>; - -let isCommutable = 1 in { -defm V_MADAK_F32 : VOP2Inst , "v_madak_f32", VOP_F32_F32_F32>; -} // End isCommutable = 1 - - -defm V_BCNT_U32_B32 : VOP2Inst , "v_bcnt_u32_b32", VOP_I32_I32_I32>; -defm V_MBCNT_LO_U32_B32 : VOP2Inst , "v_mbcnt_lo_u32_b32", - - VOP_I32_I32_I32 ->; -defm V_MBCNT_HI_U32_B32 : VOP2Inst , "v_mbcnt_hi_u32_b32", - VOP_I32_I32_I32 ->; - let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC // No patterns so that the scalar instructions are always selected. // The scalar versions will be replaced with vector when needed later. -defm V_ADD_I32 : VOP2bInst , "v_add_i32", + +// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI, +// but the VI instructions behave the same as the SI versions. +defm V_ADD_I32 : VOP2bInst , "v_add_i32", VOP_I32_I32_I32, add >; -defm V_SUB_I32 : VOP2bInst , "v_sub_i32", +defm V_SUB_I32 : VOP2bInst , "v_sub_i32", VOP_I32_I32_I32, sub >; -defm V_SUBREV_I32 : VOP2bInst , "v_subrev_i32", + +defm V_SUBREV_I32 : VOP2bInst , "v_subrev_i32", VOP_I32_I32_I32, null_frag, "v_sub_i32" >; let Uses = [VCC] in { // Carry-in comes from VCC -defm V_ADDC_U32 : VOP2bInst , "v_addc_u32", +defm V_ADDC_U32 : VOP2bInst , "v_addc_u32", VOP_I32_I32_I32_VCC, adde >; -defm V_SUBB_U32 : VOP2bInst , "v_subb_u32", +defm V_SUBB_U32 : VOP2bInst , "v_subb_u32", VOP_I32_I32_I32_VCC, sube >; -defm V_SUBBREV_U32 : VOP2bInst , "v_subbrev_u32", +defm V_SUBBREV_U32 : VOP2bInst , "v_subbrev_u32", VOP_I32_I32_I32_VCC, null_frag, "v_subb_u32" >; } // End Uses = [VCC] } // End isCommutable = 1, Defs = [VCC] +// These instructions only exist on SI and CI +let SubtargetPredicate = isSICI in { + +def V_READLANE_B32 : VOP2 < + 0x00000001, + (outs SReg_32:$vdst), + (ins VReg_32:$src0, SSrc_32:$vsrc1), + "v_readlane_b32 $vdst, $src0, $vsrc1", + [] +>; + +def V_WRITELANE_B32 : VOP2 < + 0x00000002, + (outs VReg_32:$vdst), + (ins SReg_32:$src0, SSrc_32:$vsrc1), + "v_writelane_b32 $vdst, $src0, $vsrc1", + [] +>; + +let isCommutable = 1 in { +defm V_MAC_LEGACY_F32 : VOP2Inst , "v_mac_legacy_f32", + VOP_F32_F32_F32 +>; + +defm V_MIN_LEGACY_F32 : VOP2Inst , "v_min_legacy_f32", + VOP_F32_F32_F32, AMDGPUfmin_legacy +>; +defm V_MAX_LEGACY_F32 : VOP2Inst , "v_max_legacy_f32", + VOP_F32_F32_F32, AMDGPUfmax_legacy +>; + +defm V_LSHR_B32 : VOP2Inst , "v_lshr_b32", VOP_I32_I32_I32, srl>; +defm V_ASHR_I32 : VOP2Inst , "v_ashr_i32", + VOP_I32_I32_I32, sra +>; + +let hasPostISelHook = 1 in { +defm V_LSHL_B32 : VOP2Inst , "v_lshl_b32", VOP_I32_I32_I32, shl>; +} + +} // End isCommutable = 1 + +defm V_BFM_B32 : VOP2Inst , "v_bfm_b32", VOP_I32_I32_I32, + AMDGPUbfm>; +defm V_BCNT_U32_B32 : VOP2Inst , "v_bcnt_u32_b32", VOP_I32_I32_I32>; +defm V_MBCNT_LO_U32_B32 : VOP2Inst , "v_mbcnt_lo_u32_b32", + VOP_I32_I32_I32 +>; +defm V_MBCNT_HI_U32_B32 : VOP2Inst , "v_mbcnt_hi_u32_b32", + VOP_I32_I32_I32 +>; defm V_LDEXP_F32 : VOP2Inst , "v_ldexp_f32", VOP_F32_F32_I32, AMDGPUldexp >; + ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "v_cvt_pkaccum_u8_f32", []>; ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "v_cvt_pknorm_i16_f32", []>; ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "v_cvt_pknorm_u16_f32", []>; @@ -1537,65 +1552,72 @@ defm V_CVT_PKRTZ_F16_F32 : VOP2Inst , "v_cvt_pkrtz_f16_f32", ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "v_cvt_pk_u16_u32", []>; ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "v_cvt_pk_i16_i32", []>; +} // End let SubtargetPredicate = SICI //===----------------------------------------------------------------------===// // VOP3 Instructions //===----------------------------------------------------------------------===// let isCommutable = 1 in { -defm V_MAD_LEGACY_F32 : VOP3Inst , "v_mad_legacy_f32", +defm V_MAD_LEGACY_F32 : VOP3Inst , "v_mad_legacy_f32", VOP_F32_F32_F32_F32 >; -defm V_MAD_F32 : VOP3Inst , "v_mad_f32", +defm V_MAD_F32 : VOP3Inst , "v_mad_f32", VOP_F32_F32_F32_F32, fmad >; -defm V_MAD_I32_I24 : VOP3Inst , "v_mad_i32_i24", +defm V_MAD_I32_I24 : VOP3Inst , "v_mad_i32_i24", VOP_I32_I32_I32_I32, AMDGPUmad_i24 >; -defm V_MAD_U32_U24 : VOP3Inst , "v_mad_u32_u24", +defm V_MAD_U32_U24 : VOP3Inst , "v_mad_u32_u24", VOP_I32_I32_I32_I32, AMDGPUmad_u24 >; } // End isCommutable = 1 -defm V_CUBEID_F32 : VOP3Inst , "v_cubeid_f32", +defm V_CUBEID_F32 : VOP3Inst , "v_cubeid_f32", VOP_F32_F32_F32_F32 >; -defm V_CUBESC_F32 : VOP3Inst , "v_cubesc_f32", +defm V_CUBESC_F32 : VOP3Inst , "v_cubesc_f32", VOP_F32_F32_F32_F32 >; -defm V_CUBETC_F32 : VOP3Inst , "v_cubetc_f32", +defm V_CUBETC_F32 : VOP3Inst , "v_cubetc_f32", VOP_F32_F32_F32_F32 >; -defm V_CUBEMA_F32 : VOP3Inst , "v_cubema_f32", +defm V_CUBEMA_F32 : VOP3Inst , "v_cubema_f32", VOP_F32_F32_F32_F32 >; -defm V_BFE_U32 : VOP3Inst , "v_bfe_u32", + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +defm V_BFE_U32 : VOP3Inst , "v_bfe_u32", VOP_I32_I32_I32_I32, AMDGPUbfe_u32 >; -defm V_BFE_I32 : VOP3Inst , "v_bfe_i32", +defm V_BFE_I32 : VOP3Inst , "v_bfe_i32", VOP_I32_I32_I32_I32, AMDGPUbfe_i32 >; -defm V_BFI_B32 : VOP3Inst , "v_bfi_b32", +} + +defm V_BFI_B32 : VOP3Inst , "v_bfi_b32", VOP_I32_I32_I32_I32, AMDGPUbfi >; let isCommutable = 1 in { -defm V_FMA_F32 : VOP3Inst , "v_fma_f32", +defm V_FMA_F32 : VOP3Inst , "v_fma_f32", VOP_F32_F32_F32_F32, fma >; -defm V_FMA_F64 : VOP3Inst , "v_fma_f64", +defm V_FMA_F64 : VOP3Inst , "v_fma_f64", VOP_F64_F64_F64_F64, fma >; } // End isCommutable = 1 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "v_lerp_u8", []>; -defm V_ALIGNBIT_B32 : VOP3Inst , "v_alignbit_b32", +defm V_ALIGNBIT_B32 : VOP3Inst , "v_alignbit_b32", VOP_I32_I32_I32_I32 >; -defm V_ALIGNBYTE_B32 : VOP3Inst , "v_alignbyte_b32", +defm V_ALIGNBYTE_B32 : VOP3Inst , "v_alignbyte_b32", VOP_I32_I32_I32_I32 >; + +// Only on SI defm V_MULLIT_F32 : VOP3Inst , "v_mullit_f32", VOP_F32_F32_F32_F32>; defm V_MIN3_F32 : VOP3Inst , "v_min3_f32", @@ -1622,76 +1644,82 @@ defm V_MAX3_U32 : VOP3Inst , "v_max3_u32", //def V_SAD_U8 : VOP3_U8 <0x0000015a, "v_sad_u8", []>; //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "v_sad_hi_u8", []>; //def V_SAD_U16 : VOP3_U16 <0x0000015c, "v_sad_u16", []>; -defm V_SAD_U32 : VOP3Inst , "v_sad_u32", +defm V_SAD_U32 : VOP3Inst , "v_sad_u32", VOP_I32_I32_I32_I32 >; ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "v_cvt_pk_u8_f32", []>; defm V_DIV_FIXUP_F32 : VOP3Inst < - vop3<0x15f>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup + vop3<0x15f, 0x1de>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup >; defm V_DIV_FIXUP_F64 : VOP3Inst < - vop3<0x160>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup + vop3<0x160, 0x1df>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup >; +// Only on SI defm V_LSHL_B64 : VOP3Inst , "v_lshl_b64", VOP_I64_I64_I32, shl >; + +// Only on SI defm V_LSHR_B64 : VOP3Inst , "v_lshr_b64", VOP_I64_I64_I32, srl >; + +// Only on SI defm V_ASHR_I64 : VOP3Inst , "v_ashr_i64", VOP_I64_I64_I32, sra >; let isCommutable = 1 in { -defm V_ADD_F64 : VOP3Inst , "v_add_f64", +defm V_ADD_F64 : VOP3Inst , "v_add_f64", VOP_F64_F64_F64, fadd >; -defm V_MUL_F64 : VOP3Inst , "v_mul_f64", +defm V_MUL_F64 : VOP3Inst , "v_mul_f64", VOP_F64_F64_F64, fmul >; -defm V_MIN_F64 : VOP3Inst , "v_min_f64", +defm V_MIN_F64 : VOP3Inst , "v_min_f64", VOP_F64_F64_F64, fminnum >; -defm V_MAX_F64 : VOP3Inst , "v_max_f64", +defm V_MAX_F64 : VOP3Inst , "v_max_f64", VOP_F64_F64_F64, fmaxnum >; } // isCommutable = 1 -defm V_LDEXP_F64 : VOP3Inst , "v_ldexp_f64", +defm V_LDEXP_F64 : VOP3Inst , "v_ldexp_f64", VOP_F64_F64_I32, AMDGPUldexp >; let isCommutable = 1 in { -defm V_MUL_LO_U32 : VOP3Inst , "v_mul_lo_u32", +defm V_MUL_LO_U32 : VOP3Inst , "v_mul_lo_u32", VOP_I32_I32_I32 >; -defm V_MUL_HI_U32 : VOP3Inst , "v_mul_hi_u32", +defm V_MUL_HI_U32 : VOP3Inst , "v_mul_hi_u32", VOP_I32_I32_I32 >; -defm V_MUL_LO_I32 : VOP3Inst , "v_mul_lo_i32", + +defm V_MUL_LO_I32 : VOP3Inst , "v_mul_lo_i32", VOP_I32_I32_I32 >; -defm V_MUL_HI_I32 : VOP3Inst , "v_mul_hi_i32", +defm V_MUL_HI_I32 : VOP3Inst , "v_mul_hi_i32", VOP_I32_I32_I32 >; } // isCommutable = 1 -defm V_DIV_SCALE_F32 : VOP3b_32 , "v_div_scale_f32", []>; +defm V_DIV_SCALE_F32 : VOP3b_32 , "v_div_scale_f32", []>; // Double precision division pre-scale. -defm V_DIV_SCALE_F64 : VOP3b_64 , "v_div_scale_f64", []>; +defm V_DIV_SCALE_F64 : VOP3b_64 , "v_div_scale_f64", []>; let isCommutable = 1 in { -defm V_DIV_FMAS_F32 : VOP3Inst , "v_div_fmas_f32", +defm V_DIV_FMAS_F32 : VOP3Inst , "v_div_fmas_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fmas >; -defm V_DIV_FMAS_F64 : VOP3Inst , "v_div_fmas_f64", +defm V_DIV_FMAS_F64 : VOP3Inst , "v_div_fmas_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fmas >; } // End isCommutable = 1 @@ -1701,7 +1729,7 @@ defm V_DIV_FMAS_F64 : VOP3Inst , "v_div_fmas_f64", //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "v_mqsad_u8", []>; defm V_TRIG_PREOP_F64 : VOP3Inst < - vop3<0x174>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop + vop3<0x174, 0x292>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop >; //===----------------------------------------------------------------------===// @@ -1906,9 +1934,9 @@ def SI_CONSTDATA_PTR : InstSI < } // end IsCodeGenOnly, isPseudo -} // end SubtargetPredicate = SI +} // end SubtargetPredicate = isGCN -let Predicates = [isSI] in { +let Predicates = [isGCN] in { def : Pat< (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2), @@ -1922,12 +1950,16 @@ def : Pat < (SI_KILL 0xbf800000) >; +let Predicates = [isSICI] in { + /* int_SI_vs_load_input */ def : Pat< (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr), (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0) >; +} // End Predicates = [isSICI] + /* int_SI_export */ def : Pat < (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, @@ -1981,8 +2013,6 @@ def : Pat < (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset)) >; -} // Predicates = [isSI] in { - //===----------------------------------------------------------------------===// // SOP1 Patterns //===----------------------------------------------------------------------===// @@ -2005,8 +2035,6 @@ def : Pat < (S_ADD_U32 $src0, $src1) >; -let Predicates = [isSI] in { - //===----------------------------------------------------------------------===// // SOPP Patterns //===----------------------------------------------------------------------===// @@ -2576,12 +2604,16 @@ class Ext32Pat : Pat < def : Ext32Pat ; def : Ext32Pat ; +let Predicates = [isSICI] in { + // Offset in an 32Bit VGPR def : Pat < (SIload_constant v4i32:$sbase, i32:$voff), (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0, 0) >; +} // End Predicates = [isSICI] + // The multiplication scales from [0,1] to the unsigned integer range def : Pat < (AMDGPUurecip i32:$src0), @@ -2590,12 +2622,16 @@ def : Pat < (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0)))) >; +let Predicates = [isSICI] in { + def : Pat < (int_SI_tid), (V_MBCNT_HI_U32_B32_e32 0xffffffff, (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0)) >; +} + //===----------------------------------------------------------------------===// // VOP3 Patterns //===----------------------------------------------------------------------===// @@ -2747,6 +2783,7 @@ multiclass MUBUFLoad_Pattern ; } +let Predicates = [isSICI] in { defm : MUBUFLoad_Pattern ; defm : MUBUFLoad_Pattern ; defm : MUBUFLoad_Pattern ; @@ -2754,6 +2791,7 @@ defm : MUBUFLoad_Pattern ; defm : MUBUFLoad_Pattern ; defm : MUBUFLoad_Pattern ; +} // End Predicates = [isSICI] class MUBUFScratchLoadPat : Pat < (vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr, @@ -2761,6 +2799,7 @@ class MUBUFScratchLoadPat : Pat < (Instr $srsrc, $vaddr, $soffset, $offset, 0, 0, 0) >; +let Predicates = [isSICI] in { def : MUBUFScratchLoadPat ; def : MUBUFScratchLoadPat ; def : MUBUFScratchLoadPat ; @@ -2768,6 +2807,7 @@ def : MUBUFScratchLoadPat ; def : MUBUFScratchLoadPat ; def : MUBUFScratchLoadPat ; def : MUBUFScratchLoadPat ; +} // End Predicates = [isSICI] // BUFFER_LOAD_DWORD*, addr64=0 multiclass MUBUF_Load_Dword ; } +let Predicates = [isSICI] in { defm : MUBUF_Load_Dword ; defm : MUBUF_Load_Dword ; defm : MUBUF_Load_Dword ; +} // End Predicates = [isSICI] class MUBUFScratchStorePat : Pat < (st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset, @@ -2819,11 +2861,13 @@ class MUBUFScratchStorePat : Pat < (Instr $value, $srsrc, $vaddr, $soffset, $offset, 0, 0, 0) >; +let Predicates = [isSICI] in { def : MUBUFScratchStorePat ; def : MUBUFScratchStorePat ; def : MUBUFScratchStorePat ; def : MUBUFScratchStorePat ; def : MUBUFScratchStorePat ; +} // End Predicates = [isSICI] /* class MUBUFStore_Pattern : Pat < @@ -2831,11 +2875,13 @@ class MUBUFStore_Pattern : Pat < (Instr $value, $srsrc, $vaddr, $offset) >; +let Predicates = [isSICI] in { def : MUBUFStore_Pattern ; def : MUBUFStore_Pattern ; def : MUBUFStore_Pattern ; def : MUBUFStore_Pattern ; def : MUBUFStore_Pattern ; +} // End Predicates = [isSICI] */ @@ -2862,20 +2908,6 @@ def : MTBUF_StoreResource ; let SubtargetPredicate = isCI in { -// Sea island new arithmetic instructinos -defm V_TRUNC_F64 : VOP1Inst , "v_trunc_f64", - VOP_F64_F64, ftrunc ->; -defm V_CEIL_F64 : VOP1Inst , "v_ceil_f64", - VOP_F64_F64, fceil ->; -defm V_FLOOR_F64 : VOP1Inst , "v_floor_f64", - VOP_F64_F64, ffloor ->; -defm V_RNDNE_F64 : VOP1Inst , "v_rndne_f64", - VOP_F64_F64, frint ->; - defm V_QSAD_PK_U16_U8 : VOP3Inst , "v_qsad_pk_u16_u8", VOP_I32_I32_I32 >; @@ -2904,8 +2936,6 @@ defm V_MAD_I64_I32 : VOP3Inst , "v_mad_i64_i32", // S_CBRANCH_CDBGSYS_OR_USER // S_CBRANCH_CDBGSYS_AND_USER // S_DCACHE_INV_VOL -// V_EXP_LEGACY_F32 -// V_LOG_LEGACY_F32 // DS_NOP // DS_GWS_SEMA_RELEASE_ALL // DS_WRAP_RTN_B32 @@ -2918,7 +2948,7 @@ defm V_MAD_I64_I32 : VOP3Inst , "v_mad_i64_i32", // BUFFER_LOAD_DWORDX3 // BUFFER_STORE_DWORDX3 -} // End iSCI +} // End isCI //===----------------------------------------------------------------------===// // Flat Patterns @@ -3120,4 +3150,4 @@ def : Pat < def : SHA256MaPattern ; -} // End isSI predicate +} // End isGCN predicate diff --git a/lib/Target/R600/VIInstrFormats.td b/lib/Target/R600/VIInstrFormats.td new file mode 100644 index 00000000000..5285d18ced4 --- /dev/null +++ b/lib/Target/R600/VIInstrFormats.td @@ -0,0 +1,145 @@ +//===-- VIInstrFormats.td - VI Instruction Encodings ----------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// VI Instruction format definitions. +// +//===----------------------------------------------------------------------===// + +class DSe_vi op> : Enc64 { + + bits<8> vdst; + bits<1> gds; + bits<8> addr; + bits<8> data0; + bits<8> data1; + bits<8> offset0; + bits<8> offset1; + + let Inst{7-0} = offset0; + let Inst{15-8} = offset1; + let Inst{16} = gds; + let Inst{24-17} = op; + let Inst{31-26} = 0x36; //encoding + let Inst{39-32} = addr; + let Inst{47-40} = data0; + let Inst{55-48} = data1; + let Inst{63-56} = vdst; +} + +class MUBUFe_vi op> : Enc64 { + + bits<12> offset; + bits<1> offen; + bits<1> idxen; + bits<1> glc; + bits<1> lds; + bits<8> vaddr; + bits<8> vdata; + bits<7> srsrc; + bits<1> slc; + bits<1> tfe; + bits<8> soffset; + + let Inst{11-0} = offset; + let Inst{12} = offen; + let Inst{13} = idxen; + let Inst{14} = glc; + let Inst{16} = lds; + let Inst{17} = slc; + let Inst{24-18} = op; + let Inst{31-26} = 0x38; //encoding + let Inst{39-32} = vaddr; + let Inst{47-40} = vdata; + let Inst{52-48} = srsrc{6-2}; + let Inst{55} = tfe; + let Inst{63-56} = soffset; +} + +class MTBUFe_vi op> : Enc64 { + + bits<12> offset; + bits<1> offen; + bits<1> idxen; + bits<1> glc; + bits<4> dfmt; + bits<3> nfmt; + bits<8> vaddr; + bits<8> vdata; + bits<7> srsrc; + bits<1> slc; + bits<1> tfe; + bits<8> soffset; + + let Inst{11-0} = offset; + let Inst{12} = offen; + let Inst{13} = idxen; + let Inst{14} = glc; + let Inst{18-15} = op; + let Inst{22-19} = dfmt; + let Inst{25-23} = nfmt; + let Inst{31-26} = 0x3a; //encoding + let Inst{39-32} = vaddr; + let Inst{47-40} = vdata; + let Inst{52-48} = srsrc{6-2}; + let Inst{54} = slc; + let Inst{55} = tfe; + let Inst{63-56} = soffset; +} + +class SMEMe_vi op, bit imm> : Enc64 { + + bits<7> sbase; + bits<7> sdata; + bits<1> glc; + bits<20> offset; + + let Inst{5-0} = sbase{6-1}; + let Inst{12-6} = sdata; + let Inst{16} = glc; + let Inst{17} = imm; + let Inst{25-18} = op; + let Inst{31-26} = 0x30; //encoding + let Inst{51-32} = offset; +} + +class VOP3e_vi op> : Enc64 { + + bits<8> dst; + bits<2> src0_modifiers; + bits<9> src0; + bits<2> src1_modifiers; + bits<9> src1; + bits<2> src2_modifiers; + bits<9> src2; + bits<1> clamp; + bits<2> omod; + + let Inst{7-0} = dst; + let Inst{8} = src0_modifiers{1}; + let Inst{9} = src1_modifiers{1}; + let Inst{10} = src2_modifiers{1}; + let Inst{15} = clamp; + let Inst{25-16} = op; + let Inst{31-26} = 0x34; //encoding + let Inst{40-32} = src0; + let Inst{49-41} = src1; + let Inst{58-50} = src2; + let Inst{60-59} = omod; + let Inst{61} = src0_modifiers{0}; + let Inst{62} = src1_modifiers{0}; + let Inst{63} = src2_modifiers{0}; +} + +class EXPe_vi : EXPe { + let Inst{31-26} = 0x31; //encoding +} + +class VINTRPe_vi op> : VINTRPe { + let Inst{31-26} = 0x35; // encoding +} diff --git a/lib/Target/R600/VIInstructions.td b/lib/Target/R600/VIInstructions.td new file mode 100644 index 00000000000..9fc46fbf136 --- /dev/null +++ b/lib/Target/R600/VIInstructions.td @@ -0,0 +1,83 @@ +//===-- VIInstructions.td - VI Instruction Defintions ---------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// Instruction definitions for VI and newer. +//===----------------------------------------------------------------------===// + +def isVI : Predicate < + "Subtarget.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS" +>; + +let SubtargetPredicate = isVI in { + +def V_LDEXP_F32 : VOP3InstVI <0x288, "v_ldexp_f32", VOP_F32_F32_I32, + AMDGPUldexp +>; +def V_BFM_B32 : VOP3InstVI <0x293, "v_bfm_b32", VOP_I32_I32_I32, AMDGPUbfm>; +def V_BCNT_U32_B32 : VOP3InstVI <0x28b, "v_bcnt_u32_b32", VOP_I32_I32_I32>; +def V_MBCNT_LO_U32_B32 : VOP3InstVI <0x28c, "v_mbcnt_lo_u32_b32", + VOP_I32_I32_I32 +>; +def V_MBCNT_HI_U32_B32 : VOP3InstVI <0x28d, "v_mbcnt_hi_u32_b32", + VOP_I32_I32_I32 +>; + +def V_CVT_PKRTZ_F16_F32 : VOP3InstVI <0x296, "v_cvt_pkrtz_f16_f32", + VOP_I32_F32_F32, int_SI_packf16 +>; + +defm BUFFER_LOAD_DWORD_VI : MUBUF_Load_Helper_vi < + 0x14, "buffer_load_dword", VReg_32, i32, global_load +>; + +defm BUFFER_LOAD_FORMAT_XYZW_VI : MUBUF_Load_Helper_vi < + 0x03, "buffer_load_format_xyzw", VReg_128 +>; + +} // End SubtargetPredicate = isVI + +//===----------------------------------------------------------------------===// +// VOP2 Patterns +//===----------------------------------------------------------------------===// + +let Predicates = [isVI] in { + +def : Pat < + (int_SI_tid), + (V_MBCNT_HI_U32_B32 0xffffffff, + (V_MBCNT_LO_U32_B32 0xffffffff, 0)) +>; + +//===----------------------------------------------------------------------===// +// MUBUF Patterns +//===----------------------------------------------------------------------===// + +// Offset in an 32Bit VGPR +def : Pat < + (SIload_constant v4i32:$sbase, i32:$voff), + (BUFFER_LOAD_DWORD_VI_OFFEN $sbase, $voff, 0, 0, 0, 0, 0) +>; + +// Offset in an 32Bit VGPR +def : Pat < + (SIload_constant v4i32:$sbase, i32:$voff), + (BUFFER_LOAD_DWORD_VI_OFFEN $sbase, $voff, 0, 0, 0, 0, 0) +>; + +/* int_SI_vs_load_input */ +def : Pat< + (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr), + (BUFFER_LOAD_FORMAT_XYZW_VI_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0) +>; + +defm : MUBUF_Load_Dword ; + +} // End Predicates = [isVI]