From: dkl <dkl@rock-chips.com>
Date: Thu, 11 Dec 2014 06:38:26 +0000 (+0800)
Subject: rk3368: dts: clk: fix some errors
X-Git-Tag: firefly_0821_release~4158^2~535
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=7dfaf7a105a7197c7600f62d8fc0d3b49c5689c0;p=firefly-linux-kernel-4.4.55.git

rk3368: dts: clk: fix some errors

Adjust vip clks, rename clk_gpu_core "clk_gpu" and remove wrong clk4x_ddr.

Signed-off-by: dkl <dkl@rock-chips.com>
---

diff --git a/arch/arm64/boot/dts/rk3368-clocks.dtsi b/arch/arm64/boot/dts/rk3368-clocks.dtsi
index 29b1773791a0..c9ecfefd2755 100644
--- a/arch/arm64/boot/dts/rk3368-clocks.dtsi
+++ b/arch/arm64/boot/dts/rk3368-clocks.dtsi
@@ -689,14 +689,6 @@
 							<CLKOPS_RATE_RK3288_USB480M>;
 						#clock-init-cells = <1>;
 					};
-
-					clk4x_ddr: clk4x_ddr_mux {
-						compatible = "rockchip,rk3188-mux-con";
-						rockchip,bits = <4 1>;
-						clocks = <&clk_dpll>, <&clk_gpll>;
-						clock-output-names = "clk4x_ddr";
-						#clock-cells = <0>;
-					};
 				};
 
 				clk_sel_con14: sel-con@0138 {
@@ -709,7 +701,7 @@
 						compatible = "rockchip,rk3188-div-con";
 						rockchip,bits = <0 5>;
 						clocks = <&clk_gpu_core>;
-						clock-output-names = "clk_gpu_core";
+						clock-output-names = "clk_gpu";
 						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 						#clock-cells = <0>;
 						rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
@@ -722,7 +714,7 @@
 						compatible = "rockchip,rk3188-mux-con";
 						rockchip,bits = <6 2>;
 						clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
-						clock-output-names = "clk_gpu_core";
+						clock-output-names = "clk_gpu";
 						#clock-cells = <0>;
 						#clock-init-cells = <1>;
 					};
@@ -1018,12 +1010,21 @@
 
 					clk_vip: clk_vip_mux {
 						compatible = "rockchip,rk3188-mux-con";
-						rockchip,bits = <14 2>;
-						clocks = <&clk_cpll>, <&xin24m>, <&clk_gpll>, <&xin24m>;
+						rockchip,bits = <14 1>;
+						clocks = <&clk_vip_pll>, <&xin24m>;
 						clock-output-names = "clk_vip";
 						#clock-cells = <0>;
 						#clock-init-cells = <1>;
 					};
+
+					clk_vip_pll: clk_vip_pll_mux {
+						compatible = "rockchip,rk3188-mux-con";
+						rockchip,bits = <15 1>;
+						clocks = <&clk_cpll>, <&clk_gpll>;
+						clock-output-names = "clk_vip_pll";
+						#clock-cells = <0>;
+						#clock-init-cells = <1>;
+					};
 				};
 
 				clk_sel_con22: sel-con@0158 {
@@ -1103,6 +1104,8 @@
 						#clock-cells = <0>;
 					};
 
+					/* 7:6 reserved */
+
 					clk_saradc: clk_saradc_div {
 						compatible = "rockchip,rk3188-div-con";
 						rockchip,bits = <8 8>;
@@ -1374,8 +1377,6 @@
                                                 #clock-cells = <0>;
 						#clock-init-cells = <1>;
                                         };
-
-					/* 14:13 reserved */
 				};
 
 				clk_sel_con36: sel-con@0190 {
@@ -2037,7 +2038,7 @@
                                                 <&aclk_vio0>,	<&dclk_vop0>,
                                                 <&xin24m>,	<&aclk_rga_pre>,
 
-						<&clk_rga>,	<&clk_vip>,
+						<&clk_rga>,	<&clk_vip_pll>,
 						<&aclk_vepu>,	<&aclk_vdpu>,
 
 						<&dummy>,	<&clk_isp>,
@@ -2050,11 +2051,11 @@
                                                 "aclk_vio0",	"dclk_vop0",
                                                 "clk_vop0_pwm",	"aclk_rga_pre",
 
-						"clk_rga",	"clk_vip",
+						"clk_rga",	"clk_vip_pll",
 						"aclk_vepu",	"aclk_vdpu",
 
 						"reserved",	"clk_isp", /* bit8: hclk_vpu */
-						"reserved",	"clk_gpu_core",
+						"reserved",	"clk_gpu",
 
 						"clk_hdmi_cec",	"clk_hdmi_hdcp",
 						"clk_dsiphy_24m",	"reserved";