From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Sun, 23 Aug 2015 15:22:14 +0000 (+0000)
Subject: [DAGCombiner] Fold CONCAT_VECTORS of bitcasted EXTRACT_SUBVECTOR
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=7b7cb4251e43deb536df2e39b221a70f770db354;p=oota-llvm.git

[DAGCombiner] Fold CONCAT_VECTORS of bitcasted EXTRACT_SUBVECTOR

Minor generalization of D12125 - peek through any bitcast to the original vector that we're extracting from.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245814 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index ab3a6631d33..607c3bf2336 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2285,7 +2285,7 @@ SDValue DAGCombiner::visitUDIV(SDNode *N) {
       }
     }
   }
-  
+
   // fold (udiv x, c) -> alternate
   bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
   if (N1C && !TLI.isIntDivCheap(N->getValueType(0), MinSize))
@@ -12270,12 +12270,21 @@ static SDValue combineConcatVectorOfExtracts(SDNode *N, SelectionDAG &DAG) {
 
     // What vector are we extracting the subvector from and at what index?
     SDValue ExtVec = Op.getOperand(0);
+
+    // We want the EVT of the original extraction to correctly scale the
+    // extraction index.
+    EVT ExtVT = ExtVec.getValueType();
+
+    // Peek through any bitcast.
+    while (ExtVec.getOpcode() == ISD::BITCAST)
+      ExtVec = ExtVec.getOperand(0);
+
+    // UNDEF nodes convert to UNDEF shuffle mask values.
     if (ExtVec.getOpcode() == ISD::UNDEF) {
       Mask.append((unsigned)NumOpElts, -1);
       continue;
     }
 
-    EVT ExtVT = ExtVec.getValueType();
     if (!isa<ConstantSDNode>(Op.getOperand(1)))
       return SDValue();
     int ExtIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
diff --git a/test/CodeGen/X86/vector-shuffle-256-v8.ll b/test/CodeGen/X86/vector-shuffle-256-v8.ll
index cd0fe97d003..9e4f0e7822c 100644
--- a/test/CodeGen/X86/vector-shuffle-256-v8.ll
+++ b/test/CodeGen/X86/vector-shuffle-256-v8.ll
@@ -2128,6 +2128,22 @@ define <8 x i32> @concat_v8i32_4567CDEF_bc(<8 x i32> %a0, <8 x i32> %a1) {
   ret <8 x i32> %shuffle32
 }
 
+define <8 x float> @concat_v8f32_4567CDEF_bc(<8 x float> %f0, <8 x float> %f1) {
+; ALL-LABEL: concat_v8f32_4567CDEF_bc:
+; ALL:       # BB#0:
+; ALL-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
+; ALL-NEXT:    retq
+  %a0 = bitcast <8 x float> %f0 to <4 x i64>
+  %a1 = bitcast <8 x float> %f1 to <8 x i32>
+  %a0hi = shufflevector <4 x i64> %a0, <4 x i64> undef, <2 x i32> <i32 2, i32 3>
+  %a1hi = shufflevector <8 x i32> %a1, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+  %bc0hi = bitcast <2 x i64> %a0hi to <2 x i64>
+  %bc1hi = bitcast <4 x i32> %a1hi to <2 x i64>
+  %shuffle64 = shufflevector <2 x i64> %bc0hi, <2 x i64> %bc1hi, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %shuffle32 = bitcast <4 x i64> %shuffle64 to <8 x float>
+  ret <8 x float> %shuffle32
+}
+
 define <8 x i32> @insert_dup_mem_v8i32(i32* %ptr) {
 ; ALL-LABEL: insert_dup_mem_v8i32:
 ; ALL:       # BB#0: