From: Chris Lattner Date: Sat, 22 Nov 2008 19:10:48 +0000 (+0000) Subject: Describe how the JIT maps fields to MachineOperands, patch by X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=7a1527389265ad5444ac1a4a3dd8901c2f20e902;p=oota-llvm.git Describe how the JIT maps fields to MachineOperands, patch by JP Bonn! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59876 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/docs/WritingAnLLVMBackend.html b/docs/WritingAnLLVMBackend.html index 7277b029b7c..f531585fbbe 100644 --- a/docs/WritingAnLLVMBackend.html +++ b/docs/WritingAnLLVMBackend.html @@ -29,6 +29,7 @@
  • Instruction Set
  • @@ -996,6 +997,88 @@ be taken to ensure the values in Sparc.h correspond to the values in SparcInstrInfo.td; that is, SPCC::ICC_NE = 9, SPCC::FCC_U = 23 and so on.)

    + +
    + Instruction Operand Mapping +
    +
    +

    The code generator backend maps instruction operands to fields in +the instruction. Operands are assigned to unbound fields in the instruction in +the order they are defined. Fields are bound when they are assigned a value. +For example, the Sparc target defines the XNORrr instruction as a F3_1 format +instruction having three operands.

    +
    + +
    +def XNORrr  : F3_1<2, 0b000111,
    +                   (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
    +                   "xnor $b, $c, $dst",
    +                   [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
    +
    + +
    +

    The instruction templates in SparcInstrFormats.td show the base class for F3_1 is InstSP.

    +
    + +
    +class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
    +  field bits<32> Inst;
    +  let Namespace = "SP";
    +  bits<2> op;
    +  let Inst{31-30} = op;       
    +  dag OutOperandList = outs;
    +  dag InOperandList = ins;
    +  let AsmString   = asmstr;
    +  let Pattern = pattern;
    +}
    +
    +
    +

    +InstSP leaves the op field unbound. +

    +
    + +
    +class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
    +    : InstSP<outs, ins, asmstr, pattern> {
    +  bits<5> rd;
    +  bits<6> op3;
    +  bits<5> rs1;
    +  let op{1} = 1;   // Op = 2 or 3
    +  let Inst{29-25} = rd;
    +  let Inst{24-19} = op3;
    +  let Inst{18-14} = rs1;
    +}
    +
    +
    +

    +F3 binds the op field and defines the rd, op3, and rs1 fields. F3 format instructions will +bind the operands rd, op3, and rs1 fields. +

    +
    + +
    +class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
    +           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
    +  bits<8> asi = 0; // asi not currently used
    +  bits<5> rs2;
    +  let op         = opVal;
    +  let op3        = op3val;
    +  let Inst{13}   = 0;     // i field = 0
    +  let Inst{12-5} = asi;   // address space identifier
    +  let Inst{4-0}  = rs2;
    +}
    +
    +
    +

    +F3_1 binds the op3 field and defines the rs2 fields. F3_1 format instructions will +bind the operands to the rd, rs1, and rs2 fields. This results in the XNORrr instruction +binding $dst, $b, and $c operands to the rd, rs1, and rs2 fields respectively. +

    +
    + + +
    Implement a subclass of