From: Chad Rosier <mcrosier@codeaurora.org>
Date: Thu, 24 Sep 2015 19:21:42 +0000 (+0000)
Subject: [AArch64] The paired post-increment store instruction has an output register.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=76d7ac2e738ca55ca0be2ebead2e46593f7df804;p=oota-llvm.git

[AArch64] The paired post-increment store instruction has an output register.

The pre- and post-increment version update the base register, but the post-
version was defined incorrectly.  There is no test case as we don't currently
generate these instructions, but I plan on changing that in the near future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248528 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td
index d644f264eb9..39310cb5084 100644
--- a/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/lib/Target/AArch64/AArch64InstrFormats.td
@@ -3253,8 +3253,8 @@ class LoadPairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
 let mayStore = 1, mayLoad = 0 in
 class StorePairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
                        Operand idxtype, string asm>
-    : BaseLoadStorePairPostIdx<opc, V, 0, (outs),
-                             (ins GPR64sp:$wback, regtype:$Rt, regtype:$Rt2,
+    : BaseLoadStorePairPostIdx<opc, V, 0, (outs GPR64sp:$wback),
+                             (ins regtype:$Rt, regtype:$Rt2,
                                   GPR64sp:$Rn, idxtype:$offset),
                              asm>,
       Sched<[WriteAdr, WriteSTP]>;