From: Misha Brukman <brukman+llvm@gmail.com>
Date: Sun, 7 Sep 2003 20:12:52 +0000 (+0000)
Subject: Fixed spelling of `intentionally'.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=737af827e830eb8eeecda42a31d44d284fbe0204;p=oota-llvm.git

Fixed spelling of `intentionally'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8387 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/support/tools/TableGen/TableGen.cpp b/support/tools/TableGen/TableGen.cpp
index 67efdb46c85..971ac9081aa 100644
--- a/support/tools/TableGen/TableGen.cpp
+++ b/support/tools/TableGen/TableGen.cpp
@@ -193,9 +193,9 @@ static unsigned getFirstFixedBitInSequence(std::vector<Record*>::iterator IB,
 }
 
 // ParseMachineCode - Try to split the vector of instructions (which is
-// intentially taken by-copy) in half, narrowing down the possible instructions
-// that we may have found.  Eventually, this list will get pared down to zero or
-// one instruction, in which case we have a match or failure.
+// intentionally taken by-copy) in half, narrowing down the possible
+// instructions that we may have found.  Eventually, this list will get pared
+// down to zero or one instruction, in which case we have a match or failure.
 //
 static Record *ParseMachineCode(std::vector<Record*>::iterator InstsB, 
 				std::vector<Record*>::iterator InstsE,
diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index 67efdb46c85..971ac9081aa 100644
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -193,9 +193,9 @@ static unsigned getFirstFixedBitInSequence(std::vector<Record*>::iterator IB,
 }
 
 // ParseMachineCode - Try to split the vector of instructions (which is
-// intentially taken by-copy) in half, narrowing down the possible instructions
-// that we may have found.  Eventually, this list will get pared down to zero or
-// one instruction, in which case we have a match or failure.
+// intentionally taken by-copy) in half, narrowing down the possible
+// instructions that we may have found.  Eventually, this list will get pared
+// down to zero or one instruction, in which case we have a match or failure.
 //
 static Record *ParseMachineCode(std::vector<Record*>::iterator InstsB, 
 				std::vector<Record*>::iterator InstsE,