From: Xing Zheng Date: Wed, 23 Mar 2016 02:31:56 +0000 (+0800) Subject: clk: rockchip: fix PLL table and add pclk DFLAG for rk3399 X-Git-Tag: firefly_0821_release~3036 X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=6d3b3d984da4a6a78684069c5d07f01357b2acbd;p=firefly-linux-kernel-4.4.55.git clk: rockchip: fix PLL table and add pclk DFLAG for rk3399 Change-Id: Id89c7099b24fdcff967528a3741af2e84fa1a754 Signed-off-by: Xing Zheng --- diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index e6bfb4982a7a..378e972caa2a 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -313,40 +313,41 @@ static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = { } static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = { - RK3399_CPUCLKL_RATE(1800000000, 2, 8, 8), - RK3399_CPUCLKL_RATE(1704000000, 2, 8, 8), - RK3399_CPUCLKL_RATE(1608000000, 2, 7, 7), - RK3399_CPUCLKL_RATE(1512000000, 2, 7, 7), - RK3399_CPUCLKL_RATE(1488000000, 2, 6, 6), - RK3399_CPUCLKL_RATE(1416000000, 2, 6, 6), - RK3399_CPUCLKL_RATE(1200000000, 2, 5, 5), - RK3399_CPUCLKL_RATE(1008000000, 2, 5, 5), - RK3399_CPUCLKL_RATE( 816000000, 2, 4, 4), - RK3399_CPUCLKL_RATE( 696000000, 2, 3, 3), - RK3399_CPUCLKL_RATE( 600000000, 2, 3, 3), - RK3399_CPUCLKL_RATE( 408000000, 2, 2, 2), - RK3399_CPUCLKL_RATE( 312000000, 2, 2, 2), + RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8), + RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8), + RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7), + RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7), + RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6), + RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6), + RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5), + RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5), + RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4), + RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3), + RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3), + RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2), + RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1), }; static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = { - RK3399_CPUCLKB_RATE(2184000000, 2, 11, 11), - RK3399_CPUCLKB_RATE(2088000000, 2, 10, 10), - RK3399_CPUCLKB_RATE(2040000000, 2, 10, 10), - RK3399_CPUCLKB_RATE(1992000000, 2, 9, 9), - RK3399_CPUCLKB_RATE(1896000000, 2, 9, 9), - RK3399_CPUCLKB_RATE(1800000000, 2, 8, 8), - RK3399_CPUCLKB_RATE(1704000000, 2, 8, 8), - RK3399_CPUCLKB_RATE(1608000000, 2, 7, 7), - RK3399_CPUCLKB_RATE(1512000000, 2, 6, 6), - RK3399_CPUCLKB_RATE(1488000000, 2, 5, 5), - RK3399_CPUCLKB_RATE(1416000000, 2, 5, 5), - RK3399_CPUCLKB_RATE(1200000000, 2, 4, 4), - RK3399_CPUCLKB_RATE(1008000000, 2, 4, 4), - RK3399_CPUCLKB_RATE( 816000000, 2, 3, 3), - RK3399_CPUCLKB_RATE( 696000000, 2, 3, 3), - RK3399_CPUCLKB_RATE( 600000000, 2, 2, 2), - RK3399_CPUCLKB_RATE( 408000000, 2, 2, 2), - RK3399_CPUCLKB_RATE( 312000000, 2, 2, 2), + RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11), + RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11), + RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10), + RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10), + RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9), + RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9), + RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8), + RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8), + RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7), + RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7), + RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6), + RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6), + RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5), + RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5), + RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4), + RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3), + RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3), + RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2), + RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1), }; static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { @@ -483,7 +484,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(14), 4, GFLAGS), - DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", 0, + DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY), GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, @@ -800,7 +801,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(14), 8, 2, DFLAGS, RK3399_CLKGATE_CON(5), 3, GFLAGS), - COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", 0, + COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(14), 12, 2, DFLAGS, RK3399_CLKGATE_CON(5), 4, GFLAGS),