From: Misha Brukman <brukman+llvm@gmail.com>
Date: Mon, 2 Dec 2002 21:10:35 +0000 (+0000)
Subject: Fix order of operands on a store from reg to [reg+offset].
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=6877dd3fb05bb7f8fabf907e520c7d3ae0fab341;p=oota-llvm.git

Fix order of operands on a store from reg to [reg+offset].


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4857 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 9b7256f9e64..4ec29710700 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -31,8 +31,8 @@ X86RegisterInfo::storeReg2RegOffset(MachineBasicBlock *MBB,
                                     unsigned ImmOffset, unsigned dataSize)
   const
 {
-  MachineInstr *MI = addRegOffset(BuildMI(X86::MOVrm32, 5).addReg(SrcReg),
-                                  DestReg, ImmOffset);
+  MachineInstr *MI = addRegOffset(BuildMI(X86::MOVrm32, 5),
+                                  DestReg, ImmOffset).addReg(SrcReg);
   return ++(MBB->insert(MBBI, MI));
 }