From: Jim Grosbach Date: Tue, 18 Oct 2011 20:10:47 +0000 (+0000) Subject: ARM vmov assembly parsing for the lane index operand. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=687656c6300138583f2e8e3cdaff6cfeb6261b7f;p=oota-llvm.git ARM vmov assembly parsing for the lane index operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142412 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index a06d4ae22a7..0ae4d216dec 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -4389,40 +4389,40 @@ def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd), // VMOV : Vector Get Lane (move scalar to ARM core register) def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?}, - (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane), - IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]", + (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane), + IIC_VMOVSI, "vmov", "s8", "$R, $V$lane", [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V), imm:$lane))]> { let Inst{21} = lane{2}; let Inst{6-5} = lane{1-0}; } def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1}, - (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane), - IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]", + (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane), + IIC_VMOVSI, "vmov", "s16", "$R, $V$lane", [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V), imm:$lane))]> { let Inst{21} = lane{1}; let Inst{6} = lane{0}; } def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?}, - (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane), - IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]", + (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane), + IIC_VMOVSI, "vmov", "u8", "$R, $V$lane", [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V), imm:$lane))]> { let Inst{21} = lane{2}; let Inst{6-5} = lane{1-0}; } def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1}, - (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane), - IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]", + (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane), + IIC_VMOVSI, "vmov", "u16", "$R, $V$lane", [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V), imm:$lane))]> { let Inst{21} = lane{1}; let Inst{6} = lane{0}; } def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00, - (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane), - IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]", + (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane), + IIC_VMOVSI, "vmov", "32", "$R, $V$lane", [(set GPR:$R, (extractelt (v2i32 DPR:$V), imm:$lane))]> { let Inst{21} = lane{0}; @@ -4464,24 +4464,24 @@ def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2), let Constraints = "$src1 = $V" in { def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V), - (ins DPR:$src1, GPR:$R, nohash_imm:$lane), - IIC_VMOVISL, "vmov", "8", "$V[$lane], $R", + (ins DPR:$src1, GPR:$R, VectorIndex8:$lane), + IIC_VMOVISL, "vmov", "8", "$V$lane, $R", [(set DPR:$V, (vector_insert (v8i8 DPR:$src1), GPR:$R, imm:$lane))]> { let Inst{21} = lane{2}; let Inst{6-5} = lane{1-0}; } def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V), - (ins DPR:$src1, GPR:$R, nohash_imm:$lane), - IIC_VMOVISL, "vmov", "16", "$V[$lane], $R", + (ins DPR:$src1, GPR:$R, VectorIndex16:$lane), + IIC_VMOVISL, "vmov", "16", "$V$lane, $R", [(set DPR:$V, (vector_insert (v4i16 DPR:$src1), GPR:$R, imm:$lane))]> { let Inst{21} = lane{1}; let Inst{6} = lane{0}; } def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V), - (ins DPR:$src1, GPR:$R, nohash_imm:$lane), - IIC_VMOVISL, "vmov", "32", "$V[$lane], $R", + (ins DPR:$src1, GPR:$R, VectorIndex32:$lane), + IIC_VMOVISL, "vmov", "32", "$V$lane, $R", [(set DPR:$V, (insertelt (v2i32 DPR:$src1), GPR:$R, imm:$lane))]> { let Inst{21} = lane{0}; diff --git a/test/MC/ARM/neon-mov-encoding.s b/test/MC/ARM/neon-mov-encoding.s index c6f3f5d4fb8..2e330039cad 100644 --- a/test/MC/ARM/neon-mov-encoding.s +++ b/test/MC/ARM/neon-mov-encoding.s @@ -105,26 +105,26 @@ @ CHECK: vqmovun.s32 d16, q8 @ encoding: [0x60,0x02,0xf6,0xf3] @ CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xf3] -@ vmov.s8 r0, d16[1] -@ vmov.s16 r0, d16[1] -@ vmov.u8 r0, d16[1] -@ vmov.u16 r0, d16[1] -@ vmov.32 r0, d16[1] -@ vmov.8 d16[1], r1 -@ vmov.16 d16[1], r1 -@ vmov.32 d16[1], r1 -@ vmov.8 d18[1], r1 -@ vmov.16 d18[1], r1 -@ vmov.32 d18[1], r1 + vmov.s8 r0, d16[1] + vmov.s16 r0, d16[1] + vmov.u8 r0, d16[1] + vmov.u16 r0, d16[1] + vmov.32 r0, d16[1] + vmov.8 d16[1], r1 + vmov.16 d16[1], r1 + vmov.32 d16[1], r1 + vmov.8 d18[1], r1 + vmov.16 d18[1], r1 + vmov.32 d18[1], r1 -@ FIXME: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee] -@ FIXME: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee] -@ FIXME: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee] -@ FIXME: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee] -@ FIXME: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee] -@ FIXME: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee] -@ FIXME: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee] -@ FIXME: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee] -@ FIXME: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee] -@ FIXME: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee] -@ FIXME: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee] +@ CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee] +@ CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee] +@ CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee] +@ CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee] +@ CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee] +@ CHECK: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee] +@ CHECK: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee] +@ CHECK: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee] +@ CHECK: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee] +@ CHECK: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee] +@ CHECK: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee]