From: Dan Gohman Date: Fri, 25 Sep 2009 18:54:59 +0000 (+0000) Subject: Rename getTargetNode to getMachineNode, for consistency with the X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=602b0c8c17f458d2c80f2deb3c8e554d516ee316;p=oota-llvm.git Rename getTargetNode to getMachineNode, for consistency with the naming scheme used in SelectionDAG, where there are multiple kinds of "target" nodes, but "machine" nodes are nodes which represent a MachineInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82790 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index a4430ba3201..a3e8a92d990 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -650,38 +650,38 @@ public: SDNode *MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, const SDValue *Ops, unsigned NumOps); - /// getTargetNode - These are used for target selectors to create a new node - /// with specified return type(s), target opcode, and operands. + /// getMachineNode - These are used for target selectors to create a new node + /// with specified return type(s), MachineInstr opcode, and operands. /// - /// Note that getTargetNode returns the resultant node. If there is already a - /// node of the specified opcode and operands, it returns that node instead of - /// the current one. - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT); - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1); - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1, - SDValue Op2); - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, - SDValue Op1, SDValue Op2, SDValue Op3); - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, - const SDValue *Ops, unsigned NumOps); - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2); - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, - SDValue Op1); - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, - EVT VT2, SDValue Op1, SDValue Op2); - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, - EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3); - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, - const SDValue *Ops, unsigned NumOps); - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, - SDValue Op1, SDValue Op2); - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, - SDValue Op1, SDValue Op2, SDValue Op3); - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, - const SDValue *Ops, unsigned NumOps); - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, - EVT VT4, const SDValue *Ops, unsigned NumOps); - SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, + /// Note that getMachineNode returns the resultant node. If there is already + /// a node of the specified opcode and operands, it returns that node instead + /// of the current one. + SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT); + SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1); + SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1, + SDValue Op2); + SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, + SDValue Op1, SDValue Op2, SDValue Op3); + SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, + const SDValue *Ops, unsigned NumOps); + SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2); + SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, + SDValue Op1); + SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, + EVT VT2, SDValue Op1, SDValue Op2); + SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, + EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3); + SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, + const SDValue *Ops, unsigned NumOps); + SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, + EVT VT3, SDValue Op1, SDValue Op2); + SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, + EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3); + SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, + EVT VT3, const SDValue *Ops, unsigned NumOps); + SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, + EVT VT3, EVT VT4, const SDValue *Ops, unsigned NumOps); + SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, const std::vector &ResultTys, const SDValue *Ops, unsigned NumOps); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 9925cf77a81..2b2e911ebe7 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -4494,107 +4494,107 @@ SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, } -/// getTargetNode - These are used for target selectors to create a new node -/// with specified return type(s), target opcode, and operands. +/// getMachineNode - These are used for target selectors to create a new node +/// with specified return type(s), MachineInstr opcode, and operands. /// -/// Note that getTargetNode returns the resultant node. If there is already a +/// Note that getMachineNode returns the resultant node. If there is already a /// node of the specified opcode and operands, it returns that node instead of /// the current one. -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT) { +SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT) { return getNode(~Opcode, dl, VT).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, - SDValue Op1) { +SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, + SDValue Op1) { return getNode(~Opcode, dl, VT, Op1).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, - SDValue Op1, SDValue Op2) { +SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, + SDValue Op1, SDValue Op2) { return getNode(~Opcode, dl, VT, Op1, Op2).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, - SDValue Op1, SDValue Op2, - SDValue Op3) { +SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, + SDValue Op1, SDValue Op2, + SDValue Op3) { return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, - const SDValue *Ops, unsigned NumOps) { +SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, + const SDValue *Ops, unsigned NumOps) { return getNode(~Opcode, dl, VT, Ops, NumOps).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, - EVT VT1, EVT VT2) { +SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, + EVT VT1, EVT VT2) { SDVTList VTs = getVTList(VT1, VT2); SDValue Op; return getNode(~Opcode, dl, VTs, &Op, 0).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, - EVT VT2, SDValue Op1) { +SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, + EVT VT2, SDValue Op1) { SDVTList VTs = getVTList(VT1, VT2); return getNode(~Opcode, dl, VTs, &Op1, 1).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, - EVT VT2, SDValue Op1, - SDValue Op2) { +SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, + EVT VT2, SDValue Op1, + SDValue Op2) { SDVTList VTs = getVTList(VT1, VT2); SDValue Ops[] = { Op1, Op2 }; return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, - EVT VT2, SDValue Op1, - SDValue Op2, SDValue Op3) { +SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, + EVT VT2, SDValue Op1, + SDValue Op2, SDValue Op3) { SDVTList VTs = getVTList(VT1, VT2); SDValue Ops[] = { Op1, Op2, Op3 }; return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, - EVT VT1, EVT VT2, - const SDValue *Ops, unsigned NumOps) { +SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, + EVT VT1, EVT VT2, + const SDValue *Ops, unsigned NumOps) { SDVTList VTs = getVTList(VT1, VT2); return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, - EVT VT1, EVT VT2, EVT VT3, - SDValue Op1, SDValue Op2) { +SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, + EVT VT1, EVT VT2, EVT VT3, + SDValue Op1, SDValue Op2) { SDVTList VTs = getVTList(VT1, VT2, VT3); SDValue Ops[] = { Op1, Op2 }; return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, - EVT VT1, EVT VT2, EVT VT3, - SDValue Op1, SDValue Op2, - SDValue Op3) { +SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, + EVT VT1, EVT VT2, EVT VT3, + SDValue Op1, SDValue Op2, + SDValue Op3) { SDVTList VTs = getVTList(VT1, VT2, VT3); SDValue Ops[] = { Op1, Op2, Op3 }; return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, - EVT VT1, EVT VT2, EVT VT3, - const SDValue *Ops, unsigned NumOps) { +SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, + EVT VT1, EVT VT2, EVT VT3, + const SDValue *Ops, unsigned NumOps) { SDVTList VTs = getVTList(VT1, VT2, VT3); return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, - EVT VT2, EVT VT3, EVT VT4, - const SDValue *Ops, unsigned NumOps) { +SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, + EVT VT2, EVT VT3, EVT VT4, + const SDValue *Ops, unsigned NumOps) { SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, - const std::vector &ResultTys, - const SDValue *Ops, unsigned NumOps) { +SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, + const std::vector &ResultTys, + const SDValue *Ops, unsigned NumOps) { return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode(); } @@ -4604,8 +4604,8 @@ SDValue SelectionDAG::getTargetExtractSubreg(int SRIdx, DebugLoc DL, EVT VT, SDValue Operand) { SDValue SRIdxVal = getTargetConstant(SRIdx, MVT::i32); - SDNode *Subreg = getTargetNode(TargetInstrInfo::EXTRACT_SUBREG, DL, - VT, Operand, SRIdxVal); + SDNode *Subreg = getMachineNode(TargetInstrInfo::EXTRACT_SUBREG, DL, + VT, Operand, SRIdxVal); return SDValue(Subreg, 0); } diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 86407f71567..a37c7c5a026 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -813,8 +813,8 @@ SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) { SDValue Base = LD->getBasePtr(); SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), Chain }; - return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32, - MVT::Other, Ops, 6); + return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32, + MVT::Other, Ops, 6); } return NULL; @@ -861,8 +861,8 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) { SDValue Base = LD->getBasePtr(); SDValue Ops[]= { Base, Offset, getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), Chain }; - return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32, - MVT::Other, Ops, 5); + return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32, + MVT::Other, Ops, 5); } return NULL; @@ -882,7 +882,7 @@ SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) { // instruction that can read and write SP. This matches to a pseudo // instruction that has a chain to ensure the result is written back to // the stack pointer. - SP = SDValue(CurDAG->getTargetNode(ARM::tANDsp, dl, VT, SP, Align), 0); + SP = SDValue(CurDAG->getMachineNode(ARM::tANDsp, dl, VT, SP, Align), 0); bool isC = isa(Size); uint32_t C = isC ? cast(Size)->getZExtValue() : ~0UL; @@ -958,8 +958,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32); SDValue PredReg = CurDAG->getRegister(0, MVT::i32); SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; - ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other, - Ops, 4); + ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other, + Ops, 4); } else { SDValue Ops[] = { CPIdx, @@ -969,8 +969,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { CurDAG->getRegister(0, MVT::i32), CurDAG->getEntryNode() }; - ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other, - Ops, 6); + ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other, + Ops, 6); } ReplaceUses(Op, SDValue(ResNode, 0)); return NULL; @@ -1038,9 +1038,9 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { } break; case ARMISD::FMRRD: - return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32, - Op.getOperand(0), getAL(CurDAG), - CurDAG->getRegister(0, MVT::i32)); + return CurDAG->getMachineNode(ARM::FMRRD, dl, MVT::i32, MVT::i32, + Op.getOperand(0), getAL(CurDAG), + CurDAG->getRegister(0, MVT::i32)); case ISD::UMUL_LOHI: { if (Subtarget->isThumb1Only()) break; @@ -1048,12 +1048,12 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), CurDAG->getRegister(0, MVT::i32) }; - return CurDAG->getTargetNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4); + return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4); } else { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), CurDAG->getRegister(0, MVT::i32) }; - return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5); + return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5); } } case ISD::SMUL_LOHI: { @@ -1062,12 +1062,12 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { if (Subtarget->isThumb()) { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) }; - return CurDAG->getTargetNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4); + return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4); } else { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), CurDAG->getRegister(0, MVT::i32) }; - return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5); + return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5); } } case ISD::LOAD: { @@ -1109,8 +1109,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { cast(N2)->getZExtValue()), MVT::i32); SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag }; - SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other, - MVT::Flag, Ops, 5); + SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other, + MVT::Flag, Ops, 5); Chain = SDValue(ResNode, 0); if (Op.getNode()->getNumValues() == 2) { InFlag = SDValue(ResNode, 1); @@ -1277,8 +1277,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case MVT::v4f32: case MVT::v4i32: Opc = ARM::VZIPq32; break; } - return CurDAG->getTargetNode(Opc, dl, VT, VT, - N->getOperand(0), N->getOperand(1)); + return CurDAG->getMachineNode(Opc, dl, VT, VT, + N->getOperand(0), N->getOperand(1)); } case ARMISD::VUZP: { unsigned Opc = 0; @@ -1294,8 +1294,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case MVT::v4f32: case MVT::v4i32: Opc = ARM::VUZPq32; break; } - return CurDAG->getTargetNode(Opc, dl, VT, VT, - N->getOperand(0), N->getOperand(1)); + return CurDAG->getMachineNode(Opc, dl, VT, VT, + N->getOperand(0), N->getOperand(1)); } case ARMISD::VTRN: { unsigned Opc = 0; @@ -1311,8 +1311,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case MVT::v4f32: case MVT::v4i32: Opc = ARM::VTRNq32; break; } - return CurDAG->getTargetNode(Opc, dl, VT, VT, - N->getOperand(0), N->getOperand(1)); + return CurDAG->getMachineNode(Opc, dl, VT, VT, + N->getOperand(0), N->getOperand(1)); } case ISD::INTRINSIC_VOID: @@ -1338,7 +1338,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { } SDValue Chain = N->getOperand(0); const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain }; - return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 4); + return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 4); } case Intrinsic::arm_neon_vld3: { @@ -1354,7 +1354,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { } SDValue Chain = N->getOperand(0); const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain }; - return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 4); + return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 4); } case Intrinsic::arm_neon_vld4: { @@ -1372,7 +1372,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain }; std::vector ResTys(4, VT); ResTys.push_back(MVT::Other); - return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 4); + return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 4); } case Intrinsic::arm_neon_vld2lane: { @@ -1390,7 +1390,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, N->getOperand(3), N->getOperand(4), N->getOperand(5), Chain }; - return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 7); + return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 7); } case Intrinsic::arm_neon_vld3lane: { @@ -1408,7 +1408,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, N->getOperand(3), N->getOperand(4), N->getOperand(5), N->getOperand(6), Chain }; - return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 8); + return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 8); } case Intrinsic::arm_neon_vld4lane: { @@ -1429,7 +1429,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { N->getOperand(7), Chain }; std::vector ResTys(4, VT); ResTys.push_back(MVT::Other); - return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 9); + return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 9); } case Intrinsic::arm_neon_vst2: { @@ -1446,7 +1446,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { SDValue Chain = N->getOperand(0); const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, N->getOperand(3), N->getOperand(4), Chain }; - return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6); + return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6); } case Intrinsic::arm_neon_vst3: { @@ -1464,7 +1464,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, N->getOperand(3), N->getOperand(4), N->getOperand(5), Chain }; - return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7); + return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7); } case Intrinsic::arm_neon_vst4: { @@ -1482,7 +1482,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, N->getOperand(3), N->getOperand(4), N->getOperand(5), N->getOperand(6), Chain }; - return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8); + return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8); } case Intrinsic::arm_neon_vst2lane: { @@ -1500,7 +1500,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, N->getOperand(3), N->getOperand(4), N->getOperand(5), Chain }; - return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7); + return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7); } case Intrinsic::arm_neon_vst3lane: { @@ -1518,7 +1518,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, N->getOperand(3), N->getOperand(4), N->getOperand(5), N->getOperand(6), Chain }; - return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8); + return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8); } case Intrinsic::arm_neon_vst4lane: { @@ -1537,7 +1537,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { N->getOperand(3), N->getOperand(4), N->getOperand(5), N->getOperand(6), N->getOperand(7), Chain }; - return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 9); + return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 9); } } } diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index c40bba392f4..e3587fb2c90 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -270,8 +270,8 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0, Chain.getValue(1)); SDNode *CNode = - CurDAG->getTargetNode(Alpha::JSRs, dl, MVT::Other, MVT::Flag, - Chain, Chain.getValue(1)); + CurDAG->getMachineNode(Alpha::JSRs, dl, MVT::Other, MVT::Flag, + Chain, Chain.getValue(1)); Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64, SDValue(CNode, 1)); return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain); @@ -279,8 +279,8 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { case ISD::READCYCLECOUNTER: { SDValue Chain = N->getOperand(0); - return CurDAG->getTargetNode(Alpha::RPCC, dl, MVT::i64, MVT::Other, - Chain); + return CurDAG->getMachineNode(Alpha::RPCC, dl, MVT::i64, MVT::Other, + Chain); } case ISD::Constant: { @@ -306,8 +306,8 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { ConstantInt *C = ConstantInt::get( Type::getInt64Ty(*CurDAG->getContext()), uval); SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64); - SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, dl, MVT::i64, CPI, - SDValue(getGlobalBaseReg(), 0)); + SDNode *Tmp = CurDAG->getMachineNode(Alpha::LDAHr, dl, MVT::i64, CPI, + SDValue(getGlobalBaseReg(), 0)); return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, CPI, SDValue(Tmp, 0), CurDAG->getEntryNode()); } @@ -358,29 +358,29 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { }; SDValue tmp1 = N->getOperand(rev?1:0); SDValue tmp2 = N->getOperand(rev?0:1); - SDNode *cmp = CurDAG->getTargetNode(Opc, dl, MVT::f64, tmp1, tmp2); + SDNode *cmp = CurDAG->getMachineNode(Opc, dl, MVT::f64, tmp1, tmp2); if (inv) - cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, dl, - MVT::f64, SDValue(cmp, 0), - CurDAG->getRegister(Alpha::F31, MVT::f64)); + cmp = CurDAG->getMachineNode(Alpha::CMPTEQ, dl, + MVT::f64, SDValue(cmp, 0), + CurDAG->getRegister(Alpha::F31, MVT::f64)); switch(CC) { case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE: case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE: { - SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, dl, MVT::f64, - tmp1, tmp2); - cmp = CurDAG->getTargetNode(Alpha::ADDT, dl, MVT::f64, - SDValue(cmp2, 0), SDValue(cmp, 0)); + SDNode* cmp2 = CurDAG->getMachineNode(Alpha::CMPTUN, dl, MVT::f64, + tmp1, tmp2); + cmp = CurDAG->getMachineNode(Alpha::ADDT, dl, MVT::f64, + SDValue(cmp2, 0), SDValue(cmp, 0)); break; } default: break; } - SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, dl, - MVT::i64, SDValue(cmp, 0)); - return CurDAG->getTargetNode(Alpha::CMPULT, dl, MVT::i64, - CurDAG->getRegister(Alpha::R31, MVT::i64), - SDValue(LD,0)); + SDNode* LD = CurDAG->getMachineNode(Alpha::FTOIT, dl, + MVT::i64, SDValue(cmp, 0)); + return CurDAG->getMachineNode(Alpha::CMPULT, dl, MVT::i64, + CurDAG->getRegister(Alpha::R31, MVT::i64), + SDValue(LD,0)); } break; @@ -405,11 +405,11 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { if (get_zapImm(mask)) { SDValue Z = - SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, dl, MVT::i64, - N->getOperand(0).getOperand(0), - getI64Imm(get_zapImm(mask))), 0); - return CurDAG->getTargetNode(Alpha::SRLr, dl, MVT::i64, Z, - getI64Imm(sval)); + SDValue(CurDAG->getMachineNode(Alpha::ZAPNOTi, dl, MVT::i64, + N->getOperand(0).getOperand(0), + getI64Imm(get_zapImm(mask))), 0); + return CurDAG->getMachineNode(Alpha::SRLr, dl, MVT::i64, Z, + getI64Imm(sval)); } } break; @@ -433,14 +433,14 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) { SDValue GOT = SDValue(getGlobalBaseReg(), 0); Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag); InFlag = Chain.getValue(1); - Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, dl, MVT::Other, - MVT::Flag, Addr.getOperand(0), - Chain, InFlag), 0); + Chain = SDValue(CurDAG->getMachineNode(Alpha::BSR, dl, MVT::Other, + MVT::Flag, Addr.getOperand(0), + Chain, InFlag), 0); } else { Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag); InFlag = Chain.getValue(1); - Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, dl, MVT::Other, - MVT::Flag, Chain, InFlag), 0); + Chain = SDValue(CurDAG->getMachineNode(Alpha::JSR, dl, MVT::Other, + MVT::Flag, Chain, InFlag), 0); } InFlag = Chain.getValue(1); diff --git a/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp b/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp index 28aeaede7ce..fc62a1884b1 100644 --- a/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp +++ b/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp @@ -177,11 +177,11 @@ void BlackfinDAGToDAGISel::FixRegisterClasses(SelectionDAG &DAG) { // We cannot copy CC <-> !(CC/D) if ((isCC(DefRC) && !isDCC(UseRC)) || (isCC(UseRC) && !isDCC(DefRC))) { SDNode *Copy = - DAG.getTargetNode(TargetInstrInfo::COPY_TO_REGCLASS, - NI->getDebugLoc(), - MVT::i32, - UI.getUse().get(), - DAG.getTargetConstant(BF::DRegClassID, MVT::i32)); + DAG.getMachineNode(TargetInstrInfo::COPY_TO_REGCLASS, + NI->getDebugLoc(), + MVT::i32, + UI.getUse().get(), + DAG.getTargetConstant(BF::DRegClassID, MVT::i32)); UpdateNodeOperand(DAG, *UI, UI.getOperandNo(), SDValue(Copy, 0)); } } diff --git a/lib/Target/Blackfin/BlackfinISelLowering.cpp b/lib/Target/Blackfin/BlackfinISelLowering.cpp index 374ac278fa1..4b321ec0fda 100644 --- a/lib/Target/Blackfin/BlackfinISelLowering.cpp +++ b/lib/Target/Blackfin/BlackfinISelLowering.cpp @@ -422,26 +422,26 @@ SDValue BlackfinTargetLowering::LowerADDE(SDValue Op, SelectionDAG &DAG) { unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB; // zext incoming carry flag in AC0 to 32 bits - SDNode* CarryIn = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, MVT::i32, - /* flag= */ Op.getOperand(2)); - CarryIn = DAG.getTargetNode(BF::MOVECC_zext, dl, MVT::i32, - SDValue(CarryIn, 0)); + SDNode* CarryIn = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32, + /* flag= */ Op.getOperand(2)); + CarryIn = DAG.getMachineNode(BF::MOVECC_zext, dl, MVT::i32, + SDValue(CarryIn, 0)); // Add operands, produce sum and carry flag - SDNode *Sum = DAG.getTargetNode(Opcode, dl, MVT::i32, MVT::Flag, - Op.getOperand(0), Op.getOperand(1)); + SDNode *Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Flag, + Op.getOperand(0), Op.getOperand(1)); // Store intermediate carry from Sum - SDNode* Carry1 = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, MVT::i32, - /* flag= */ SDValue(Sum, 1)); + SDNode* Carry1 = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32, + /* flag= */ SDValue(Sum, 1)); // Add incoming carry, again producing an output flag - Sum = DAG.getTargetNode(Opcode, dl, MVT::i32, MVT::Flag, - SDValue(Sum, 0), SDValue(CarryIn, 0)); + Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Flag, + SDValue(Sum, 0), SDValue(CarryIn, 0)); // Update AC0 with the intermediate carry, producing a flag. - SDNode *CarryOut = DAG.getTargetNode(BF::OR_ac0_cc, dl, MVT::Flag, - SDValue(Carry1, 0)); + SDNode *CarryOut = DAG.getMachineNode(BF::OR_ac0_cc, dl, MVT::Flag, + SDValue(Carry1, 0)); // Compose (i32, flag) pair SDValue ops[2] = { SDValue(Sum, 0), SDValue(CarryOut, 0) }; diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index 1c5e739ef84..1f9e5fcc4a7 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -713,8 +713,9 @@ SPUDAGToDAGISel::Select(SDValue Op) { } else { NewOpc = SPU::Ar32; Ops[0] = CurDAG->getRegister(SPU::R1, Op.getValueType()); - Ops[1] = SDValue(CurDAG->getTargetNode(SPU::ILAr32, dl, Op.getValueType(), - TFI, Imm0), 0); + Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILAr32, dl, + Op.getValueType(), TFI, Imm0), + 0); n_ops = 2; } } else if (Opc == ISD::Constant && OpVT == MVT::i64) { @@ -813,8 +814,8 @@ SPUDAGToDAGISel::Select(SDValue Op) { if (shift_amt >= 32) { SDNode *hi32 = - CurDAG->getTargetNode(SPU::ORr32_r64, dl, OpVT, - Op0.getOperand(0)); + CurDAG->getMachineNode(SPU::ORr32_r64, dl, OpVT, + Op0.getOperand(0)); shift_amt -= 32; if (shift_amt > 0) { @@ -825,8 +826,8 @@ SPUDAGToDAGISel::Select(SDValue Op) { if (Op0.getOpcode() == ISD::SRL) Opc = SPU::ROTMr32; - hi32 = CurDAG->getTargetNode(Opc, dl, OpVT, SDValue(hi32, 0), - shift); + hi32 = CurDAG->getMachineNode(Opc, dl, OpVT, SDValue(hi32, 0), + shift); } return hi32; @@ -858,10 +859,10 @@ SPUDAGToDAGISel::Select(SDValue Op) { if (OpVT == MVT::v2f64) Opc = SPU::DFNMSv2f64; - return CurDAG->getTargetNode(Opc, dl, OpVT, - Op00.getOperand(0), - Op00.getOperand(1), - Op0.getOperand(1)); + return CurDAG->getMachineNode(Opc, dl, OpVT, + Op00.getOperand(0), + Op00.getOperand(1), + Op0.getOperand(1)); } } @@ -878,20 +879,20 @@ SPUDAGToDAGISel::Select(SDValue Op) { negConst, negConst)); } - return CurDAG->getTargetNode(Opc, dl, OpVT, - Op.getOperand(0), SDValue(signMask, 0)); + return CurDAG->getMachineNode(Opc, dl, OpVT, + Op.getOperand(0), SDValue(signMask, 0)); } else if (Opc == ISD::FABS) { if (OpVT == MVT::f64) { SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl); - return CurDAG->getTargetNode(SPU::ANDfabs64, dl, OpVT, - Op.getOperand(0), SDValue(signMask, 0)); + return CurDAG->getMachineNode(SPU::ANDfabs64, dl, OpVT, + Op.getOperand(0), SDValue(signMask, 0)); } else if (OpVT == MVT::v2f64) { SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64); SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, absConst, absConst); SDNode *signMask = emitBuildVector(absVec); - return CurDAG->getTargetNode(SPU::ANDfabsvec, dl, OpVT, - Op.getOperand(0), SDValue(signMask, 0)); + return CurDAG->getMachineNode(SPU::ANDfabsvec, dl, OpVT, + Op.getOperand(0), SDValue(signMask, 0)); } } else if (Opc == SPUISD::LDRESULT) { // Custom select instructions for LDRESULT @@ -913,9 +914,9 @@ SPUDAGToDAGISel::Select(SDValue Op) { if (vtm->ldresult_imm) { SDValue Zero = CurDAG->getTargetConstant(0, VT); - Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain); + Result = CurDAG->getMachineNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain); } else { - Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain); + Result = CurDAG->getMachineNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain); } return Result; @@ -951,7 +952,7 @@ SPUDAGToDAGISel::Select(SDValue Op) { if (N->hasOneUse()) return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops); else - return CurDAG->getTargetNode(NewOpc, dl, OpVT, Ops, n_ops); + return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops); } else return SelectCode(Op); } @@ -979,15 +980,15 @@ SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, EVT OpVT) { SDValue SelMaskVal; DebugLoc dl = Op.getDebugLoc(); - VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0); + VecOp0 = CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, Op0); SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16); - SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal); - ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, dl, VecVT, - CurDAG->getTargetConstant(0, OpVT)); - VecOp0 = CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT, - SDValue(ZeroFill, 0), - SDValue(VecOp0, 0), - SDValue(SelMask, 0)); + SelMask = CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal); + ZeroFill = CurDAG->getMachineNode(SPU::ILv2i64, dl, VecVT, + CurDAG->getTargetConstant(0, OpVT)); + VecOp0 = CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT, + SDValue(ZeroFill, 0), + SDValue(VecOp0, 0), + SDValue(SelMask, 0)); if (ConstantSDNode *CN = dyn_cast(ShiftAmt)) { unsigned bytes = unsigned(CN->getZExtValue()) >> 3; @@ -995,35 +996,35 @@ SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, EVT OpVT) { if (bytes > 0) { Shift = - CurDAG->getTargetNode(SPU::SHLQBYIv2i64, dl, VecVT, - SDValue(VecOp0, 0), - CurDAG->getTargetConstant(bytes, ShiftAmtVT)); + CurDAG->getMachineNode(SPU::SHLQBYIv2i64, dl, VecVT, + SDValue(VecOp0, 0), + CurDAG->getTargetConstant(bytes, ShiftAmtVT)); } if (bits > 0) { Shift = - CurDAG->getTargetNode(SPU::SHLQBIIv2i64, dl, VecVT, - SDValue((Shift != 0 ? Shift : VecOp0), 0), - CurDAG->getTargetConstant(bits, ShiftAmtVT)); + CurDAG->getMachineNode(SPU::SHLQBIIv2i64, dl, VecVT, + SDValue((Shift != 0 ? Shift : VecOp0), 0), + CurDAG->getTargetConstant(bits, ShiftAmtVT)); } } else { SDNode *Bytes = - CurDAG->getTargetNode(SPU::ROTMIr32, dl, ShiftAmtVT, - ShiftAmt, - CurDAG->getTargetConstant(3, ShiftAmtVT)); + CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT, + ShiftAmt, + CurDAG->getTargetConstant(3, ShiftAmtVT)); SDNode *Bits = - CurDAG->getTargetNode(SPU::ANDIr32, dl, ShiftAmtVT, - ShiftAmt, - CurDAG->getTargetConstant(7, ShiftAmtVT)); + CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT, + ShiftAmt, + CurDAG->getTargetConstant(7, ShiftAmtVT)); Shift = - CurDAG->getTargetNode(SPU::SHLQBYv2i64, dl, VecVT, - SDValue(VecOp0, 0), SDValue(Bytes, 0)); + CurDAG->getMachineNode(SPU::SHLQBYv2i64, dl, VecVT, + SDValue(VecOp0, 0), SDValue(Bytes, 0)); Shift = - CurDAG->getTargetNode(SPU::SHLQBIv2i64, dl, VecVT, - SDValue(Shift, 0), SDValue(Bits, 0)); + CurDAG->getMachineNode(SPU::SHLQBIv2i64, dl, VecVT, + SDValue(Shift, 0), SDValue(Bits, 0)); } - return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0)); + return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0)); } /*! @@ -1044,7 +1045,7 @@ SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, EVT OpVT) { SDNode *VecOp0, *Shift = 0; DebugLoc dl = Op.getDebugLoc(); - VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0); + VecOp0 = CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, Op0); if (ConstantSDNode *CN = dyn_cast(ShiftAmt)) { unsigned bytes = unsigned(CN->getZExtValue()) >> 3; @@ -1052,45 +1053,45 @@ SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, EVT OpVT) { if (bytes > 0) { Shift = - CurDAG->getTargetNode(SPU::ROTQMBYIv2i64, dl, VecVT, - SDValue(VecOp0, 0), - CurDAG->getTargetConstant(bytes, ShiftAmtVT)); + CurDAG->getMachineNode(SPU::ROTQMBYIv2i64, dl, VecVT, + SDValue(VecOp0, 0), + CurDAG->getTargetConstant(bytes, ShiftAmtVT)); } if (bits > 0) { Shift = - CurDAG->getTargetNode(SPU::ROTQMBIIv2i64, dl, VecVT, - SDValue((Shift != 0 ? Shift : VecOp0), 0), - CurDAG->getTargetConstant(bits, ShiftAmtVT)); + CurDAG->getMachineNode(SPU::ROTQMBIIv2i64, dl, VecVT, + SDValue((Shift != 0 ? Shift : VecOp0), 0), + CurDAG->getTargetConstant(bits, ShiftAmtVT)); } } else { SDNode *Bytes = - CurDAG->getTargetNode(SPU::ROTMIr32, dl, ShiftAmtVT, - ShiftAmt, - CurDAG->getTargetConstant(3, ShiftAmtVT)); + CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT, + ShiftAmt, + CurDAG->getTargetConstant(3, ShiftAmtVT)); SDNode *Bits = - CurDAG->getTargetNode(SPU::ANDIr32, dl, ShiftAmtVT, - ShiftAmt, - CurDAG->getTargetConstant(7, ShiftAmtVT)); + CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT, + ShiftAmt, + CurDAG->getTargetConstant(7, ShiftAmtVT)); // Ensure that the shift amounts are negated! - Bytes = CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT, - SDValue(Bytes, 0), - CurDAG->getTargetConstant(0, ShiftAmtVT)); + Bytes = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT, + SDValue(Bytes, 0), + CurDAG->getTargetConstant(0, ShiftAmtVT)); - Bits = CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT, - SDValue(Bits, 0), - CurDAG->getTargetConstant(0, ShiftAmtVT)); + Bits = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT, + SDValue(Bits, 0), + CurDAG->getTargetConstant(0, ShiftAmtVT)); Shift = - CurDAG->getTargetNode(SPU::ROTQMBYv2i64, dl, VecVT, - SDValue(VecOp0, 0), SDValue(Bytes, 0)); + CurDAG->getMachineNode(SPU::ROTQMBYv2i64, dl, VecVT, + SDValue(VecOp0, 0), SDValue(Bytes, 0)); Shift = - CurDAG->getTargetNode(SPU::ROTQMBIv2i64, dl, VecVT, - SDValue(Shift, 0), SDValue(Bits, 0)); + CurDAG->getMachineNode(SPU::ROTQMBIv2i64, dl, VecVT, + SDValue(Shift, 0), SDValue(Bits, 0)); } - return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0)); + return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0)); } /*! @@ -1111,25 +1112,25 @@ SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, EVT OpVT) { DebugLoc dl = Op.getDebugLoc(); SDNode *VecOp0 = - CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op.getOperand(0)); + CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, Op.getOperand(0)); SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT); SDNode *SignRot = - CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64, - SDValue(VecOp0, 0), SignRotAmt); + CurDAG->getMachineNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64, + SDValue(VecOp0, 0), SignRotAmt); SDNode *UpperHalfSign = - CurDAG->getTargetNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0)); + CurDAG->getMachineNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0)); SDNode *UpperHalfSignMask = - CurDAG->getTargetNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0)); + CurDAG->getMachineNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0)); SDNode *UpperLowerMask = - CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT, - CurDAG->getTargetConstant(0xff00ULL, MVT::i16)); + CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT, + CurDAG->getTargetConstant(0xff00ULL, MVT::i16)); SDNode *UpperLowerSelect = - CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT, - SDValue(UpperHalfSignMask, 0), - SDValue(VecOp0, 0), - SDValue(UpperLowerMask, 0)); + CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT, + SDValue(UpperHalfSignMask, 0), + SDValue(VecOp0, 0), + SDValue(UpperLowerMask, 0)); SDNode *Shift = 0; @@ -1140,32 +1141,32 @@ SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, EVT OpVT) { if (bytes > 0) { bytes = 31 - bytes; Shift = - CurDAG->getTargetNode(SPU::ROTQBYIv2i64, dl, VecVT, - SDValue(UpperLowerSelect, 0), - CurDAG->getTargetConstant(bytes, ShiftAmtVT)); + CurDAG->getMachineNode(SPU::ROTQBYIv2i64, dl, VecVT, + SDValue(UpperLowerSelect, 0), + CurDAG->getTargetConstant(bytes, ShiftAmtVT)); } if (bits > 0) { bits = 8 - bits; Shift = - CurDAG->getTargetNode(SPU::ROTQBIIv2i64, dl, VecVT, - SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0), - CurDAG->getTargetConstant(bits, ShiftAmtVT)); + CurDAG->getMachineNode(SPU::ROTQBIIv2i64, dl, VecVT, + SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0), + CurDAG->getTargetConstant(bits, ShiftAmtVT)); } } else { SDNode *NegShift = - CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT, - ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT)); + CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT, + ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT)); Shift = - CurDAG->getTargetNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT, - SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0)); + CurDAG->getMachineNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT, + SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0)); Shift = - CurDAG->getTargetNode(SPU::ROTQBIv2i64, dl, VecVT, - SDValue(Shift, 0), SDValue(NegShift, 0)); + CurDAG->getMachineNode(SPU::ROTQBIv2i64, dl, VecVT, + SDValue(Shift, 0), SDValue(NegShift, 0)); } - return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0)); + return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0)); } /*! @@ -1192,8 +1193,8 @@ SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT, SDValue Op0 = i64vec.getOperand(0); ReplaceUses(i64vec, Op0); - return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, - SDValue(emitBuildVector(Op0), 0)); + return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, + SDValue(emitBuildVector(Op0), 0)); } else if (i64vec.getOpcode() == SPUISD::SHUFB) { SDValue lhs = i64vec.getOperand(0); SDValue rhs = i64vec.getOperand(1); @@ -1231,11 +1232,11 @@ SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT, SDValue(lhsNode, 0), SDValue(rhsNode, 0), SDValue(shufMaskNode, 0))); - return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, - SDValue(shufNode, 0)); + return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, + SDValue(shufNode, 0)); } else if (i64vec.getOpcode() == ISD::BUILD_VECTOR) { - return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, - SDValue(emitBuildVector(i64vec), 0)); + return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, + SDValue(emitBuildVector(i64vec), 0)); } else { llvm_report_error("SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec" "condition"); diff --git a/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp index 7a34c6fcb00..25287e9dcec 100644 --- a/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp +++ b/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp @@ -166,8 +166,8 @@ SDNode *MSP430DAGToDAGISel::Select(SDValue Op) { if (Node->hasOneUse()) return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16, TFI, CurDAG->getTargetConstant(0, MVT::i16)); - return CurDAG->getTargetNode(MSP430::ADD16ri, dl, MVT::i16, - TFI, CurDAG->getTargetConstant(0, MVT::i16)); + return CurDAG->getMachineNode(MSP430::ADD16ri, dl, MVT::i16, + TFI, CurDAG->getTargetConstant(0, MVT::i16)); } } diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp index f2dec31d29b..cc20dd7b4ff 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -232,9 +232,9 @@ SDNode* MipsDAGToDAGISel::Select(SDValue N) { SDValue RHS = Node->getOperand(1); EVT VT = LHS.getValueType(); - SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, dl, VT, Ops, 2); - SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, dl, VT, - SDValue(Carry,0), RHS); + SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2); + SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT, + SDValue(Carry,0), RHS); return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag, LHS, SDValue(AddCarry,0)); @@ -254,13 +254,13 @@ SDNode* MipsDAGToDAGISel::Select(SDValue N) { else Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV); - SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2); + SDNode *Node = CurDAG->getMachineNode(Op, dl, MVT::Flag, Op1, Op2); SDValue InFlag = SDValue(Node, 0); - SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32, - MVT::Flag, InFlag); + SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, + MVT::Flag, InFlag); InFlag = SDValue(Lo,1); - SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag); + SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); if (!N.getValue(0).use_empty()) ReplaceUses(N.getValue(0), SDValue(Lo,0)); @@ -279,15 +279,15 @@ SDNode* MipsDAGToDAGISel::Select(SDValue N) { SDValue MulOp2 = Node->getOperand(1); unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT); - SDNode *MulNode = CurDAG->getTargetNode(MulOp, dl, - MVT::Flag, MulOp1, MulOp2); + SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl, + MVT::Flag, MulOp1, MulOp2); SDValue InFlag = SDValue(MulNode, 0); if (MulOp == ISD::MUL) - return CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32, InFlag); + return CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, InFlag); else - return CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag); + return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); } /// Div/Rem operations @@ -306,10 +306,10 @@ SDNode* MipsDAGToDAGISel::Select(SDValue N) { Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu); MOp = Mips::MFHI; } - SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2); + SDNode *Node = CurDAG->getMachineNode(Op, dl, MVT::Flag, Op1, Op2); SDValue InFlag = SDValue(Node, 0); - return CurDAG->getTargetNode(MOp, dl, MVT::i32, InFlag); + return CurDAG->getMachineNode(MOp, dl, MVT::i32, InFlag); } // Get target GOT address. @@ -335,7 +335,7 @@ SDNode* MipsDAGToDAGISel::Select(SDValue N) { // Use load to get GOT target SDValue Ops[] = { Callee, GPReg, Chain }; - SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, dl, MVT::i32, + SDValue Load = SDValue(CurDAG->getMachineNode(Mips::LW, dl, MVT::i32, MVT::Other, Ops, 3), 0); Chain = Load.getValue(1); @@ -346,7 +346,7 @@ SDNode* MipsDAGToDAGISel::Select(SDValue N) { Chain = CurDAG->getCopyToReg(Chain, dl, T9Reg, Callee, InFlag); // Emit Jump and Link Register - SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, dl, MVT::Other, + SDNode *ResNode = CurDAG->getMachineNode(Mips::JALR, dl, MVT::Other, MVT::Flag, T9Reg, Chain); Chain = SDValue(ResNode, 0); InFlag = SDValue(ResNode, 1); diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 356ca32830e..8fa6a6614b9 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -469,7 +469,7 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { SH &= 31; SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; - return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); + return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); } } return 0; @@ -488,12 +488,12 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, if (isInt32Immediate(RHS, Imm)) { // SETEQ/SETNE comparison with 16-bit immediate, fold it. if (isUInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS, - getI32Imm(Imm & 0xFFFF)), 0); + return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, + getI32Imm(Imm & 0xFFFF)), 0); // If this is a 16-bit signed immediate, fold it. if (isInt16((int)Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS, - getI32Imm(Imm & 0xFFFF)), 0); + return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, + getI32Imm(Imm & 0xFFFF)), 0); // For non-equality comparisons, the default code would materialize the // constant, then compare against it, like this: @@ -504,22 +504,22 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, // xoris r0,r3,0x1234 // cmplwi cr0,r0,0x5678 // beq cr0,L6 - SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, dl, MVT::i32, LHS, - getI32Imm(Imm >> 16)), 0); - return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, Xor, - getI32Imm(Imm & 0xFFFF)), 0); + SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS, + getI32Imm(Imm >> 16)), 0); + return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor, + getI32Imm(Imm & 0xFFFF)), 0); } Opc = PPC::CMPLW; } else if (ISD::isUnsignedIntSetCC(CC)) { if (isInt32Immediate(RHS, Imm) && isUInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS, - getI32Imm(Imm & 0xFFFF)), 0); + return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, + getI32Imm(Imm & 0xFFFF)), 0); Opc = PPC::CMPLW; } else { short SImm; if (isIntS16Immediate(RHS, SImm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS, - getI32Imm((int)SImm & 0xFFFF)), + return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, + getI32Imm((int)SImm & 0xFFFF)), 0); Opc = PPC::CMPW; } @@ -529,12 +529,12 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, if (isInt64Immediate(RHS.getNode(), Imm)) { // SETEQ/SETNE comparison with 16-bit immediate, fold it. if (isUInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS, - getI32Imm(Imm & 0xFFFF)), 0); + return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, + getI32Imm(Imm & 0xFFFF)), 0); // If this is a 16-bit signed immediate, fold it. if (isInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS, - getI32Imm(Imm & 0xFFFF)), 0); + return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, + getI32Imm(Imm & 0xFFFF)), 0); // For non-equality comparisons, the default code would materialize the // constant, then compare against it, like this: @@ -546,23 +546,23 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, // cmpldi cr0,r0,0x5678 // beq cr0,L6 if (isUInt32(Imm)) { - SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, dl, MVT::i64, LHS, - getI64Imm(Imm >> 16)), 0); - return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, Xor, - getI64Imm(Imm & 0xFFFF)), 0); + SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS, + getI64Imm(Imm >> 16)), 0); + return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor, + getI64Imm(Imm & 0xFFFF)), 0); } } Opc = PPC::CMPLD; } else if (ISD::isUnsignedIntSetCC(CC)) { if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS, - getI64Imm(Imm & 0xFFFF)), 0); + return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, + getI64Imm(Imm & 0xFFFF)), 0); Opc = PPC::CMPLD; } else { short SImm; if (isIntS16Immediate(RHS, SImm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS, - getI64Imm(SImm & 0xFFFF)), + return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, + getI64Imm(SImm & 0xFFFF)), 0); Opc = PPC::CMPD; } @@ -572,7 +572,7 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, assert(LHS.getValueType() == MVT::f64 && "Unknown vt!"); Opc = PPC::FCMPUD; } - return SDValue(CurDAG->getTargetNode(Opc, dl, MVT::i32, LHS, RHS), 0); + return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0); } static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { @@ -654,14 +654,14 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) { switch (CC) { default: break; case ISD::SETEQ: { - Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, dl, MVT::i32, Op), 0); + Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0); SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } case ISD::SETNE: { SDValue AD = - SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, - Op, getI32Imm(~0U)), 0); + SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, + Op, getI32Imm(~0U)), 0); return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1)); } @@ -671,8 +671,8 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) { } case ISD::SETGT: { SDValue T = - SDValue(CurDAG->getTargetNode(PPC::NEG, dl, MVT::i32, Op), 0); - T = SDValue(CurDAG->getTargetNode(PPC::ANDC, dl, MVT::i32, T, Op), 0); + SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0); + T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0); SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } @@ -682,31 +682,31 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) { switch (CC) { default: break; case ISD::SETEQ: - Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, - Op, getI32Imm(1)), 0); + Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, + Op, getI32Imm(1)), 0); return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, - SDValue(CurDAG->getTargetNode(PPC::LI, dl, - MVT::i32, - getI32Imm(0)), 0), + SDValue(CurDAG->getMachineNode(PPC::LI, dl, + MVT::i32, + getI32Imm(0)), 0), Op.getValue(1)); case ISD::SETNE: { - Op = SDValue(CurDAG->getTargetNode(PPC::NOR, dl, MVT::i32, Op, Op), 0); - SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, - Op, getI32Imm(~0U)); + Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0); + SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, + Op, getI32Imm(~0U)); return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), Op, SDValue(AD, 1)); } case ISD::SETLT: { - SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, dl, MVT::i32, Op, - getI32Imm(1)), 0); - SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, dl, MVT::i32, AD, - Op), 0); + SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op, + getI32Imm(1)), 0); + SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD, + Op), 0); SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } case ISD::SETGT: { SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; - Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), + Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1)); @@ -729,10 +729,10 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) { InFlag).getValue(1); if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1) - IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, - CCReg), 0); + IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, + CCReg), 0); else - IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, CCReg), 0); + IntCR = SDValue(CurDAG->getMachineNode(PPC::MFCR, dl, MVT::i32, CCReg), 0); SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31), getI32Imm(31), getI32Imm(31) }; @@ -741,7 +741,7 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) { // Get the specified bit. SDValue Tmp = - SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); + SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); if (Inv) { assert(OtherCondIdx == -1 && "Can't have split plus negation"); return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); @@ -753,7 +753,7 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) { // Get the other bit of the comparison. Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31); SDValue OtherCond = - SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); + SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond); } @@ -806,17 +806,17 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { // Simple value. if (isInt16(Imm)) { // Just the Lo bits. - Result = CurDAG->getTargetNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo)); + Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo)); } else if (Lo) { // Handle the Hi bits. unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8; - Result = CurDAG->getTargetNode(OpC, dl, MVT::i64, getI32Imm(Hi)); + Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi)); // And Lo bits. - Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64, - SDValue(Result, 0), getI32Imm(Lo)); + Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, + SDValue(Result, 0), getI32Imm(Lo)); } else { // Just the Hi bits. - Result = CurDAG->getTargetNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi)); + Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi)); } // If no shift, we're done. @@ -824,19 +824,20 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { // Shift for next step if the upper 32-bits were not zero. if (Imm) { - Result = CurDAG->getTargetNode(PPC::RLDICR, dl, MVT::i64, - SDValue(Result, 0), - getI32Imm(Shift), getI32Imm(63 - Shift)); + Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, + SDValue(Result, 0), + getI32Imm(Shift), + getI32Imm(63 - Shift)); } // Add in the last bits as required. if ((Hi = (Remainder >> 16) & 0xFFFF)) { - Result = CurDAG->getTargetNode(PPC::ORIS8, dl, MVT::i64, - SDValue(Result, 0), getI32Imm(Hi)); + Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64, + SDValue(Result, 0), getI32Imm(Hi)); } if ((Lo = Remainder & 0xFFFF)) { - Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64, - SDValue(Result, 0), getI32Imm(Lo)); + Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, + SDValue(Result, 0), getI32Imm(Lo)); } return Result; @@ -856,18 +857,18 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { if (N->hasOneUse()) return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI, getSmallIPtrImm(0)); - return CurDAG->getTargetNode(Opc, dl, Op.getValueType(), TFI, - getSmallIPtrImm(0)); + return CurDAG->getMachineNode(Opc, dl, Op.getValueType(), TFI, + getSmallIPtrImm(0)); } case PPCISD::MFCR: { SDValue InFlag = N->getOperand(1); // Use MFOCRF if supported. if (PPCSubTarget.isGigaProcessor()) - return CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32, - N->getOperand(0), InFlag); + return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, + N->getOperand(0), InFlag); else - return CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, InFlag); + return CurDAG->getMachineNode(PPC::MFCR, dl, MVT::i32, InFlag); } case ISD::SDIV: { @@ -881,17 +882,17 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { SDValue N0 = N->getOperand(0); if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { SDNode *Op = - CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag, - N0, getI32Imm(Log2_32(Imm))); + CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag, + N0, getI32Imm(Log2_32(Imm))); return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, SDValue(Op, 0), SDValue(Op, 1)); } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { SDNode *Op = - CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag, - N0, getI32Imm(Log2_32(-Imm))); + CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag, + N0, getI32Imm(Log2_32(-Imm))); SDValue PT = - SDValue(CurDAG->getTargetNode(PPC::ADDZE, dl, MVT::i32, - SDValue(Op, 0), SDValue(Op, 1)), + SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32, + SDValue(Op, 0), SDValue(Op, 1)), 0); return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); } @@ -945,9 +946,9 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { SDValue Base = LD->getBasePtr(); SDValue Ops[] = { Offset, Base, Chain }; // FIXME: PPC64 - return CurDAG->getTargetNode(Opcode, dl, LD->getValueType(0), - PPCLowering.getPointerTy(), - MVT::Other, Ops, 3); + return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0), + PPCLowering.getPointerTy(), + MVT::Other, Ops, 3); } else { llvm_unreachable("R+R preindex loads not supported yet!"); } @@ -989,7 +990,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { SDValue Ops[] = { N->getOperand(0).getOperand(0), N->getOperand(0).getOperand(1), getI32Imm(0), getI32Imm(MB),getI32Imm(ME) }; - return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); + return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); } } @@ -1039,8 +1040,8 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { // FIXME: Implement this optzn for PPC64. N->getValueType(0) == MVT::i32) { SDNode *Tmp = - CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, - N->getOperand(0), getI32Imm(~0U)); + CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, + N->getOperand(0), getI32Imm(~0U)); return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(Tmp, 0), N->getOperand(0), SDValue(Tmp, 1)); @@ -1090,8 +1091,8 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { SDValue Chain = N->getOperand(0); SDValue Target = N->getOperand(1); unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; - Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Target, - Chain), 0); + Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target, + Chain), 0); return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain); } } diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 3b05679364d..c7895ad59dc 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -909,7 +909,7 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; - Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base), 0); + Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); return true; } } @@ -1021,7 +1021,7 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; - Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base),0); + Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0); return true; } } @@ -2765,7 +2765,7 @@ PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee, // Set CR6 to true if this is a vararg call. if (isVarArg) { - SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, MVT::i32), 0); + SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0); Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag); InFlag = Chain.getValue(1); } diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 071590f4d7f..a1a4a8ef52c 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -173,12 +173,12 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) { // Set the Y register to the high-part. SDValue TopPart; if (N->getOpcode() == ISD::SDIV) { - TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, dl, MVT::i32, DivLHS, + TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS, CurDAG->getTargetConstant(31, MVT::i32)), 0); } else { TopPart = CurDAG->getRegister(SP::G0, MVT::i32); } - TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, dl, MVT::Flag, TopPart, + TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Flag, TopPart, CurDAG->getRegister(SP::G0, MVT::i32)), 0); // FIXME: Handle div by immediate. @@ -192,8 +192,8 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) { SDValue MulLHS = N->getOperand(0); SDValue MulRHS = N->getOperand(1); unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; - SDNode *Mul = CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::Flag, - MulLHS, MulRHS); + SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Flag, + MulLHS, MulRHS); // The high part is in the Y register. return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1)); return NULL; diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index 6af2f610897..028ee8986a3 100644 --- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -663,37 +663,38 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { // Prepare the dividend SDNode *Dividend; if (is32Bit) - Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0); + Dividend = CurDAG->getMachineNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0); else Dividend = N0.getNode(); // Insert prepared dividend into suitable 'subreg' - SDNode *Tmp = CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF, - dl, ResVT); + SDNode *Tmp = CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF, + dl, ResVT); Dividend = - CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT, - SDValue(Tmp, 0), SDValue(Dividend, 0), - CurDAG->getTargetConstant(subreg_odd, MVT::i32)); + CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT, + SDValue(Tmp, 0), SDValue(Dividend, 0), + CurDAG->getTargetConstant(subreg_odd, MVT::i32)); SDNode *Result; SDValue DivVal = SDValue(Dividend, 0); if (foldedLoad) { SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) }; - Result = CurDAG->getTargetNode(MOpc, dl, ResVT, Ops, array_lengthof(Ops)); + Result = CurDAG->getMachineNode(MOpc, dl, ResVT, + Ops, array_lengthof(Ops)); // Update the chain. ReplaceUses(N1.getValue(1), SDValue(Result, 0)); } else { - Result = CurDAG->getTargetNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1); + Result = CurDAG->getMachineNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1); } // Copy the division (odd subreg) result, if it is needed. if (!Op.getValue(0).use_empty()) { unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd); - SDNode *Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG, - dl, NVT, - SDValue(Result, 0), - CurDAG->getTargetConstant(SubRegIdx, - MVT::i32)); + SDNode *Div = CurDAG->getMachineNode(TargetInstrInfo::EXTRACT_SUBREG, + dl, NVT, + SDValue(Result, 0), + CurDAG->getTargetConstant(SubRegIdx, + MVT::i32)); ReplaceUses(Op.getValue(0), SDValue(Div, 0)); DEBUG(errs().indent(Indent-2) << "=> "; @@ -704,11 +705,11 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { // Copy the remainder (even subreg) result, if it is needed. if (!Op.getValue(1).use_empty()) { unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even); - SDNode *Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG, - dl, NVT, - SDValue(Result, 0), - CurDAG->getTargetConstant(SubRegIdx, - MVT::i32)); + SDNode *Rem = CurDAG->getMachineNode(TargetInstrInfo::EXTRACT_SUBREG, + dl, NVT, + SDValue(Result, 0), + CurDAG->getTargetConstant(SubRegIdx, + MVT::i32)); ReplaceUses(Op.getValue(1), SDValue(Rem, 0)); DEBUG(errs().indent(Indent-2) << "=> "; @@ -751,39 +752,39 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { SDNode *Dividend = N0.getNode(); // Insert prepared dividend into suitable 'subreg' - SDNode *Tmp = CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF, - dl, ResVT); + SDNode *Tmp = CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF, + dl, ResVT); { unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd); Dividend = - CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT, - SDValue(Tmp, 0), SDValue(Dividend, 0), - CurDAG->getTargetConstant(SubRegIdx, MVT::i32)); + CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT, + SDValue(Tmp, 0), SDValue(Dividend, 0), + CurDAG->getTargetConstant(SubRegIdx, MVT::i32)); } // Zero out even subreg - Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0)); + Dividend = CurDAG->getMachineNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0)); SDValue DivVal = SDValue(Dividend, 0); SDNode *Result; if (foldedLoad) { SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) }; - Result = CurDAG->getTargetNode(MOpc, dl,ResVT, - Ops, array_lengthof(Ops)); + Result = CurDAG->getMachineNode(MOpc, dl,ResVT, + Ops, array_lengthof(Ops)); // Update the chain. ReplaceUses(N1.getValue(1), SDValue(Result, 0)); } else { - Result = CurDAG->getTargetNode(Opc, dl, ResVT, DivVal, N1); + Result = CurDAG->getMachineNode(Opc, dl, ResVT, DivVal, N1); } // Copy the division (odd subreg) result, if it is needed. if (!Op.getValue(0).use_empty()) { unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd); - SDNode *Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG, - dl, NVT, - SDValue(Result, 0), - CurDAG->getTargetConstant(SubRegIdx, - MVT::i32)); + SDNode *Div = CurDAG->getMachineNode(TargetInstrInfo::EXTRACT_SUBREG, + dl, NVT, + SDValue(Result, 0), + CurDAG->getTargetConstant(SubRegIdx, + MVT::i32)); ReplaceUses(Op.getValue(0), SDValue(Div, 0)); DEBUG(errs().indent(Indent-2) << "=> "; Result->dump(CurDAG); @@ -793,11 +794,11 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { // Copy the remainder (even subreg) result, if it is needed. if (!Op.getValue(1).use_empty()) { unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even); - SDNode *Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG, - dl, NVT, - SDValue(Result, 0), - CurDAG->getTargetConstant(SubRegIdx, - MVT::i32)); + SDNode *Rem = CurDAG->getMachineNode(TargetInstrInfo::EXTRACT_SUBREG, + dl, NVT, + SDValue(Result, 0), + CurDAG->getTargetConstant(SubRegIdx, + MVT::i32)); ReplaceUses(Op.getValue(1), SDValue(Rem, 0)); DEBUG(errs().indent(Indent-2) << "=> "; Result->dump(CurDAG); diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 21681f9c4d0..addfa9c1332 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -1467,9 +1467,9 @@ SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { return NULL; SDValue LSI = Node->getOperand(4); // MemOperand const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, LSI, Chain}; - return CurDAG->getTargetNode(Opc, Node->getDebugLoc(), - MVT::i32, MVT::i32, MVT::Other, Ops, - array_lengthof(Ops)); + return CurDAG->getMachineNode(Opc, Node->getDebugLoc(), + MVT::i32, MVT::i32, MVT::Other, Ops, + array_lengthof(Ops)); } SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) { @@ -1603,17 +1603,17 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) { } DebugLoc dl = Node->getDebugLoc(); - SDValue Undef = SDValue(CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF, - dl, NVT), 0); + SDValue Undef = SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF, + dl, NVT), 0); SDValue MemOp = CurDAG->getMemOperand(cast(Node)->getMemOperand()); if (isInc || isDec) { SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, MemOp, Chain }; - SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7), 0); + SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0); SDValue RetVals[] = { Undef, Ret }; return CurDAG->getMergeValues(RetVals, 2, dl).getNode(); } else { SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, MemOp, Chain }; - SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8), 0); + SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8), 0); SDValue RetVals[] = { Undef, Ret }; return CurDAG->getMergeValues(RetVals, 2, dl).getNode(); } @@ -1723,14 +1723,14 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), InFlag }; SDNode *CNode = - CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, - array_lengthof(Ops)); + CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, + array_lengthof(Ops)); InFlag = SDValue(CNode, 1); // Update the chain. ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); } else { InFlag = - SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0); + SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, N1, InFlag), 0); } // Copy the low half of the result, if it is needed. @@ -1756,8 +1756,8 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, X86::AX, MVT::i16, InFlag); InFlag = Result.getValue(2); - Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16, - Result, + Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16, + Result, CurDAG->getTargetConstant(8, MVT::i8)), 0); // Then truncate it down to i8. Result = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl, @@ -1846,14 +1846,14 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) }; Move = - SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16, - MVT::Other, Ops, - array_lengthof(Ops)), 0); + SDValue(CurDAG->getMachineNode(X86::MOVZX16rm8, dl, MVT::i16, + MVT::Other, Ops, + array_lengthof(Ops)), 0); Chain = Move.getValue(1); ReplaceUses(N0.getValue(1), Chain); } else { Move = - SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0); + SDValue(CurDAG->getMachineNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0); Chain = CurDAG->getEntryNode(); } Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue()); @@ -1865,27 +1865,27 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { if (isSigned && !signBitIsZero) { // Sign extend the low part into the high part. InFlag = - SDValue(CurDAG->getTargetNode(SExtOpcode, dl, MVT::Flag, InFlag),0); + SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Flag, InFlag),0); } else { // Zero out the high part, effectively zero extending the input. SDValue ClrNode; if (NVT.getSimpleVT() == MVT::i64) { - ClrNode = SDValue(CurDAG->getTargetNode(X86::MOV32r0, dl, MVT::i32), + ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, MVT::i32), 0); // We just did a 32-bit clear, insert it into a 64-bit register to // clear the whole 64-bit reg. SDValue Undef = - SDValue(CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF, - dl, MVT::i64), 0); + SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF, + dl, MVT::i64), 0); SDValue SubRegNo = CurDAG->getTargetConstant(X86::SUBREG_32BIT, MVT::i32); ClrNode = - SDValue(CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, - MVT::i64, Undef, ClrNode, SubRegNo), + SDValue(CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl, + MVT::i64, Undef, ClrNode, SubRegNo), 0); } else { - ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, dl, NVT), 0); + ClrNode = SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0); } InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, HiReg, @@ -1897,14 +1897,14 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), InFlag }; SDNode *CNode = - CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, - array_lengthof(Ops)); + CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, + array_lengthof(Ops)); InFlag = SDValue(CNode, 1); // Update the chain. ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); } else { InFlag = - SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0); + SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, N1, InFlag), 0); } // Copy the division (low) result, if it is needed. @@ -1930,7 +1930,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, X86::AX, MVT::i16, InFlag); InFlag = Result.getValue(2); - Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16, + Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16, Result, CurDAG->getTargetConstant(8, MVT::i8)), 0); @@ -1985,8 +1985,8 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { default: llvm_unreachable("Unsupported TEST operand type!"); } SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); - Reg = SDValue(CurDAG->getTargetNode(X86::COPY_TO_REGCLASS, dl, - Reg.getValueType(), Reg, RC), 0); + Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, + Reg.getValueType(), Reg, RC), 0); } // Extract the l-register. @@ -1994,7 +1994,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { MVT::i8, Reg); // Emit a testb. - return CurDAG->getTargetNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm); + return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm); } // For example, "testl %eax, $2048" to "testb %ah, $8". @@ -2013,8 +2013,8 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { default: llvm_unreachable("Unsupported TEST operand type!"); } SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); - Reg = SDValue(CurDAG->getTargetNode(X86::COPY_TO_REGCLASS, dl, - Reg.getValueType(), Reg, RC), 0); + Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, + Reg.getValueType(), Reg, RC), 0); // Extract the h-register. SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT_HI, dl, @@ -2022,8 +2022,8 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { // Emit a testb. No special NOREX tricks are needed since there's // only one GPR operand! - return CurDAG->getTargetNode(X86::TEST8ri, dl, MVT::i32, - Subreg, ShiftedImm); + return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, + Subreg, ShiftedImm); } // For example, "testl %eax, $32776" to "testw %ax, $32776". @@ -2037,7 +2037,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { MVT::i16, Reg); // Emit a testw. - return CurDAG->getTargetNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm); + return CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm); } // For example, "testq %rax, $268468232" to "testl %eax, $268468232". @@ -2051,7 +2051,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { MVT::i32, Reg); // Emit a testl. - return CurDAG->getTargetNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm); + return CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm); } } break; diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index fb26c5ce4ed..d94b74197d4 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -2588,8 +2588,8 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, EVT VT = *RC->vt_begin(); bool isAligned = (RI.getStackAlignment() >= 16) || RI.needsStackRealignment(MF); - Load = DAG.getTargetNode(getLoadRegOpcode(0, RC, isAligned, TM), dl, - VT, MVT::Other, &AddrOps[0], AddrOps.size()); + Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl, + VT, MVT::Other, &AddrOps[0], AddrOps.size()); NewNodes.push_back(Load); } @@ -2608,8 +2608,8 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, if (Load) BeforeOps.push_back(SDValue(Load, 0)); std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); - SDNode *NewNode= DAG.getTargetNode(Opc, dl, VTs, &BeforeOps[0], - BeforeOps.size()); + SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0], + BeforeOps.size()); NewNodes.push_back(NewNode); // Emit the store instruction. @@ -2621,10 +2621,10 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, AddrOps.push_back(Chain); bool isAligned = (RI.getStackAlignment() >= 16) || RI.needsStackRealignment(MF); - SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(0, DstRC, - isAligned, TM), - dl, MVT::Other, - &AddrOps[0], AddrOps.size()); + SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC, + isAligned, TM), + dl, MVT::Other, + &AddrOps[0], AddrOps.size()); NewNodes.push_back(Store); } diff --git a/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/lib/Target/XCore/XCoreISelDAGToDAG.cpp index 1a5f10291f5..258966cb9f6 100644 --- a/lib/Target/XCore/XCoreISelDAGToDAG.cpp +++ b/lib/Target/XCore/XCoreISelDAGToDAG.cpp @@ -169,7 +169,8 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) { case ISD::Constant: { if (Predicate_immMskBitp(N)) { SDValue MskSize = Transform_msksize_xform(N); - return CurDAG->getTargetNode(XCore::MKMSK_rus, dl, MVT::i32, MskSize); + return CurDAG->getMachineNode(XCore::MKMSK_rus, dl, + MVT::i32, MskSize); } else if (! Predicate_immU16(N)) { unsigned Val = cast(N)->getZExtValue(); @@ -177,20 +178,20 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) { CurDAG->getTargetConstantPool(ConstantInt::get( Type::getInt32Ty(*CurDAG->getContext()), Val), TLI.getPointerTy()); - return CurDAG->getTargetNode(XCore::LDWCP_lru6, dl, MVT::i32, - MVT::Other, CPIdx, - CurDAG->getEntryNode()); + return CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, + MVT::Other, CPIdx, + CurDAG->getEntryNode()); } break; } case ISD::SMUL_LOHI: { // FIXME fold addition into the macc instruction if (!Subtarget.isXS1A()) { - SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, dl, MVT::i32, + SDValue Zero(CurDAG->getMachineNode(XCore::LDC_ru6, dl, MVT::i32, CurDAG->getTargetConstant(0, MVT::i32)), 0); SDValue Ops[] = { Zero, Zero, Op.getOperand(0), Op.getOperand(1) }; - SDNode *ResNode = CurDAG->getTargetNode(XCore::MACCS_l4r, dl, - MVT::i32, MVT::i32, Ops, 4); + SDNode *ResNode = CurDAG->getMachineNode(XCore::MACCS_l4r, dl, + MVT::i32, MVT::i32, Ops, 4); ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1)); ReplaceUses(SDValue(N, 1), SDValue(ResNode, 0)); return NULL; @@ -199,12 +200,12 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) { } case ISD::UMUL_LOHI: { // FIXME fold addition into the macc / lmul instruction - SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, dl, MVT::i32, + SDValue Zero(CurDAG->getMachineNode(XCore::LDC_ru6, dl, MVT::i32, CurDAG->getTargetConstant(0, MVT::i32)), 0); SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), Zero, Zero }; - SDNode *ResNode = CurDAG->getTargetNode(XCore::LMUL_l6r, dl, MVT::i32, - MVT::i32, Ops, 4); + SDNode *ResNode = CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, + MVT::i32, Ops, 4); ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1)); ReplaceUses(SDValue(N, 1), SDValue(ResNode, 0)); return NULL; @@ -213,8 +214,8 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) { if (!Subtarget.isXS1A()) { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), Op.getOperand(2) }; - return CurDAG->getTargetNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32, - Ops, 3); + return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32, + Ops, 3); } break; } @@ -222,8 +223,8 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) { if (!Subtarget.isXS1A()) { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), Op.getOperand(2) }; - return CurDAG->getTargetNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32, - Ops, 3); + return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32, + Ops, 3); } break; } diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index d4cd1661d7f..2488a96ea2a 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -784,7 +784,7 @@ public: EmitResultCode(TreePatternNode *N, std::vector DstRegs, bool InFlagDecled, bool ResNodeDecled, bool LikeLeaf = false, bool isRoot = false) { - // List of arguments of getTargetNode() or SelectNodeTo(). + // List of arguments of getMachineNode() or SelectNodeTo(). std::vector NodeOps; // This is something selected from the pattern we matched. if (!N->getName().empty()) { @@ -1089,7 +1089,7 @@ public: std::string Code = "Opc" + utostr(OpcNo); if (!isRoot || (InputHasChain && !NodeHasChain)) - // For call to "getTargetNode()". + // For call to "getMachineNode()". Code += ", N.getDebugLoc()"; emitOpcode(II.Namespace + "::" + II.TheDef->getName()); @@ -1303,7 +1303,7 @@ public: // would leave users of the chain dangling. // if (!isRoot || (InputHasChain && !NodeHasChain)) { - Code = "CurDAG->getTargetNode(" + Code; + Code = "CurDAG->getMachineNode(" + Code; } else { Code = "CurDAG->SelectNodeTo(N.getNode(), " + Code; }