From: Vikram S. Adve Date: Tue, 27 May 2003 00:05:23 +0000 (+0000) Subject: (1) Added special register class containing (for now) %fsr. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=5f2180c53330502eb2f0f5bf3f21a838ad800906;p=oota-llvm.git (1) Added special register class containing (for now) %fsr. Fixed spilling of %fcc[0-3] which are part of %fsr. (2) Moved some machine-independent reg-class code to class TargetRegInfo from SparcReg{Class,}Info. (3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly() and related functions and flags. Fixed several bugs where only "isDef" was being checked, not "isDefAndUse". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6341 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/InstrSched/SchedGraph.cpp b/lib/CodeGen/InstrSched/SchedGraph.cpp index fa7920309f8..dc27f40812f 100644 --- a/lib/CodeGen/InstrSched/SchedGraph.cpp +++ b/lib/CodeGen/InstrSched/SchedGraph.cpp @@ -525,18 +525,18 @@ SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap, for (unsigned i=0; i < regRefVec.size(); ++i) { SchedGraphNode* node = regRefVec[i].first; unsigned int opNum = regRefVec[i].second; - bool isDef = node->getMachineInstr()->operandIsDefined(opNum); + bool isDef = node->getMachineInstr()->getOperand(opNum).opIsDefOnly(); bool isDefAndUse = - node->getMachineInstr()->operandIsDefinedAndUsed(opNum); + node->getMachineInstr()->getOperand(opNum).opIsDefAndUse(); for (unsigned p=0; p < i; ++p) { SchedGraphNode* prevNode = regRefVec[p].first; if (prevNode != node) { unsigned int prevOpNum = regRefVec[p].second; bool prevIsDef = - prevNode->getMachineInstr()->operandIsDefined(prevOpNum); + prevNode->getMachineInstr()->getOperand(prevOpNum).opIsDefOnly(); bool prevIsDefAndUse = - prevNode->getMachineInstr()->operandIsDefinedAndUsed(prevOpNum); + prevNode->getMachineInstr()->getOperand(prevOpNum).opIsDefAndUse(); if (isDef) { if (prevIsDef) new SchedGraphEdge(prevNode, node, regNum, @@ -612,7 +612,7 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& MI, // for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i) { - switch (MI.getOperandType(i)) + switch (MI.getOperand(i).getType()) { case MachineOperand::MO_VirtualRegister: case MachineOperand::MO_CCRegister: @@ -622,8 +622,8 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& MI, ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI); if (I != valueToDefVecMap.end()) addEdgesForValue(node, I->second, srcI, - MI.operandIsDefined(i), - MI.operandIsDefinedAndUsed(i), target); + MI.getOperand(i).opIsDefOnly(), + MI.getOperand(i).opIsDefAndUse(), target); } break; @@ -646,16 +646,15 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& MI, // value of a Ret instruction. // for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i) - if (! MI.implicitRefIsDefined(i) || - MI.implicitRefIsDefinedAndUsed(i)) + if (MI.getImplicitOp(i).opIsUse() || MI.getImplicitOp(i).opIsDefAndUse()) if (const Instruction *srcI = dyn_cast_or_null(MI.getImplicitRef(i))) { ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI); if (I != valueToDefVecMap.end()) addEdgesForValue(node, I->second, srcI, - MI.implicitRefIsDefined(i), - MI.implicitRefIsDefinedAndUsed(i), target); + MI.getImplicitOp(i).opIsDefOnly(), + MI.getImplicitOp(i).opIsDefAndUse(), target); } } @@ -693,7 +692,8 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, } // ignore all other non-def operands - if (! minstr.operandIsDefined(i)) + if (!minstr.getOperand(i).opIsDefOnly() && + !minstr.getOperand(i).opIsDefAndUse()) continue; // We must be defining a value. @@ -710,7 +710,8 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, // them assumes they must be virtual registers! // for (unsigned i=0, N = minstr.getNumImplicitRefs(); i != N; ++i) - if (minstr.implicitRefIsDefined(i)) + if (minstr.getImplicitOp(i).opIsDefOnly() || + minstr.getImplicitOp(i).opIsDefAndUse()) if (const Instruction* defInstr = dyn_cast_or_null(minstr.getImplicitRef(i))) valueToDefVecMap[defInstr].push_back(std::make_pair(node, -i)); diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp index 3d9758136ce..d38ed274e36 100644 --- a/lib/CodeGen/LiveVariables.cpp +++ b/lib/CodeGen/LiveVariables.cpp @@ -231,7 +231,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { // Process all explicit defs... for (unsigned i = 0; i != NumOperandsToProcess; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.opIsDef() || MO.opIsDefAndUse()) { + if (MO.opIsDefOnly() || MO.opIsDefAndUse()) { if (MO.isVirtualRegister()) { VarInfo &VRInfo = getVarInfo(MO.getReg()); diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index e83ad798d5e..a7a6988fccf 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -94,7 +94,7 @@ MachineInstr::SetMachineOperandVal(unsigned i, if (isDefAndUse) operands[i].flags = MachineOperand::DEFUSEFLAG; else if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i) - operands[i].flags = MachineOperand::DEFFLAG; + operands[i].flags = MachineOperand::DEFONLYFLAG; else operands[i].flags = 0; } @@ -126,7 +126,7 @@ MachineInstr::SetMachineOperandReg(unsigned i, operands[i].regNum = regNum; if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i) - operands[i].flags = MachineOperand::DEFFLAG; + operands[i].flags = MachineOperand::DEFONLYFLAG; else operands[i].flags = 0; @@ -152,7 +152,7 @@ MachineInstr::substituteValue(const Value* oldVal, Value* newVal, bool defsOnly) // Subsitute operands for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O) if (*O == oldVal) - if (!defsOnly || O.isDef()) + if (!defsOnly || !O.isUseOnly()) { O.getMachineOperand().value = newVal; ++numSubst; @@ -161,7 +161,7 @@ MachineInstr::substituteValue(const Value* oldVal, Value* newVal, bool defsOnly) // Subsitute implicit refs for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i) if (getImplicitRef(i) == oldVal) - if (!defsOnly || implicitRefIsDefined(i)) + if (!defsOnly || !getImplicitOp(i).opIsUse()) { getImplicitOp(i).value = newVal; ++numSubst; @@ -281,7 +281,8 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const { unsigned StartOp = 0; // Specialize printing if op#0 is definition - if (getNumOperands() && operandIsDefined(0)) { + if (getNumOperands() && + (getOperand(0).opIsDefOnly() || getOperand(0).opIsDefAndUse())) { ::print(getOperand(0), OS, TM); OS << " = "; ++StartOp; // Don't print this operand again! @@ -289,14 +290,15 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const { OS << TM.getInstrInfo().getName(getOpcode()); for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { + const MachineOperand& mop = getOperand(i); if (i != StartOp) OS << ","; OS << " "; - ::print(getOperand(i), OS, TM); + ::print(mop, OS, TM); - if (operandIsDefinedAndUsed(i)) + if (mop.opIsDefAndUse()) OS << ""; - else if (operandIsDefined(i)) + else if (mop.opIsDefOnly()) OS << ""; } @@ -305,10 +307,10 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const { OS << "\tImplicitRefs: "; for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) { OS << "\t"; - OutputValue(OS, getImplicitRef(i)); - if (implicitRefIsDefinedAndUsed(i)) + OutputValue(OS, getImplicitRef(i)); + if (getImplicitOp(i).opIsDefAndUse()) OS << ""; - else if (implicitRefIsDefined(i)) + else if (getImplicitOp(i).opIsDefOnly()) OS << ""; } } @@ -323,9 +325,9 @@ std::ostream &operator<<(std::ostream& os, const MachineInstr& MI) for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) { os << "\t" << MI.getOperand(i); - if (MI.operandIsDefined(i)) + if (MI.getOperand(i).opIsDefOnly()) os << ""; - if (MI.operandIsDefinedAndUsed(i)) + if (MI.getOperand(i).opIsDefAndUse()) os << ""; } @@ -335,8 +337,8 @@ std::ostream &operator<<(std::ostream& os, const MachineInstr& MI) os << "\tImplicit: "; for (unsigned z=0; z < NumOfImpRefs; z++) { OutputValue(os, MI.getImplicitRef(z)); - if (MI.implicitRefIsDefined(z)) os << ""; - if (MI.implicitRefIsDefinedAndUsed(z)) os << ""; + if (MI.getImplicitOp(z).opIsDefOnly()) os << ""; + if (MI.getImplicitOp(z).opIsDefAndUse()) os << ""; os << "\t"; } } diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp index 11835cb30c5..2149f9044ea 100644 --- a/lib/CodeGen/PHIElimination.cpp +++ b/lib/CodeGen/PHIElimination.cpp @@ -165,7 +165,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) { for (unsigned i = 0, e = PrevInst->getNumOperands(); i != e; ++i) { MachineOperand &MO = PrevInst->getOperand(i); if (MO.isVirtualRegister() && MO.getReg() == IncomingReg) - if (MO.opIsDef() || MO.opIsDefAndUse()) { + if (MO.opIsDefOnly() || MO.opIsDefAndUse()) { HaveNotEmitted = false; break; } diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp index 4839c09751d..06de9bf0240 100644 --- a/lib/CodeGen/PrologEpilogInserter.cpp +++ b/lib/CodeGen/PrologEpilogInserter.cpp @@ -108,7 +108,8 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) { MachineOperand &MO = (*I)->getOperand(i); assert(!MO.isVirtualRegister() && "Register allocation must be performed!"); - if (MO.isPhysicalRegister() && MO.opIsDef()) + if (MO.isPhysicalRegister() && + (MO.opIsDefOnly() || MO.opIsDefAndUse())) ModifiedRegs[MO.getReg()] = true; // Register is modified } ++I; diff --git a/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp b/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp index f3c22e9898b..15584f14a57 100644 --- a/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp +++ b/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp @@ -170,7 +170,7 @@ void LiveRangeInfo::constructLiveRanges() { // for each operand that is defined by the instruction for (MachineInstr::val_op_iterator OpI = MInst->begin(), OpE = MInst->end(); OpI != OpE; ++OpI) - if (OpI.isDef()) { + if (OpI.isDefOnly() || OpI.isDefAndUse()) { const Value *Def = *OpI; bool isCC = (OpI.getMachineOperand().getType() == MachineOperand::MO_CCRegister); @@ -180,7 +180,8 @@ void LiveRangeInfo::constructLiveRanges() { // iterate over implicit MI operands and create a new LR // for each operand that is defined by the instruction for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i) - if (MInst->implicitRefIsDefined(i)) { + if (MInst->getImplicitOp(i).opIsDefOnly() || + MInst->getImplicitOp(i).opIsDefAndUse()) { const Value *Def = MInst->getImplicitRef(i); createOrAddToLiveRange(Def, /*isCC*/ false); } @@ -264,7 +265,7 @@ void LiveRangeInfo::coalesceLRs() // iterate over MI operands to find defs for(MachineInstr::const_val_op_iterator DefI = MI->begin(), DefE = MI->end(); DefI != DefE; ++DefI) { - if (DefI.isDef()) { // iff this operand is a def + if (DefI.isDefOnly() || DefI.isDefAndUse()) { // this operand is modified LiveRange *LROfDef = getLiveRangeForValue( *DefI ); RegClass *RCOfDef = LROfDef->getRegClass(); diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp index 007d0758969..409916fb02b 100644 --- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp +++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp @@ -302,7 +302,7 @@ void PhyRegAlloc::buildInterferenceGraphs() // for (MachineInstr::const_val_op_iterator OpI = MInst->begin(), OpE = MInst->end(); OpI != OpE; ++OpI) { - if (OpI.isDef()) // create a new LR iff this operand is a def + if (OpI.isDefOnly() || OpI.isDefAndUse()) // create a new LR since def addInterference(*OpI, &LVSetAI, isCallInst); // Calculate the spill cost of each live range @@ -322,12 +322,10 @@ void PhyRegAlloc::buildInterferenceGraphs() // instr (currently, only calls have this). // unsigned NumOfImpRefs = MInst->getNumImplicitRefs(); - if ( NumOfImpRefs > 0 ) { - for (unsigned z=0; z < NumOfImpRefs; z++) - if (MInst->implicitRefIsDefined(z) ) - addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst ); - } - + for (unsigned z=0; z < NumOfImpRefs; z++) + if (MInst->getImplicitOp(z).opIsDefOnly() || + MInst->getImplicitOp(z).opIsDefAndUse()) + addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst ); } // for all machine instructions in BB } // for all BBs in function @@ -359,7 +357,7 @@ void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) { for (MachineInstr::const_val_op_iterator It1 = MInst->begin(), ItE = MInst->end(); It1 != ItE; ++It1) { const LiveRange *LROfOp1 = LRI.getLiveRangeForValue(*It1); - assert((LROfOp1 || !It1.isDef()) && "No LR for Def in PSEUDO insruction"); + assert((LROfOp1 || !It1.isUseOnly())&& "No LR for Def in PSEUDO insruction"); MachineInstr::const_val_op_iterator It2 = It1; for (++It2; It2 != ItE; ++It2) { @@ -652,8 +650,8 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR, "Return value of a ret must be handled elsewhere"); MachineOperand& Op = MInst->getOperand(OpNum); - bool isDef = MInst->operandIsDefined(OpNum); - bool isDefAndUse = MInst->operandIsDefinedAndUsed(OpNum); + bool isDef = Op.opIsDefOnly(); + bool isDefAndUse = Op.opIsDefAndUse(); unsigned RegType = MRI.getRegType(LR); int SpillOff = LR->getSpillOffFromFP(); RegClass *RC = LR->getRegClass(); @@ -885,8 +883,8 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, { const MachineOperand& Op = MInst->getOperand(OpNum); - if (MInst->getOperandType(OpNum) == MachineOperand::MO_VirtualRegister || - MInst->getOperandType(OpNum) == MachineOperand::MO_CCRegister) + if (Op.getType() == MachineOperand::MO_VirtualRegister || + Op.getType() == MachineOperand::MO_CCRegister) if (const Value* Val = Op.getVRegValue()) if (MRI.getRegClassIDOfType(Val->getType()) == RC->getID()) if (Op.getAllocatedRegNum() == -1) @@ -987,7 +985,7 @@ void PhyRegAlloc::printMachineCode() else cerr << "(" << Val << ")"; - if (Op.opIsDef() ) + if (Op.opIsDefOnly() || Op.opIsDefAndUse()) cerr << "*"; const LiveRange *LROfVal = LRI.getLiveRangeForValue(Val); diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp index 80100445a46..fed05b7dbbc 100644 --- a/lib/CodeGen/RegAllocLocal.cpp +++ b/lib/CodeGen/RegAllocLocal.cpp @@ -489,7 +489,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { // Loop over all of the operands of the instruction, spilling registers that // are defined, and marking explicit destinations in the PhysRegsUsed map. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) - if ((MI->getOperand(i).opIsDef() || MI->getOperand(i).opIsDefAndUse()) && + if ((MI->getOperand(i).opIsDefOnly() || MI->getOperand(i).opIsDefAndUse()) && MI->getOperand(i).isPhysicalRegister()) { unsigned Reg = MI->getOperand(i).getAllocatedRegNum(); spillPhysReg(MBB, I, Reg); // Spill any existing value in the reg @@ -512,8 +512,8 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { // we need to scavenge a register. // for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) - if (MI->getOperand(i).opIsDef() && - MI->getOperand(i).isVirtualRegister()) { + if ((MI->getOperand(i).opIsDefOnly() || MI->getOperand(i).opIsDefAndUse()) + && MI->getOperand(i).isVirtualRegister()) { unsigned DestVirtReg = MI->getOperand(i).getAllocatedRegNum(); unsigned DestPhysReg; diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index 6b95af82fda..31b637496cf 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -173,7 +173,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { // register in any given instruction unsigned physReg = Virt2PhysRegMap[virtualReg]; if (physReg == 0) { - if (op.opIsDef()) { + if (op.opIsDefOnly() || op.opIsDefAndUse()) { if (TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) { // must be same register number as the first operand // This maps a = b + c into b += c, and saves b into a's spot diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp index fa7920309f8..dc27f40812f 100644 --- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp +++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp @@ -525,18 +525,18 @@ SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap, for (unsigned i=0; i < regRefVec.size(); ++i) { SchedGraphNode* node = regRefVec[i].first; unsigned int opNum = regRefVec[i].second; - bool isDef = node->getMachineInstr()->operandIsDefined(opNum); + bool isDef = node->getMachineInstr()->getOperand(opNum).opIsDefOnly(); bool isDefAndUse = - node->getMachineInstr()->operandIsDefinedAndUsed(opNum); + node->getMachineInstr()->getOperand(opNum).opIsDefAndUse(); for (unsigned p=0; p < i; ++p) { SchedGraphNode* prevNode = regRefVec[p].first; if (prevNode != node) { unsigned int prevOpNum = regRefVec[p].second; bool prevIsDef = - prevNode->getMachineInstr()->operandIsDefined(prevOpNum); + prevNode->getMachineInstr()->getOperand(prevOpNum).opIsDefOnly(); bool prevIsDefAndUse = - prevNode->getMachineInstr()->operandIsDefinedAndUsed(prevOpNum); + prevNode->getMachineInstr()->getOperand(prevOpNum).opIsDefAndUse(); if (isDef) { if (prevIsDef) new SchedGraphEdge(prevNode, node, regNum, @@ -612,7 +612,7 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& MI, // for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i) { - switch (MI.getOperandType(i)) + switch (MI.getOperand(i).getType()) { case MachineOperand::MO_VirtualRegister: case MachineOperand::MO_CCRegister: @@ -622,8 +622,8 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& MI, ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI); if (I != valueToDefVecMap.end()) addEdgesForValue(node, I->second, srcI, - MI.operandIsDefined(i), - MI.operandIsDefinedAndUsed(i), target); + MI.getOperand(i).opIsDefOnly(), + MI.getOperand(i).opIsDefAndUse(), target); } break; @@ -646,16 +646,15 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& MI, // value of a Ret instruction. // for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i) - if (! MI.implicitRefIsDefined(i) || - MI.implicitRefIsDefinedAndUsed(i)) + if (MI.getImplicitOp(i).opIsUse() || MI.getImplicitOp(i).opIsDefAndUse()) if (const Instruction *srcI = dyn_cast_or_null(MI.getImplicitRef(i))) { ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI); if (I != valueToDefVecMap.end()) addEdgesForValue(node, I->second, srcI, - MI.implicitRefIsDefined(i), - MI.implicitRefIsDefinedAndUsed(i), target); + MI.getImplicitOp(i).opIsDefOnly(), + MI.getImplicitOp(i).opIsDefAndUse(), target); } } @@ -693,7 +692,8 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, } // ignore all other non-def operands - if (! minstr.operandIsDefined(i)) + if (!minstr.getOperand(i).opIsDefOnly() && + !minstr.getOperand(i).opIsDefAndUse()) continue; // We must be defining a value. @@ -710,7 +710,8 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, // them assumes they must be virtual registers! // for (unsigned i=0, N = minstr.getNumImplicitRefs(); i != N; ++i) - if (minstr.implicitRefIsDefined(i)) + if (minstr.getImplicitOp(i).opIsDefOnly() || + minstr.getImplicitOp(i).opIsDefAndUse()) if (const Instruction* defInstr = dyn_cast_or_null(minstr.getImplicitRef(i))) valueToDefVecMap[defInstr].push_back(std::make_pair(node, -i)); diff --git a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp index f3c22e9898b..15584f14a57 100644 --- a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp +++ b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp @@ -170,7 +170,7 @@ void LiveRangeInfo::constructLiveRanges() { // for each operand that is defined by the instruction for (MachineInstr::val_op_iterator OpI = MInst->begin(), OpE = MInst->end(); OpI != OpE; ++OpI) - if (OpI.isDef()) { + if (OpI.isDefOnly() || OpI.isDefAndUse()) { const Value *Def = *OpI; bool isCC = (OpI.getMachineOperand().getType() == MachineOperand::MO_CCRegister); @@ -180,7 +180,8 @@ void LiveRangeInfo::constructLiveRanges() { // iterate over implicit MI operands and create a new LR // for each operand that is defined by the instruction for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i) - if (MInst->implicitRefIsDefined(i)) { + if (MInst->getImplicitOp(i).opIsDefOnly() || + MInst->getImplicitOp(i).opIsDefAndUse()) { const Value *Def = MInst->getImplicitRef(i); createOrAddToLiveRange(Def, /*isCC*/ false); } @@ -264,7 +265,7 @@ void LiveRangeInfo::coalesceLRs() // iterate over MI operands to find defs for(MachineInstr::const_val_op_iterator DefI = MI->begin(), DefE = MI->end(); DefI != DefE; ++DefI) { - if (DefI.isDef()) { // iff this operand is a def + if (DefI.isDefOnly() || DefI.isDefAndUse()) { // this operand is modified LiveRange *LROfDef = getLiveRangeForValue( *DefI ); RegClass *RCOfDef = LROfDef->getRegClass(); diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp index 007d0758969..409916fb02b 100644 --- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp +++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp @@ -302,7 +302,7 @@ void PhyRegAlloc::buildInterferenceGraphs() // for (MachineInstr::const_val_op_iterator OpI = MInst->begin(), OpE = MInst->end(); OpI != OpE; ++OpI) { - if (OpI.isDef()) // create a new LR iff this operand is a def + if (OpI.isDefOnly() || OpI.isDefAndUse()) // create a new LR since def addInterference(*OpI, &LVSetAI, isCallInst); // Calculate the spill cost of each live range @@ -322,12 +322,10 @@ void PhyRegAlloc::buildInterferenceGraphs() // instr (currently, only calls have this). // unsigned NumOfImpRefs = MInst->getNumImplicitRefs(); - if ( NumOfImpRefs > 0 ) { - for (unsigned z=0; z < NumOfImpRefs; z++) - if (MInst->implicitRefIsDefined(z) ) - addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst ); - } - + for (unsigned z=0; z < NumOfImpRefs; z++) + if (MInst->getImplicitOp(z).opIsDefOnly() || + MInst->getImplicitOp(z).opIsDefAndUse()) + addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst ); } // for all machine instructions in BB } // for all BBs in function @@ -359,7 +357,7 @@ void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) { for (MachineInstr::const_val_op_iterator It1 = MInst->begin(), ItE = MInst->end(); It1 != ItE; ++It1) { const LiveRange *LROfOp1 = LRI.getLiveRangeForValue(*It1); - assert((LROfOp1 || !It1.isDef()) && "No LR for Def in PSEUDO insruction"); + assert((LROfOp1 || !It1.isUseOnly())&& "No LR for Def in PSEUDO insruction"); MachineInstr::const_val_op_iterator It2 = It1; for (++It2; It2 != ItE; ++It2) { @@ -652,8 +650,8 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR, "Return value of a ret must be handled elsewhere"); MachineOperand& Op = MInst->getOperand(OpNum); - bool isDef = MInst->operandIsDefined(OpNum); - bool isDefAndUse = MInst->operandIsDefinedAndUsed(OpNum); + bool isDef = Op.opIsDefOnly(); + bool isDefAndUse = Op.opIsDefAndUse(); unsigned RegType = MRI.getRegType(LR); int SpillOff = LR->getSpillOffFromFP(); RegClass *RC = LR->getRegClass(); @@ -885,8 +883,8 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, { const MachineOperand& Op = MInst->getOperand(OpNum); - if (MInst->getOperandType(OpNum) == MachineOperand::MO_VirtualRegister || - MInst->getOperandType(OpNum) == MachineOperand::MO_CCRegister) + if (Op.getType() == MachineOperand::MO_VirtualRegister || + Op.getType() == MachineOperand::MO_CCRegister) if (const Value* Val = Op.getVRegValue()) if (MRI.getRegClassIDOfType(Val->getType()) == RC->getID()) if (Op.getAllocatedRegNum() == -1) @@ -987,7 +985,7 @@ void PhyRegAlloc::printMachineCode() else cerr << "(" << Val << ")"; - if (Op.opIsDef() ) + if (Op.opIsDefOnly() || Op.opIsDefAndUse()) cerr << "*"; const LiveRange *LROfVal = LRI.getLiveRangeForValue(Val);