From: Chris Lattner <sabre@nondot.org>
Date: Tue, 24 Dec 2002 00:04:01 +0000 (+0000)
Subject: Changes to allow for a configurable target machine that allows big endian and/or... 
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=5bcd95c57feb92b9036636d98157f1f11e432b6d;p=oota-llvm.git

Changes to allow for a configurable target machine that allows big endian and/or long pointer operation


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5131 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index 0eb71da814a..18656af4138 100644
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -5,11 +5,11 @@
 //===----------------------------------------------------------------------===//
 
 #include "X86TargetMachine.h"
+#include "X86.h"
 #include "llvm/Transforms/Scalar.h"
 #include "llvm/Target/TargetMachineImpls.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/PassManager.h"
-#include "X86.h"
 #include "Support/CommandLine.h"
 #include "Support/Statistic.h"
 #include <iostream>
@@ -17,17 +17,26 @@
 namespace {
   cl::opt<bool> NoLocalRA("no-local-ra",
                           cl::desc("Use Simple RA instead of Local RegAlloc"));
+  cl::opt<bool> PrintCode("print-machineinstrs",
+			  cl::desc("Print generated machine code"));
 }
 
 // allocateX86TargetMachine - Allocate and return a subclass of TargetMachine
 // that implements the X86 backend.
 //
-TargetMachine *allocateX86TargetMachine() { return new X86TargetMachine(); }
+TargetMachine *allocateX86TargetMachine(unsigned Configuration) {
+  return new X86TargetMachine(Configuration);
+}
 
 
 /// X86TargetMachine ctor - Create an ILP32 architecture model
 ///
-X86TargetMachine::X86TargetMachine() : TargetMachine("X86", 1, 4, 4, 4) {
+X86TargetMachine::X86TargetMachine(unsigned Config)
+  : TargetMachine("X86", 
+		  (Config & TM::EndianMask) == TM::LittleEndian,
+		  1, 4, 
+		  (Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4,
+		  (Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4) {
 }
 
 
@@ -46,7 +55,8 @@ bool X86TargetMachine::addPassesToJITCompile(PassManager &PM) {
   // TODO: optional optimizations go here
 
   // Print the instruction selected machine code...
-  DEBUG(PM.add(createMachineFunctionPrinterPass()));
+  if (PrintCode)
+    PM.add(createMachineFunctionPrinterPass());
 
   // Perform register allocation to convert to a concrete x86 representation
   if (NoLocalRA)
@@ -58,7 +68,8 @@ bool X86TargetMachine::addPassesToJITCompile(PassManager &PM) {
   // PM.add(createMachineFunctionPrinterPass());
 
   // Print the register-allocated code
-  DEBUG(PM.add(createX86CodePrinterPass(*this, std::cerr)));
+  if (PrintCode)
+    PM.add(createX86CodePrinterPass(*this, std::cerr));
 
   return false; // success!
 }
diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h
index 029f834027b..15b5d4950fb 100644
--- a/lib/Target/X86/X86TargetMachine.h
+++ b/lib/Target/X86/X86TargetMachine.h
@@ -13,7 +13,7 @@
 class X86TargetMachine : public TargetMachine {
   X86InstrInfo instrInfo;
 public:
-  X86TargetMachine();
+  X86TargetMachine(unsigned Configuration);
 
   virtual const X86InstrInfo     &getInstrInfo() const { return instrInfo; }
   virtual const MachineSchedInfo &getSchedInfo() const { abort(); }