From: Daniel Sanders Date: Mon, 23 Sep 2013 12:33:38 +0000 (+0000) Subject: Partially revert r191192: Fix -Wunused-variable error when assertions are disabled... X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=57ebcb28a63d8646fd8fd69cfd9e6766066e342f;p=oota-llvm.git Partially revert r191192: Fix -Wunused-variable error when assertions are disabled and -Werror is in use. An unrelated change crept in because 'svn revert' isn't recursive by default. The unrelated changes have been reverted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191193 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index 9532c9d7275..41bf01744b5 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -162,17 +162,14 @@ addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); setOperationAction(ISD::ADD, Ty, Legal); - setOperationAction(ISD::AND, Ty, Legal); setOperationAction(ISD::CTLZ, Ty, Legal); setOperationAction(ISD::MUL, Ty, Legal); - setOperationAction(ISD::OR, Ty, Legal); setOperationAction(ISD::SDIV, Ty, Legal); setOperationAction(ISD::SHL, Ty, Legal); setOperationAction(ISD::SRA, Ty, Legal); setOperationAction(ISD::SRL, Ty, Legal); setOperationAction(ISD::SUB, Ty, Legal); setOperationAction(ISD::UDIV, Ty, Legal); - setOperationAction(ISD::XOR, Ty, Legal); } // Enable MSA support for the given floating-point type and Register class. @@ -898,8 +895,6 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_addv_w: case Intrinsic::mips_addv_d: return lowerMSABinaryIntr(Op, DAG, ISD::ADD); - case Intrinsic::mips_and_v: - return lowerMSABinaryIntr(Op, DAG, ISD::AND); case Intrinsic::mips_bnz_b: case Intrinsic::mips_bnz_h: case Intrinsic::mips_bnz_w: @@ -964,8 +959,6 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_nlzc_w: case Intrinsic::mips_nlzc_d: return lowerMSAUnaryIntr(Op, DAG, ISD::CTLZ); - case Intrinsic::mips_or_v: - return lowerMSABinaryIntr(Op, DAG, ISD::OR); case Intrinsic::mips_sll_b: case Intrinsic::mips_sll_h: case Intrinsic::mips_sll_w: @@ -986,8 +979,6 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_subv_w: case Intrinsic::mips_subv_d: return lowerMSABinaryIntr(Op, DAG, ISD::SUB); - case Intrinsic::mips_xor_v: - return lowerMSABinaryIntr(Op, DAG, ISD::XOR); } }