From: Richard Sandiford Date: Wed, 13 Nov 2013 16:57:53 +0000 (+0000) Subject: [SystemZ] Add the general form of BCR X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=541c5de2fb57b2f459f0ec49f33a0ecce3532acd;p=oota-llvm.git [SystemZ] Add the general form of BCR At the moment this is just the MC support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194585 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp b/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp index fc7fbf98f59..fc3c38d2f34 100644 --- a/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp +++ b/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp @@ -48,14 +48,11 @@ extern "C" void LLVMInitializeSystemZDisassembler() { } static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, - const unsigned *Regs, - bool isAddress = false) { + const unsigned *Regs) { assert(RegNo < 16 && "Invalid register"); - if (!isAddress || RegNo) { - RegNo = Regs[RegNo]; - if (RegNo == 0) - return MCDisassembler::Fail; - } + RegNo = Regs[RegNo]; + if (RegNo == 0) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateReg(RegNo)); return MCDisassembler::Success; } @@ -87,7 +84,7 @@ static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, true); + return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs); } static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo, diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index a318aa1b73a..eb416036bf6 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -67,6 +67,8 @@ let isBranch = 1, isTerminator = 1, Uses = [CC] in { "brc\t$R1, $I2", []>; def AsmBRCL : InstRIL<0xC04, (outs), (ins uimm8zx4:$R1, brtarget32:$I2), "brcl\t$R1, $I2", []>; + def AsmBCR : InstRR<0x07, (outs), (ins uimm8zx4:$R1, GR64:$R2), + "bcr\t$R1, $R2", []>; } // Fused compare-and-branch instructions. As for normal branches, @@ -117,6 +119,7 @@ multiclass CondExtendedMnemonic ccmask, string name> { "j"##name##"\t$I2", []>; def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg"##name##"\t$I2", []>; + def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), "b"##name##"r\t$R2", []>; } def LOCR : FixedCondUnaryRRF<"locr"##name, 0xB9F2, GR32, GR32, ccmask>; def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>; diff --git a/test/MC/Disassembler/SystemZ/insns.txt b/test/MC/Disassembler/SystemZ/insns.txt index 982b35ffad5..78d348d7c19 100644 --- a/test/MC/Disassembler/SystemZ/insns.txt +++ b/test/MC/Disassembler/SystemZ/insns.txt @@ -790,6 +790,51 @@ # CHECK: basr %r15, %r1 0x0d 0xf1 +# CHECK: bcr 0, %r14 +0x07 0x0e + +# CHECK: bor %r13 +0x07 0x1d + +# CHECK: bhr %r12 +0x07 0x2c + +# CHECK: bnler %r11 +0x07 0x3b + +# CHECK: blr %r10 +0x07 0x4a + +# CHECK: bnher %r9 +0x07 0x59 + +# CHECK: blhr %r8 +0x07 0x68 + +# CHECK: bner %r7 +0x07 0x77 + +# CHECK: ber %r6 +0x07 0x86 + +# CHECK: bnlhr %r5 +0x07 0x95 + +# CHECK: bher %r4 +0x07 0xa4 + +# CHECK: bnlr %r3 +0x07 0xb3 + +# CHECK: bler %r2 +0x07 0xc2 + +# CHECK: bnhr %r1 +0x07 0xd1 + +# CHECK: bnor %r0 +0x07 0xe0 + # CHECK: br %r1 0x07 0xf1 diff --git a/test/MC/SystemZ/insn-bad.s b/test/MC/SystemZ/insn-bad.s index 64453a55816..2a3fb98c2b1 100644 --- a/test/MC/SystemZ/insn-bad.s +++ b/test/MC/SystemZ/insn-bad.s @@ -256,6 +256,14 @@ ay %r0, -524289 ay %r0, 524288 +#CHECK: error: invalid operand +#CHECK: bcr -1, %r1 +#CHECK: error: invalid operand +#CHECK: bcr 16, %r1 + + bcr -1, %r1 + bcr 16, %r1 + #CHECK: error: offset out of range #CHECK: bras %r0, -0x100002 #CHECK: error: offset out of range diff --git a/test/MC/SystemZ/insn-good.s b/test/MC/SystemZ/insn-good.s index 20410505020..23bd68a2f5d 100644 --- a/test/MC/SystemZ/insn-good.s +++ b/test/MC/SystemZ/insn-good.s @@ -527,11 +527,102 @@ basr %r14,%r9 basr %r15,%r1 +#CHECK: bcr 0, %r0 # encoding: [0x07,0x00] +#CHECK: bcr 0, %r15 # encoding: [0x07,0x0f] + bcr 0, %r0 + bcr 0, %r15 + +#CHECK: bcr 1, %r7 # encoding: [0x07,0x17] +#CHECK: bor %r15 # encoding: [0x07,0x1f] + + bcr 1, %r7 + bor %r15 + +#CHECK: bcr 2, %r7 # encoding: [0x07,0x27] +#CHECK: bhr %r15 # encoding: [0x07,0x2f] + + bcr 2, %r7 + bhr %r15 + +#CHECK: bcr 3, %r7 # encoding: [0x07,0x37] +#CHECK: bnler %r15 # encoding: [0x07,0x3f] + + bcr 3, %r7 + bnler %r15 + +#CHECK: bcr 4, %r7 # encoding: [0x07,0x47] +#CHECK: blr %r15 # encoding: [0x07,0x4f] + + bcr 4, %r7 + blr %r15 + +#CHECK: bcr 5, %r7 # encoding: [0x07,0x57] +#CHECK: bnher %r15 # encoding: [0x07,0x5f] + + bcr 5, %r7 + bnher %r15 + +#CHECK: bcr 6, %r7 # encoding: [0x07,0x67] +#CHECK: blhr %r15 # encoding: [0x07,0x6f] + + bcr 6, %r7 + blhr %r15 + +#CHECK: bcr 7, %r7 # encoding: [0x07,0x77] +#CHECK: bner %r15 # encoding: [0x07,0x7f] + + bcr 7, %r7 + bner %r15 + +#CHECK: bcr 8, %r7 # encoding: [0x07,0x87] +#CHECK: ber %r15 # encoding: [0x07,0x8f] + + bcr 8, %r7 + ber %r15 + +#CHECK: bcr 9, %r7 # encoding: [0x07,0x97] +#CHECK: bnlhr %r15 # encoding: [0x07,0x9f] + + bcr 9, %r7 + bnlhr %r15 + +#CHECK: bcr 10, %r7 # encoding: [0x07,0xa7] +#CHECK: bher %r15 # encoding: [0x07,0xaf] + + bcr 10, %r7 + bher %r15 + +#CHECK: bcr 11, %r7 # encoding: [0x07,0xb7] +#CHECK: bnlr %r15 # encoding: [0x07,0xbf] + + bcr 11, %r7 + bnlr %r15 + +#CHECK: bcr 12, %r7 # encoding: [0x07,0xc7] +#CHECK: bler %r15 # encoding: [0x07,0xcf] + + bcr 12, %r7 + bler %r15 + +#CHECK: bcr 13, %r7 # encoding: [0x07,0xd7] +#CHECK: bnhr %r15 # encoding: [0x07,0xdf] + + bcr 13, %r7 + bnhr %r15 + +#CHECK: bcr 14, %r7 # encoding: [0x07,0xe7] +#CHECK: bnor %r15 # encoding: [0x07,0xef] + + bcr 14, %r7 + bnor %r15 + +#CHECK: bcr 15, %r7 # encoding: [0x07,0xf7] #CHECK: br %r1 # encoding: [0x07,0xf1] #CHECK: br %r14 # encoding: [0x07,0xfe] #CHECK: br %r15 # encoding: [0x07,0xff] + bcr 15, %r7 br %r1 br %r14 br %r15