From: Jim Grosbach <grosbach@apple.com>
Date: Wed, 1 Dec 2010 21:09:40 +0000 (+0000)
Subject: Use the correct fixup type for ARM VLDR*
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=5177f79c378b47e38bed5ac05ba4b597f31b864e;p=oota-llvm.git

Use the correct fixup type for ARM VLDR*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120604 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index d35a1c6fb33..7a7864f75ef 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -658,7 +658,7 @@ getAddrModeS1OpValue(const MCInst &MI, unsigned OpIdx,
   return getAddrModeSOpValue(MI, OpIdx, 1);
 }
 
-/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
+/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
 uint32_t ARMMCCodeEmitter::
 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
                     SmallVectorImpl<MCFixup> &Fixups) const {
@@ -676,7 +676,7 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
 
     assert(MO.isExpr() && "Unexpected machine operand type!");
     const MCExpr *Expr = MO.getExpr();
-    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
+    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
     Fixups.push_back(MCFixup::Create(0, Expr, Kind));
 
     ++MCNumCPRelocations;