From: Chris Lattner <sabre@nondot.org>
Date: Tue, 17 Oct 2006 21:24:15 +0000 (+0000)
Subject: Fix CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=50662beab7cc6394a0d6524d16fe7de1d5192196;p=oota-llvm.git

Fix CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31019 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 997820dd64b..aa6f4ae98c5 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3689,7 +3689,7 @@ SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
             cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
           // If this is (X^1) == 0/1, swap the RHS and eliminate the xor.  We
           // can only do this if the top bits are known zero.
-          if (TLI.MaskedValueIsZero(N1, 
+          if (TLI.MaskedValueIsZero(N0, 
                                     MVT::getIntVTBitMask(N0.getValueType())-1)){
             // Okay, get the un-inverted input value.
             SDOperand Val;