From: Evan Cheng <evan.cheng@apple.com>
Date: Tue, 18 May 2010 20:07:47 +0000 (+0000)
Subject: Continuously refine the register class of REG_SEQUENCE def with all the source regist... 
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=5012f9b82525121c28709ad7a2cc27818a38c213;p=oota-llvm.git

Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104051 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 2f8f255b5b5..16eb8a72adc 100644
--- a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -551,11 +551,12 @@ void InstrEmitter::EmitRegSequence(SDNode *Node,
       const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
       const TargetRegisterClass *SRC =
         TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
-      //getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0));
       if (!SRC)
         llvm_unreachable("Invalid subregister index in REG_SEQUENCE");
-      if (SRC != RC)
+      if (SRC != RC) {
         MRI->setRegClass(NewVReg, SRC);
+        RC = SRC;
+      }
     }
     AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
                IsClone, IsCloned);