From: Colin LeMahieu Date: Wed, 28 Jan 2015 17:06:40 +0000 (+0000) Subject: [Hexagon] Replacing intrinsics for halfword adds and max/min word/dword. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=4b032d5f15ccc146a45a6118f0549f723faf5da0;p=oota-llvm.git [Hexagon] Replacing intrinsics for halfword adds and max/min word/dword. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227322 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Support/Windows/Signals.inc b/lib/Support/Windows/Signals.inc index ad740c79a7a..35ba6f8e1bb 100644 --- a/lib/Support/Windows/Signals.inc +++ b/lib/Support/Windows/Signals.inc @@ -279,14 +279,6 @@ void sys::DontRemoveFileOnSignal(StringRef Filename) { /// PrintStackTraceOnErrorSignal - When an error signal (such as SIBABRT or /// SIGSEGV) is delivered to the process, print a stack trace and then exit. void sys::PrintStackTraceOnErrorSignal() { - // Don't pop up any dialog boxes. - // We're already handling writing a "something went wrong" message. - _set_abort_behavior(0, _WRITE_ABORT_MSG); - // Disable Dr. Watson. - _set_abort_behavior(0, _CALL_REPORTFAULT); - // Disable standard error dialog box. - SetErrorMode(SEM_FAILCRITICALERRORS | SEM_NOGPFAULTERRORBOX); - RegisterHandler(); LeaveCriticalSection(&CriticalSection); } diff --git a/lib/Target/Hexagon/HexagonIntrinsics.td b/lib/Target/Hexagon/HexagonIntrinsics.td index f58e7655ed1..ee30a0b88a0 100644 --- a/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/lib/Target/Hexagon/HexagonIntrinsics.td @@ -255,6 +255,61 @@ def : T_PRR_pat ; def : T_PRR_pat ; def : T_PRR_pat ; + +//===----------------------------------------------------------------------===// +// Add/Subtract halfword +// Rd=add(Rt.L,Rs.[HL])[:sat] +// Rd=sub(Rt.L,Rs.[HL])[:sat] +// Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16] +// Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16] +//===----------------------------------------------------------------------===// + +//Rd=add(Rt.L,Rs.[LH]) +def : T_RR_pat ; +def : T_RR_pat ; + +//Rd=add(Rt.L,Rs.[LH]):sat +def : T_RR_pat ; +def : T_RR_pat ; + +//Rd=sub(Rt.L,Rs.[LH]) +def : T_RR_pat ; +def : T_RR_pat ; + +//Rd=sub(Rt.L,Rs.[LH]):sat +def : T_RR_pat ; +def : T_RR_pat ; + +//Rd=add(Rt.[LH],Rs.[LH]):<<16 +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; + +//Rd=sub(Rt.[LH],Rs.[LH]):<<16 +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; + +//Rd=add(Rt.[LH],Rs.[LH]):sat:<<16 +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; + +//Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16 +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; +def : T_RR_pat ; + +// ALU64 / ALU / min max +def : T_RR_pat; +def : T_RR_pat; +def : T_RR_pat; +def : T_RR_pat; + /******************************************************************** * ALU32/ALU * *********************************************************************/ @@ -2300,37 +2355,6 @@ def HEXAGON_A2_addp: def HEXAGON_A2_addsat: si_ALU64_sisi_sat <"add", int_hexagon_A2_addsat>; -// ALU64 / ALU / Add halfword. -// Even though the definition says hl, it should be lh - -//so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits. -def HEXAGON_A2_addh_l16_hl: - si_ALU64_sisi_l16_lh <"add", int_hexagon_A2_addh_l16_hl>; -def HEXAGON_A2_addh_l16_ll: - si_ALU64_sisi_l16_ll <"add", int_hexagon_A2_addh_l16_ll>; - -def HEXAGON_A2_addh_l16_sat_hl: - si_ALU64_sisi_l16_sat_lh <"add", int_hexagon_A2_addh_l16_sat_hl>; -def HEXAGON_A2_addh_l16_sat_ll: - si_ALU64_sisi_l16_sat_ll <"add", int_hexagon_A2_addh_l16_sat_ll>; - -def HEXAGON_A2_addh_h16_hh: - si_ALU64_sisi_h16_hh <"add", int_hexagon_A2_addh_h16_hh>; -def HEXAGON_A2_addh_h16_hl: - si_ALU64_sisi_h16_hl <"add", int_hexagon_A2_addh_h16_hl>; -def HEXAGON_A2_addh_h16_lh: - si_ALU64_sisi_h16_lh <"add", int_hexagon_A2_addh_h16_lh>; -def HEXAGON_A2_addh_h16_ll: - si_ALU64_sisi_h16_ll <"add", int_hexagon_A2_addh_h16_ll>; - -def HEXAGON_A2_addh_h16_sat_hh: - si_ALU64_sisi_h16_sat_hh <"add", int_hexagon_A2_addh_h16_sat_hh>; -def HEXAGON_A2_addh_h16_sat_hl: - si_ALU64_sisi_h16_sat_hl <"add", int_hexagon_A2_addh_h16_sat_hl>; -def HEXAGON_A2_addh_h16_sat_lh: - si_ALU64_sisi_h16_sat_lh <"add", int_hexagon_A2_addh_h16_sat_lh>; -def HEXAGON_A2_addh_h16_sat_ll: - si_ALU64_sisi_h16_sat_ll <"add", int_hexagon_A2_addh_h16_sat_ll>; - // ALU64 / ALU / Compare. def HEXAGON_C2_cmpeqp: qi_ALU64_didi <"cmp.eq", int_hexagon_C2_cmpeqp>; @@ -2347,55 +2371,12 @@ def HEXAGON_A2_orp: def HEXAGON_A2_xorp: di_ALU64_didi <"xor", int_hexagon_A2_xorp>; -// ALU64 / ALU / Maximum. -def HEXAGON_A2_max: - si_ALU64_sisi <"max", int_hexagon_A2_max>; -def HEXAGON_A2_maxu: - si_ALU64_sisi <"maxu", int_hexagon_A2_maxu>; - -// ALU64 / ALU / Minimum. -def HEXAGON_A2_min: - si_ALU64_sisi <"min", int_hexagon_A2_min>; -def HEXAGON_A2_minu: - si_ALU64_sisi <"minu", int_hexagon_A2_minu>; - // ALU64 / ALU / Subtract. def HEXAGON_A2_subp: di_ALU64_didi <"sub", int_hexagon_A2_subp>; def HEXAGON_A2_subsat: si_ALU64_sisi_sat <"sub", int_hexagon_A2_subsat>; -// ALU64 / ALU / Subtract halfword. -// Even though the definition says hl, it should be lh - -//so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits. -def HEXAGON_A2_subh_l16_hl: - si_ALU64_sisi_l16_lh <"sub", int_hexagon_A2_subh_l16_hl>; -def HEXAGON_A2_subh_l16_ll: - si_ALU64_sisi_l16_ll <"sub", int_hexagon_A2_subh_l16_ll>; - -def HEXAGON_A2_subh_l16_sat_hl: - si_ALU64_sisi_l16_sat_lh <"sub", int_hexagon_A2_subh_l16_sat_hl>; -def HEXAGON_A2_subh_l16_sat_ll: - si_ALU64_sisi_l16_sat_ll <"sub", int_hexagon_A2_subh_l16_sat_ll>; - -def HEXAGON_A2_subh_h16_hh: - si_ALU64_sisi_h16_hh <"sub", int_hexagon_A2_subh_h16_hh>; -def HEXAGON_A2_subh_h16_hl: - si_ALU64_sisi_h16_hl <"sub", int_hexagon_A2_subh_h16_hl>; -def HEXAGON_A2_subh_h16_lh: - si_ALU64_sisi_h16_lh <"sub", int_hexagon_A2_subh_h16_lh>; -def HEXAGON_A2_subh_h16_ll: - si_ALU64_sisi_h16_ll <"sub", int_hexagon_A2_subh_h16_ll>; - -def HEXAGON_A2_subh_h16_sat_hh: - si_ALU64_sisi_h16_sat_hh <"sub", int_hexagon_A2_subh_h16_sat_hh>; -def HEXAGON_A2_subh_h16_sat_hl: - si_ALU64_sisi_h16_sat_hl <"sub", int_hexagon_A2_subh_h16_sat_hl>; -def HEXAGON_A2_subh_h16_sat_lh: - si_ALU64_sisi_h16_sat_lh <"sub", int_hexagon_A2_subh_h16_sat_lh>; -def HEXAGON_A2_subh_h16_sat_ll: - si_ALU64_sisi_h16_sat_ll <"sub", int_hexagon_A2_subh_h16_sat_ll>; - // ALU64 / ALU / Transfer register. def HEXAGON_A2_tfrp: di_ALU64_di <"", int_hexagon_A2_tfrp>;