From: Chad Rosier Date: Tue, 26 Nov 2013 22:17:37 +0000 (+0000) Subject: [AArch64] Add support for NEON scalar floating-point to integer convert X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=48f115aabf3f94743de7d231f6f8a3902d673551;p=oota-llvm.git [AArch64] Add support for NEON scalar floating-point to integer convert instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195788 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/IR/IntrinsicsAArch64.td b/include/llvm/IR/IntrinsicsAArch64.td index 172a5695684..36e9cb652a0 100644 --- a/include/llvm/IR/IntrinsicsAArch64.td +++ b/include/llvm/IR/IntrinsicsAArch64.td @@ -54,6 +54,10 @@ def int_aarch64_neon_fcvtas : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; def int_aarch64_neon_fcvtau : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; +def int_aarch64_neon_fcvtzs : + Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; +def int_aarch64_neon_fcvtzu : + Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; // Vector maxNum (Floating Point) def int_aarch64_neon_vmaxnm : Neon_2Arg_Intrinsic; diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td index 206ccd697a3..272bc34754f 100644 --- a/lib/Target/AArch64/AArch64InstrNEON.td +++ b/lib/Target/AArch64/AArch64InstrNEON.td @@ -4245,7 +4245,7 @@ multiclass NeonI_Scalar2SameMisc_SD_size opcode, } multiclass NeonI_Scalar2SameMisc_D_size opcode, string asmop> { - def dd: NeonI_Scalar2SameMisc_size; + def dd : NeonI_Scalar2SameMisc_size; } multiclass NeonI_Scalar2SameMisc_BHSD_size opcode, string asmop> @@ -4255,6 +4255,9 @@ multiclass NeonI_Scalar2SameMisc_BHSD_size opcode, string asmop> def ss : NeonI_Scalar2SameMisc_size; } +class NeonI_Scalar2SameMisc_fcvtxn_D_size opcode, string asmop> + : NeonI_Scalar2SameMisc_size; + multiclass NeonI_Scalar2SameMisc_narrow_HSD_size opcode, string asmop> { def bh : NeonI_Scalar2SameMisc_size; @@ -4281,6 +4284,20 @@ multiclass NeonI_Scalar2SameMisc_accum_BHSD_size opcode, } } +class Neon_Scalar2SameMisc_fcvtxn_D_size_patterns + : Pat<(v1f32 (opnode (v1f64 FPR64:$Rn))), + (INSTD FPR64:$Rn)>; + +multiclass Neon_Scalar2SameMisc_fcvt_SD_size_patterns { + def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn))), + (INSTS FPR32:$Rn)>; + def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))), + (INSTD FPR64:$Rn)>; +} + multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns; +// Scalar Floating-point Converts +def FCVTXN : NeonI_Scalar2SameMisc_fcvtxn_D_size<0b1, 0b10110, "fcvtxn">; +def : Neon_Scalar2SameMisc_fcvtxn_D_size_patterns; + +defm FCVTNS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11010, "fcvtns">; +defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns; + +defm FCVTNU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11010, "fcvtnu">; +defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns; + +defm FCVTMS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11011, "fcvtms">; +defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns; + +defm FCVTMU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11011, "fcvtmu">; +defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns; + +defm FCVTAS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11100, "fcvtas">; +defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns; + +defm FCVTAU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11100, "fcvtau">; +defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns; + +defm FCVTPS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11010, "fcvtps">; +defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns; + +defm FCVTPU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11010, "fcvtpu">; +defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns; + +defm FCVTZS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11011, "fcvtzs">; +defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns; + +defm FCVTZU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11011, "fcvtzu">; +defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns; + // Scalar Floating-point Reciprocal Estimate defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">; defm : Neon_Scalar2SameMisc_SD_size_patterns undef, double %a, i32 0 + %vcvtf1.i = tail call <1 x float> @llvm.aarch64.neon.fcvtxn.v1f32.v1f64(<1 x double> %vcvtf.i) + %0 = extractelement <1 x float> %vcvtf1.i, i32 0 + ret float %0 +} + +declare <1 x float> @llvm.aarch64.neon.fcvtxn.v1f32.v1f64(<1 x double>) + +define i32 @test_vcvtass(float %a) { +; CHECK: test_vcvtass +; CHECK: fcvtas {{s[0-9]}}, {{s[0-9]}} +entry: + %vcvtas.i = insertelement <1 x float> undef, float %a, i32 0 + %vcvtas1.i = tail call <1 x i32> @llvm.aarch64.neon.fcvtas.v1i32.v1f32(<1 x float> %vcvtas.i) + %0 = extractelement <1 x i32> %vcvtas1.i, i32 0 + ret i32 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.fcvtas.v1i32.v1f32(<1 x float>) + +define i64 @test_test_vcvtasd(double %a) { +; CHECK: test_test_vcvtasd +; CHECK: fcvtas {{d[0-9]}}, {{d[0-9]}} +entry: + %vcvtas.i = insertelement <1 x double> undef, double %a, i32 0 + %vcvtas1.i = tail call <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double> %vcvtas.i) + %0 = extractelement <1 x i64> %vcvtas1.i, i32 0 + ret i64 %0 +} + +declare <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double>) + +define i32 @test_vcvtaus(float %a) { +; CHECK: test_vcvtaus +; CHECK: fcvtau {{s[0-9]}}, {{s[0-9]}} +entry: + %vcvtau.i = insertelement <1 x float> undef, float %a, i32 0 + %vcvtau1.i = tail call <1 x i32> @llvm.aarch64.neon.fcvtau.v1i32.v1f32(<1 x float> %vcvtau.i) + %0 = extractelement <1 x i32> %vcvtau1.i, i32 0 + ret i32 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.fcvtau.v1i32.v1f32(<1 x float>) + +define i64 @test_vcvtaud(double %a) { +; CHECK: test_vcvtaud +; CHECK: fcvtau {{d[0-9]}}, {{d[0-9]}} +entry: + %vcvtau.i = insertelement <1 x double> undef, double %a, i32 0 + %vcvtau1.i = tail call <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double> %vcvtau.i) + %0 = extractelement <1 x i64> %vcvtau1.i, i32 0 + ret i64 %0 +} + +declare <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double>) + +define i32 @test_vcvtmss(float %a) { +; CHECK: test_vcvtmss +; CHECK: fcvtms {{s[0-9]}}, {{s[0-9]}} +entry: + %vcvtms.i = insertelement <1 x float> undef, float %a, i32 0 + %vcvtms1.i = tail call <1 x i32> @llvm.aarch64.neon.fcvtms.v1i32.v1f32(<1 x float> %vcvtms.i) + %0 = extractelement <1 x i32> %vcvtms1.i, i32 0 + ret i32 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.fcvtms.v1i32.v1f32(<1 x float>) + +define i64 @test_vcvtmd_s64_f64(double %a) { +; CHECK: test_vcvtmd_s64_f64 +; CHECK: fcvtms {{d[0-9]}}, {{d[0-9]}} +entry: + %vcvtms.i = insertelement <1 x double> undef, double %a, i32 0 + %vcvtms1.i = tail call <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double> %vcvtms.i) + %0 = extractelement <1 x i64> %vcvtms1.i, i32 0 + ret i64 %0 +} + +declare <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double>) + +define i32 @test_vcvtmus(float %a) { +; CHECK: test_vcvtmus +; CHECK: fcvtmu {{s[0-9]}}, {{s[0-9]}} +entry: + %vcvtmu.i = insertelement <1 x float> undef, float %a, i32 0 + %vcvtmu1.i = tail call <1 x i32> @llvm.aarch64.neon.fcvtmu.v1i32.v1f32(<1 x float> %vcvtmu.i) + %0 = extractelement <1 x i32> %vcvtmu1.i, i32 0 + ret i32 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.fcvtmu.v1i32.v1f32(<1 x float>) + +define i64 @test_vcvtmud(double %a) { +; CHECK: test_vcvtmud +; CHECK: fcvtmu {{d[0-9]}}, {{d[0-9]}} +entry: + %vcvtmu.i = insertelement <1 x double> undef, double %a, i32 0 + %vcvtmu1.i = tail call <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double> %vcvtmu.i) + %0 = extractelement <1 x i64> %vcvtmu1.i, i32 0 + ret i64 %0 +} + +declare <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double>) + +define i32 @test_vcvtnss(float %a) { +; CHECK: test_vcvtnss +; CHECK: fcvtns {{s[0-9]}}, {{s[0-9]}} +entry: + %vcvtns.i = insertelement <1 x float> undef, float %a, i32 0 + %vcvtns1.i = tail call <1 x i32> @llvm.aarch64.neon.fcvtns.v1i32.v1f32(<1 x float> %vcvtns.i) + %0 = extractelement <1 x i32> %vcvtns1.i, i32 0 + ret i32 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.fcvtns.v1i32.v1f32(<1 x float>) + +define i64 @test_vcvtnd_s64_f64(double %a) { +; CHECK: test_vcvtnd_s64_f64 +; CHECK: fcvtns {{d[0-9]}}, {{d[0-9]}} +entry: + %vcvtns.i = insertelement <1 x double> undef, double %a, i32 0 + %vcvtns1.i = tail call <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.v1f64(<1 x double> %vcvtns.i) + %0 = extractelement <1 x i64> %vcvtns1.i, i32 0 + ret i64 %0 +} + +declare <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.v1f64(<1 x double>) + +define i32 @test_vcvtnus(float %a) { +; CHECK: test_vcvtnus +; CHECK: fcvtnu {{s[0-9]}}, {{s[0-9]}} +entry: + %vcvtnu.i = insertelement <1 x float> undef, float %a, i32 0 + %vcvtnu1.i = tail call <1 x i32> @llvm.aarch64.neon.fcvtnu.v1i32.v1f32(<1 x float> %vcvtnu.i) + %0 = extractelement <1 x i32> %vcvtnu1.i, i32 0 + ret i32 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.fcvtnu.v1i32.v1f32(<1 x float>) + +define i64 @test_vcvtnud(double %a) { +; CHECK: test_vcvtnud +; CHECK: fcvtnu {{d[0-9]}}, {{d[0-9]}} +entry: + %vcvtnu.i = insertelement <1 x double> undef, double %a, i32 0 + %vcvtnu1.i = tail call <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.v1f64(<1 x double> %vcvtnu.i) + %0 = extractelement <1 x i64> %vcvtnu1.i, i32 0 + ret i64 %0 +} + +declare <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.v1f64(<1 x double>) + +define i32 @test_vcvtpss(float %a) { +; CHECK: test_vcvtpss +; CHECK: fcvtps {{s[0-9]}}, {{s[0-9]}} +entry: + %vcvtps.i = insertelement <1 x float> undef, float %a, i32 0 + %vcvtps1.i = tail call <1 x i32> @llvm.aarch64.neon.fcvtps.v1i32.v1f32(<1 x float> %vcvtps.i) + %0 = extractelement <1 x i32> %vcvtps1.i, i32 0 + ret i32 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.fcvtps.v1i32.v1f32(<1 x float>) + +define i64 @test_vcvtpd_s64_f64(double %a) { +; CHECK: test_vcvtpd_s64_f64 +; CHECK: fcvtps {{d[0-9]}}, {{d[0-9]}} +entry: + %vcvtps.i = insertelement <1 x double> undef, double %a, i32 0 + %vcvtps1.i = tail call <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double> %vcvtps.i) + %0 = extractelement <1 x i64> %vcvtps1.i, i32 0 + ret i64 %0 +} + +declare <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double>) + +define i32 @test_vcvtpus(float %a) { +; CHECK: test_vcvtpus +; CHECK: fcvtpu {{s[0-9]}}, {{s[0-9]}} +entry: + %vcvtpu.i = insertelement <1 x float> undef, float %a, i32 0 + %vcvtpu1.i = tail call <1 x i32> @llvm.aarch64.neon.fcvtpu.v1i32.v1f32(<1 x float> %vcvtpu.i) + %0 = extractelement <1 x i32> %vcvtpu1.i, i32 0 + ret i32 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.fcvtpu.v1i32.v1f32(<1 x float>) + +define i64 @test_vcvtpud(double %a) { +; CHECK: test_vcvtpud +; CHECK: fcvtpu {{d[0-9]}}, {{d[0-9]}} +entry: + %vcvtpu.i = insertelement <1 x double> undef, double %a, i32 0 + %vcvtpu1.i = tail call <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.v1f64(<1 x double> %vcvtpu.i) + %0 = extractelement <1 x i64> %vcvtpu1.i, i32 0 + ret i64 %0 +} + +declare <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.v1f64(<1 x double>) + +define i32 @test_vcvtss(float %a) { +; CHECK: test_vcvtss +; CHECK: fcvtzs {{s[0-9]}}, {{s[0-9]}} +entry: + %vcvtzs.i = insertelement <1 x float> undef, float %a, i32 0 + %vcvtzs1.i = tail call <1 x i32> @llvm.aarch64.neon.fcvtzs.v1i32.v1f32(<1 x float> %vcvtzs.i) + %0 = extractelement <1 x i32> %vcvtzs1.i, i32 0 + ret i32 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.fcvtzs.v1i32.v1f32(<1 x float>) + +define i64 @test_vcvtd_s64_f64(double %a) { +; CHECK: test_vcvtd_s64_f64 +; CHECK: fcvtzs {{d[0-9]}}, {{d[0-9]}} +entry: + %vcvzs.i = insertelement <1 x double> undef, double %a, i32 0 + %vcvzs1.i = tail call <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.v1f64(<1 x double> %vcvzs.i) + %0 = extractelement <1 x i64> %vcvzs1.i, i32 0 + ret i64 %0 +} + +declare <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.v1f64(<1 x double>) + +define i32 @test_vcvtus(float %a) { +; CHECK: test_vcvtus +; CHECK: fcvtzu {{s[0-9]}}, {{s[0-9]}} +entry: + %vcvtzu.i = insertelement <1 x float> undef, float %a, i32 0 + %vcvtzu1.i = tail call <1 x i32> @llvm.aarch64.neon.fcvtzu.v1i32.v1f32(<1 x float> %vcvtzu.i) + %0 = extractelement <1 x i32> %vcvtzu1.i, i32 0 + ret i32 %0 +} + +declare <1 x i32> @llvm.aarch64.neon.fcvtzu.v1i32.v1f32(<1 x float>) + +define i64 @test_vcvtud(double %a) { +; CHECK: test_vcvtud +; CHECK: fcvtzu {{d[0-9]}}, {{d[0-9]}} +entry: + %vcvtzu.i = insertelement <1 x double> undef, double %a, i32 0 + %vcvtzu1.i = tail call <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.v1f64(<1 x double> %vcvtzu.i) + %0 = extractelement <1 x i64> %vcvtzu1.i, i32 0 + ret i64 %0 +} + +declare <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.v1f64(<1 x double>) diff --git a/test/MC/AArch64/neon-diagnostics.s b/test/MC/AArch64/neon-diagnostics.s index 74719e09a53..7bc76a08291 100644 --- a/test/MC/AArch64/neon-diagnostics.s +++ b/test/MC/AArch64/neon-diagnostics.s @@ -7141,3 +7141,163 @@ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b // CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Lower Precision Narrow, Rounding To +// Odd +//---------------------------------------------------------------------- + + fcvtxn s0, s1 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtxn s0, s1 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding To Nearest +// With Ties To Away +//---------------------------------------------------------------------- + + fcvtas s0, d0 + fcvtas d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtas s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtas d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding To +// Nearest With Ties To Away +//---------------------------------------------------------------------- + + fcvtau s0, d0 + fcvtau d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtau s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtau d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding Toward +// Minus Infinity +//---------------------------------------------------------------------- + + fcvtms s0, d0 + fcvtms d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtms s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtms d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +// Minus Infinity +//---------------------------------------------------------------------- + + fcvtmu s0, d0 + fcvtmu d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtmu s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtmu d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding To Nearest +// With Ties To Even +//---------------------------------------------------------------------- + + fcvtns s0, d0 + fcvtns d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtns s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtns d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding To +// Nearest With Ties To Even +//---------------------------------------------------------------------- + + fcvtnu s0, d0 + fcvtnu d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtnu s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtnu d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding Toward +// Positive Infinity +//---------------------------------------------------------------------- + + fcvtps s0, d0 + fcvtps d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtps s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtps d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +// Positive Infinity +//---------------------------------------------------------------------- + + fcvtpu s0, d0 + fcvtpu d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtpu s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtpu d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding Toward Zero +//---------------------------------------------------------------------- + + fcvtzs s0, d0 + fcvtzs d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +// Zero +//---------------------------------------------------------------------- + + fcvtzu s0, d0 + fcvtzu d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzu s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzu d0, s0 +// CHECK-ERROR: ^ diff --git a/test/MC/AArch64/neon-scalar-cvt.s b/test/MC/AArch64/neon-scalar-cvt.s index 54774097c0b..97416daf080 100644 --- a/test/MC/AArch64/neon-scalar-cvt.s +++ b/test/MC/AArch64/neon-scalar-cvt.s @@ -61,3 +61,121 @@ // CHECK: fcvtzu s21, s12, #1 // encoding: [0x95,0xfd,0x3f,0x7f] // CHECK: fcvtzu d21, d12, #1 // encoding: [0x95,0xfd,0x7f,0x7f] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Lower Precision Narrow, Rounding To +// Odd +//---------------------------------------------------------------------- + + fcvtxn s22, d13 + +// CHECK: fcvtxn s22, d13 // encoding: [0xb6,0x69,0x61,0x7e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding To Nearest +// With Ties To Away +//---------------------------------------------------------------------- + + fcvtas s12, s13 + fcvtas d21, d14 + +// CHECK: fcvtas s12, s13 // encoding: [0xac,0xc9,0x21,0x5e] +// CHECK: fcvtas d21, d14 // encoding: [0xd5,0xc9,0x61,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding To +// Nearest With Ties To Away +//---------------------------------------------------------------------- + + fcvtau s12, s13 + fcvtau d21, d14 + +// CHECK: fcvtau s12, s13 // encoding: [0xac,0xc9,0x21,0x7e] +// CHECK: fcvtau d21, d14 // encoding: [0xd5,0xc9,0x61,0x7e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding Toward +// Minus Infinity +//---------------------------------------------------------------------- + + fcvtms s22, s13 + fcvtms d21, d14 + +// CHECK: fcvtms s22, s13 // encoding: [0xb6,0xb9,0x21,0x5e] +// CHECK: fcvtms d21, d14 // encoding: [0xd5,0xb9,0x61,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +// Minus Infinity +//---------------------------------------------------------------------- + + fcvtmu s12, s13 + fcvtmu d21, d14 + +// CHECK: fcvtmu s12, s13 // encoding: [0xac,0xb9,0x21,0x7e] +// CHECK: fcvtmu d21, d14 // encoding: [0xd5,0xb9,0x61,0x7e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding To Nearest +// With Ties To Even +//---------------------------------------------------------------------- + + fcvtns s22, s13 + fcvtns d21, d14 + +// CHECK: fcvtns s22, s13 // encoding: [0xb6,0xa9,0x21,0x5e] +// CHECK: fcvtns d21, d14 // encoding: [0xd5,0xa9,0x61,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding To +// Nearest With Ties To Even +//---------------------------------------------------------------------- + + fcvtnu s12, s13 + fcvtnu d21, d14 + +// CHECK: fcvtnu s12, s13 // encoding: [0xac,0xa9,0x21,0x7e] +// CHECK: fcvtnu d21, d14 // encoding: [0xd5,0xa9,0x61,0x7e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding Toward +// Positive Infinity +//---------------------------------------------------------------------- + + fcvtps s22, s13 + fcvtps d21, d14 + +// CHECK: fcvtps s22, s13 // encoding: [0xb6,0xa9,0xa1,0x5e] +// CHECK: fcvtps d21, d14 // encoding: [0xd5,0xa9,0xe1,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +// Positive Infinity +//---------------------------------------------------------------------- + + fcvtpu s12, s13 + fcvtpu d21, d14 + +// CHECK: fcvtpu s12, s13 // encoding: [0xac,0xa9,0xa1,0x7e] +// CHECK: fcvtpu d21, d14 // encoding: [0xd5,0xa9,0xe1,0x7e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding Toward Zero +//---------------------------------------------------------------------- + + fcvtzs s12, s13 + fcvtzs d21, d14 + +// CHECK: fcvtzs s12, s13 // encoding: [0xac,0xb9,0xa1,0x5e] +// CHECK: fcvtzs d21, d14 // encoding: [0xd5,0xb9,0xe1,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +// Zero +//---------------------------------------------------------------------- + + fcvtzu s12, s13 + fcvtzu d21, d14 + +// CHECK: fcvtzu s12, s13 // encoding: [0xac,0xb9,0xa1,0x7e] +// CHECK: fcvtzu d21, d14 // encoding: [0xd5,0xb9,0xe1,0x7e] diff --git a/test/MC/Disassembler/AArch64/neon-instructions.txt b/test/MC/Disassembler/AArch64/neon-instructions.txt index 03974806cd9..3ed228a641c 100644 --- a/test/MC/Disassembler/AArch64/neon-instructions.txt +++ b/test/MC/Disassembler/AArch64/neon-instructions.txt @@ -2510,3 +2510,102 @@ # CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b # CHECK: tbx v16.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Lower Precision Narrow, Rounding To +# Odd +#---------------------------------------------------------------------- +# CHECK: fcvtxn s22, d13 +0xb6,0x69,0x61,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Signed Integer, Rounding To Nearest +# With Ties To Away +#---------------------------------------------------------------------- +# CHECK: fcvtas s12, s13 +# CHECK: fcvtas d21, d14 + +0xac,0xc9,0x21,0x5e +0xd5,0xc9,0x61,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Unsigned Integer, Rounding To +# Nearest With Ties To Away +#---------------------------------------------------------------------- +# CHECK: fcvtau s12, s13 +# CHECK: fcvtau d21, d14 +0xac,0xc9,0x21,0x7e +0xd5,0xc9,0x61,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Signed Integer, Rounding Toward +# Minus Infinity +#---------------------------------------------------------------------- +# CHECK: fcvtms s22, s13 +# CHECK: fcvtms d21, d14 +0xb6,0xb9,0x21,0x5e +0xd5,0xb9,0x61,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +# Minus Infinity +#---------------------------------------------------------------------- +# CHECK: fcvtmu s12, s13 +# CHECK: fcvtmu d21, d14 +0xac,0xb9,0x21,0x7e +0xd5,0xb9,0x61,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Signed Integer, Rounding To Nearest +# With Ties To Even +#---------------------------------------------------------------------- + +# CHECK: fcvtns s22, s13 +# CHECK: fcvtns d21, d14 + +0xb6,0xa9,0x21,0x5e +0xd5,0xa9,0x61,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Unsigned Integer, Rounding To +# Nearest With Ties To Even +#---------------------------------------------------------------------- + +# CHECK: fcvtnu s12, s13 +# CHECK: fcvtnu d21, d14 +0xac,0xa9,0x21,0x7e +0xd5,0xa9,0x61,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Signed Integer, Rounding Toward +# Positive Infinity +#---------------------------------------------------------------------- +# CHECK: fcvtps s22, s13 +# CHECK: fcvtps d21, d14 +0xb6,0xa9,0xa1,0x5e +0xd5,0xa9,0xe1,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +# Positive Infinity +#---------------------------------------------------------------------- +# CHECK: fcvtpu s12, s13 +# CHECK: fcvtpu d21, d14 +0xac,0xa9,0xa1,0x7e +0xd5,0xa9,0xe1,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Signed Integer, Rounding Toward Zero +#---------------------------------------------------------------------- +# CHECK: fcvtzs s12, s13 +# CHECK: fcvtzs d21, d14 +0xac,0xb9,0xa1,0x5e +0xd5,0xb9,0xe1,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +# Zero +#---------------------------------------------------------------------- +# CHECK: fcvtzu s12, s13 +# CHECK: fcvtzu d21, d14 +0xac,0xb9,0xa1,0x7e +0xd5,0xb9,0xe1,0x7e