From: Chris Lattner <sabre@nondot.org>
Date: Thu, 29 Sep 2005 06:44:39 +0000 (+0000)
Subject: Fix two bugs in my patch earlier today that broke int->fp conversion on X86.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=473a99073cc29f59809a0d5dfee11f5e9e6ad2b7;p=oota-llvm.git

Fix two bugs in my patch earlier today that broke int->fp conversion on X86.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23522 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 918f8258390..12599089f2c 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -261,7 +261,7 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
   }
 
   NeedsAnotherIteration = true;
-  return DAG.getNode(ISD::ADD, DestVT, Tmp1, FudgeInReg);
+  return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
 }
 
 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
@@ -2810,7 +2810,7 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
       FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
                                   CPIdx, DAG.getSrcValue(NULL), MVT::f32);
     }
-    return DAG.getNode(ISD::ADD, DestTy, SignedConv, FudgeInReg);
+    return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
   }
 
   // Check to see if the target has a custom way to lower this.  If so, use it.