From: Roman Divacky <rdivacky@freebsd.org>
Date: Mon, 2 Apr 2012 15:49:30 +0000 (+0000)
Subject: Implement the SVR4 byval alignment for aggregates. Fixing a FIXME.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=466958c2a04a74de99efd3d7e0d5bd81cdf1e1fe;p=oota-llvm.git

Implement the SVR4 byval alignment for aggregates. Fixing a FIXME.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153876 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 96b7074aa02..746fc23c211 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -446,7 +446,16 @@ unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
   // Darwin passes everything on 4 byte boundary.
   if (TM.getSubtarget<PPCSubtarget>().isDarwin())
     return 4;
-  // FIXME SVR4 TBD
+
+  // 16byte and wider vectors are passed on 16byte boundary.
+  if (VectorType *VTy = dyn_cast<VectorType>(Ty))
+    if (VTy->getBitWidth() >= 128)
+      return 16;
+
+  // The rest is 8 on PPC64 and 4 on PPC32 boundary.
+   if (PPCSubTarget.isPPC64())
+     return 8;
+
   return 4;
 }