From: Owen Anderson <resistor@mac.com>
Date: Fri, 31 Jan 2014 00:51:43 +0000 (+0000)
Subject: DAGCombine should not produce ISD::OR nodes after operation legalization if they... 
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=45b07e157c0a22fec8148e0cc7243a029d4a061e;p=oota-llvm.git

DAGCombine should not produce ISD::OR nodes after operation legalization if they're not legal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200503 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index e96a7aaaf08..7dd85a8be74 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1544,8 +1544,10 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
 
       // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
       // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
-      if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
-        return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
+      if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero){
+        if (!LegalOperations || TLI.isOperationLegal(ISD::OR, VT))
+          return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
+      }
     }
   }