From: Yakir Yang Date: Mon, 28 Mar 2016 02:48:19 +0000 (+0800) Subject: drm: bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 X-Git-Tag: firefly_0821_release~2957 X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=455be1a2af76dbc2a3d3d808bf0d88a26c2a98ad;p=firefly-linux-kernel-4.4.55.git drm: bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced by commit 45970584ead0a5dfe27a6edef198ede536ad37ba (FROMLIST: drm: bridge: analogix/dp: add some rk3288 special registers setting). The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1 BIT 0, not BIT 1. Change-Id: I8cb806d23144697225f626aaa2af19e6379dfe51 Signed-off-by: Yakir Yang --- diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h index 337912b0aeab..88d56ad5c010 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h @@ -163,8 +163,8 @@ #define HSYNC_POLARITY_CFG (0x1 << 0) /* ANALOGIX_DP_PLL_REG_1 */ -#define REF_CLK_24M (0x1 << 1) -#define REF_CLK_27M (0x0 << 1) +#define REF_CLK_24M (0x1 << 0) +#define REF_CLK_27M (0x0 << 0) /* ANALOGIX_DP_LANE_MAP */ #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)