From: Chris Lattner Date: Sat, 13 Nov 2004 20:03:48 +0000 (+0000) Subject: Compile: X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=44205cadba047b1322a235b8cd1be5f4423a8f93;p=oota-llvm.git Compile: long long X3_2(long long Y) { return Y+Y; } int X(int Y) { return Y+Y; } into: X3_2: movl 4(%esp), %eax movl 8(%esp), %edx addl %eax, %eax adcl %edx, %edx ret X: movl 4(%esp), %eax addl %eax, %eax ret instead of: X3_2: movl 4(%esp), %eax movl 8(%esp), %edx shldl $1, %eax, %edx shll $1, %eax ret X: movl 4(%esp), %eax shll $1, %eax ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17705 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp index fbdc7c51e92..e5cf618fc10 100644 --- a/lib/Target/X86/X86ISelSimple.cpp +++ b/lib/Target/X86/X86ISelSimple.cpp @@ -2925,7 +2925,12 @@ void X86ISel::emitShiftOperation(MachineBasicBlock *MBB, // if (ConstantUInt *CUI = dyn_cast(ShiftAmount)) { unsigned Amount = CUI->getValue(); - if (Amount < 32) { + if (Amount == 1) { // X << 1 == X+X + BuildMI(*MBB, IP, X86::ADD32rr, 2, + DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(*MBB, IP, X86::ADC32rr, 2, + DestReg+1).addReg(SrcReg+1).addReg(SrcReg+1); + } else if (Amount < 32) { const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned]; if (isLeftShift) { BuildMI(*MBB, IP, Opc[3], 3, @@ -3018,9 +3023,14 @@ void X86ISel::emitShiftOperation(MachineBasicBlock *MBB, // The shift amount is constant, guaranteed to be a ubyte. Get its value. assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?"); - const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned]; - BuildMI(*MBB, IP, Opc[Class], 2, - DestReg).addReg(SrcReg).addImm(CUI->getValue()); + if (CUI->getValue() == 1 && isLeftShift) { // X << 1 -> X+X + static const int AddOpC[] = { X86::ADD8rr, X86::ADD16rr, X86::ADD32rr }; + BuildMI(*MBB, IP, AddOpC[Class], 2,DestReg).addReg(SrcReg).addReg(SrcReg); + } else { + const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned]; + BuildMI(*MBB, IP, Opc[Class], 2, + DestReg).addReg(SrcReg).addImm(CUI->getValue()); + } } else { // The shift amount is non-constant. unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP); BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg);