From: Brian Gaeke <gaeke@uiuc.edu>
Date: Thu, 8 Jul 2004 09:08:22 +0000 (+0000)
Subject: Add floating-point branches and compares.  Compares don't complete
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=4185d03dc5290550f0bad33764f3971ec9a74132;p=oota-llvm.git

Add floating-point branches and compares.  Compares don't complete
until the next cycle, and there's no interlock, so they effectively
have a delay slot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14686 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Sparc/DelaySlotFiller.cpp b/lib/Target/Sparc/DelaySlotFiller.cpp
index c6606b64532..78d5baa1f9b 100644
--- a/lib/Target/Sparc/DelaySlotFiller.cpp
+++ b/lib/Target/Sparc/DelaySlotFiller.cpp
@@ -68,6 +68,26 @@ static bool hasDelaySlot (unsigned Opcode) {
     case V8::CALL:
     case V8::JMPLrr:
     case V8::RETL:
+    case V8::FBA:
+    case V8::FBN:
+    case V8::FBU:
+    case V8::FBG:
+    case V8::FBUG:
+    case V8::FBL:
+    case V8::FBUL:
+    case V8::FBLG:
+    case V8::FBNE:
+    case V8::FBE:
+    case V8::FBUE:
+    case V8::FBGE:
+    case V8::FBUGE:
+    case V8::FBLE:
+    case V8::FBULE:
+    case V8::FBO:
+    case V8::FCMPS:
+    case V8::FCMPD:
+    case V8::FCMPES:
+    case V8::FCMPED:
       return true;
     default:
       return false;
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index d2c679d0a66..3cc43dc1eda 100644
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -163,6 +163,31 @@ def BLEU : BranchV8<0b0100, "bleu">;
 def BCC  : BranchV8<0b1101, "bcc">;
 def BCS  : BranchV8<0b0101, "bcs">;
 
+// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
+
+// floating-point conditional branch class:
+class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> {
+  let isBranch = 1;
+  let isTerminator = 1;
+}
+
+def FBA  : FPBranchV8<0b1000, "fba">;
+def FBN  : FPBranchV8<0b0000, "fbn">;
+def FBU  : FPBranchV8<0b0111, "fbu">;
+def FBG  : FPBranchV8<0b0110, "fbg">;
+def FBUG : FPBranchV8<0b0101, "fbug">;
+def FBL  : FPBranchV8<0b0100, "fbl">;
+def FBUL : FPBranchV8<0b0011, "fbul">;
+def FBLG : FPBranchV8<0b0010, "fblg">;
+def FBNE : FPBranchV8<0b0001, "fbne">;
+def FBE  : FPBranchV8<0b1001, "fbe">;
+def FBUE : FPBranchV8<0b1010, "fbue">;
+def FBGE : FPBranchV8<0b1011, "fbge">;
+def FBUGE: FPBranchV8<0b1100, "fbuge">;
+def FBLE : FPBranchV8<0b1101, "fble">;
+def FBULE: FPBranchV8<0b1110, "fbule">;
+def FBO  : FPBranchV8<0b1111, "fbo">;
+
 // Section B.24 - Call and Link Instruction, p. 125
 // This is the only Format 1 instruction
 def CALL : InstV8 {
@@ -207,3 +232,10 @@ def FSMULD : F3_3<2, 0b110100, 0b001101001, "fsmuld">;
 def FDIVS  : F3_3<2, 0b110100, 0b001001101, "fdivs">;
 def FDIVD  : F3_3<2, 0b110100, 0b001001110, "fdivd">;
 
+// Floating-point Compare Instructions, p. 148
+// Note: the 2nd template arg is different for these guys
+def FCMPS  : F3_3<2, 0b110101, 0b001010001, "fcmps">;
+def FCMPD  : F3_3<2, 0b110101, 0b001010010, "fcmpd">;
+def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">;
+def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">;
+
diff --git a/lib/Target/SparcV8/DelaySlotFiller.cpp b/lib/Target/SparcV8/DelaySlotFiller.cpp
index c6606b64532..78d5baa1f9b 100644
--- a/lib/Target/SparcV8/DelaySlotFiller.cpp
+++ b/lib/Target/SparcV8/DelaySlotFiller.cpp
@@ -68,6 +68,26 @@ static bool hasDelaySlot (unsigned Opcode) {
     case V8::CALL:
     case V8::JMPLrr:
     case V8::RETL:
+    case V8::FBA:
+    case V8::FBN:
+    case V8::FBU:
+    case V8::FBG:
+    case V8::FBUG:
+    case V8::FBL:
+    case V8::FBUL:
+    case V8::FBLG:
+    case V8::FBNE:
+    case V8::FBE:
+    case V8::FBUE:
+    case V8::FBGE:
+    case V8::FBUGE:
+    case V8::FBLE:
+    case V8::FBULE:
+    case V8::FBO:
+    case V8::FCMPS:
+    case V8::FCMPD:
+    case V8::FCMPES:
+    case V8::FCMPED:
       return true;
     default:
       return false;
diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td
index d2c679d0a66..3cc43dc1eda 100644
--- a/lib/Target/SparcV8/SparcV8InstrInfo.td
+++ b/lib/Target/SparcV8/SparcV8InstrInfo.td
@@ -163,6 +163,31 @@ def BLEU : BranchV8<0b0100, "bleu">;
 def BCC  : BranchV8<0b1101, "bcc">;
 def BCS  : BranchV8<0b0101, "bcs">;
 
+// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
+
+// floating-point conditional branch class:
+class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> {
+  let isBranch = 1;
+  let isTerminator = 1;
+}
+
+def FBA  : FPBranchV8<0b1000, "fba">;
+def FBN  : FPBranchV8<0b0000, "fbn">;
+def FBU  : FPBranchV8<0b0111, "fbu">;
+def FBG  : FPBranchV8<0b0110, "fbg">;
+def FBUG : FPBranchV8<0b0101, "fbug">;
+def FBL  : FPBranchV8<0b0100, "fbl">;
+def FBUL : FPBranchV8<0b0011, "fbul">;
+def FBLG : FPBranchV8<0b0010, "fblg">;
+def FBNE : FPBranchV8<0b0001, "fbne">;
+def FBE  : FPBranchV8<0b1001, "fbe">;
+def FBUE : FPBranchV8<0b1010, "fbue">;
+def FBGE : FPBranchV8<0b1011, "fbge">;
+def FBUGE: FPBranchV8<0b1100, "fbuge">;
+def FBLE : FPBranchV8<0b1101, "fble">;
+def FBULE: FPBranchV8<0b1110, "fbule">;
+def FBO  : FPBranchV8<0b1111, "fbo">;
+
 // Section B.24 - Call and Link Instruction, p. 125
 // This is the only Format 1 instruction
 def CALL : InstV8 {
@@ -207,3 +232,10 @@ def FSMULD : F3_3<2, 0b110100, 0b001101001, "fsmuld">;
 def FDIVS  : F3_3<2, 0b110100, 0b001001101, "fdivs">;
 def FDIVD  : F3_3<2, 0b110100, 0b001001110, "fdivd">;
 
+// Floating-point Compare Instructions, p. 148
+// Note: the 2nd template arg is different for these guys
+def FCMPS  : F3_3<2, 0b110101, 0b001010001, "fcmps">;
+def FCMPD  : F3_3<2, 0b110101, 0b001010010, "fcmpd">;
+def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">;
+def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">;
+