From: 黄涛 <huangtao@rock-chips.com>
Date: Fri, 10 Dec 2010 10:05:40 +0000 (+0800)
Subject: rk29: L2 cache设置变更。根据IC部的建议，810~972频率，data ram latency设为6 cycles
X-Git-Tag: firefly_0821_release~10953
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=40a1ab5ca92ccda7cdbd88df6942e596c0702611;p=firefly-linux-kernel-4.4.55.git

rk29: L2 cache设置变更。根据IC部的建议，810~972频率，data ram latency设为6 cycles
---

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index f5e368dc0912..9e41985cca25 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -272,7 +272,7 @@ __v7_setup:
 	bic	r5, r5, #7 << 6
 	bic	r5, r5, #15
 	orr	r5, r5, #3 << 6			@ Tag RAM latency: b011 = 4 cycles
-	orr	r5, r5, #4			@ Data RAM latency: b0100 = 5 cycles
+	orr	r5, r5, #5			@ Data RAM latency: b0101 = 6 cycles
 	mcr	p15, 1, r5, c9, c0, 2
 #endif