From: Matheus Almeida Date: Mon, 10 Feb 2014 12:05:17 +0000 (+0000) Subject: [mips][msa] Add DLSA instruction. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=3f14ca5e3027bae10203ea02e716a1a4c6fddf80;p=oota-llvm.git [mips][msa] Add DLSA instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201081 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/IR/IntrinsicsMips.td b/include/llvm/IR/IntrinsicsMips.td index 50c0c278f46..34557612cb9 100644 --- a/include/llvm/IR/IntrinsicsMips.td +++ b/include/llvm/IR/IntrinsicsMips.td @@ -837,6 +837,12 @@ def int_mips_div_u_w : GCCBuiltin<"__builtin_msa_div_u_w">, def int_mips_div_u_d : GCCBuiltin<"__builtin_msa_div_u_d">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>; +// This instruction is part of the MSA spec but it does not share the +// __builtin_msa prefix because it operates on GP registers. +def int_mips_dlsa : GCCBuiltin<"__builtin_mips_dlsa">, + Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty], + [IntrNoMem]>; + def int_mips_dotp_s_h : GCCBuiltin<"__builtin_msa_dotp_s_h">, Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_mips_dotp_s_w : GCCBuiltin<"__builtin_msa_dotp_s_w">, diff --git a/lib/Target/Mips/MipsMSAInstrFormats.td b/lib/Target/Mips/MipsMSAInstrFormats.td index 3942d05914f..6bd0366b52e 100644 --- a/lib/Target/Mips/MipsMSAInstrFormats.td +++ b/lib/Target/Mips/MipsMSAInstrFormats.td @@ -27,6 +27,10 @@ class MSASpecial : MSAInst { let Inst{31-26} = 0b000000; } +class MSA64Special : MSA64Inst { + let Inst{31-26} = 0b000000; +} + class MSAPseudo pattern, InstrItinClass itin = IIPseudo>: MipsPseudo { @@ -445,3 +449,17 @@ class SPECIAL_LSA_FMT minor>: MSASpecial { let Inst{7-6} = sa; let Inst{5-0} = minor; } + +class SPECIAL_DLSA_FMT minor>: MSA64Special { + bits<5> rs; + bits<5> rt; + bits<5> rd; + bits<2> sa; + + let Inst{25-21} = rs; + let Inst{20-16} = rt; + let Inst{15-11} = rd; + let Inst{10-8} = 0b000; + let Inst{7-6} = sa; + let Inst{5-0} = minor; +} diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index 545bfccb88d..b23cfe60056 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -878,6 +878,7 @@ class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>; class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>; class LSA_ENC : SPECIAL_LSA_FMT<0b000101>; +class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>; class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>; class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>; @@ -2324,6 +2325,7 @@ class LSA_DESC_BASE; +class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd>; class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h, MSA128HOpnd>; @@ -3191,6 +3193,7 @@ def LDI_W : LDI_W_ENC, LDI_W_DESC; def LDI_D : LDI_D_ENC, LDI_D_DESC; def LSA : LSA_ENC, LSA_DESC; +def DLSA : DLSA_ENC, DLSA_DESC; def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC; def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC; diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index aa33fab720f..3d3ce0f5721 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -1807,7 +1807,8 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_ldi_w: case Intrinsic::mips_ldi_d: return lowerMSASplatImm(Op, 1, DAG); - case Intrinsic::mips_lsa: { + case Intrinsic::mips_lsa: + case Intrinsic::mips_dlsa: { EVT ResTy = Op->getValueType(0); return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), DAG.getNode(ISD::SHL, SDLoc(Op), ResTy, diff --git a/test/CodeGen/Mips/msa/special.ll b/test/CodeGen/Mips/msa/special.ll index b325c68b6a1..f65a14f7bb1 100644 --- a/test/CodeGen/Mips/msa/special.ll +++ b/test/CodeGen/Mips/msa/special.ll @@ -2,6 +2,8 @@ ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS32 +; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ +; RUN: FileCheck %s --check-prefix=MIPS64 define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind { entry: @@ -25,3 +27,26 @@ entry: ; MIPS32: lsa_test: ; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2 ; MIPS32: .size lsa_test + +define i64 @llvm_mips_dlsa_test(i64 %a, i64 %b) nounwind { +entry: + %0 = tail call i64 @llvm.mips.dlsa(i64 %a, i64 %b, i32 2) + ret i64 %0 +} + +declare i64 @llvm.mips.dlsa(i64, i64, i32) nounwind + +; MIPS64: llvm_mips_dlsa_test: +; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2 +; MIPS64: .size llvm_mips_dlsa_test + +define i64 @dlsa_test(i64 %a, i64 %b) nounwind { +entry: + %0 = shl i64 %b, 2 + %1 = add i64 %a, %0 + ret i64 %1 +} + +; MIPS64: dlsa_test: +; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2 +; MIPS64: .size dlsa_test diff --git a/test/MC/Mips/msa/test_dlsa.s b/test/MC/Mips/msa/test_dlsa.s new file mode 100644 index 00000000000..a70999dc72c --- /dev/null +++ b/test/MC/Mips/msa/test_dlsa.s @@ -0,0 +1,21 @@ +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | \ +# RUN: FileCheck %s +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips64r2 -mattr=+msa -filetype=obj -o - | \ +# RUN: llvm-objdump -d -arch=mips64 -mattr=+msa - | \ +# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP +# +# CHECK: dlsa $8, $9, $10, 1 # encoding: [0x01,0x2a,0x40,0x15] +# CHECK: dlsa $8, $9, $10, 2 # encoding: [0x01,0x2a,0x40,0x55] +# CHECK: dlsa $8, $9, $10, 3 # encoding: [0x01,0x2a,0x40,0x95] +# CHECK: dlsa $8, $9, $10, 4 # encoding: [0x01,0x2a,0x40,0xd5] + +# CHECKOBJDUMP: dlsa $8, $9, $10, 1 +# CHECKOBJDUMP: dlsa $8, $9, $10, 2 +# CHECKOBJDUMP: dlsa $8, $9, $10, 3 +# CHECKOBJDUMP: dlsa $8, $9, $10, 4 + + dlsa $8, $9, $10, 1 + dlsa $8, $9, $10, 2 + dlsa $8, $9, $10, 3 + dlsa $8, $9, $10, 4