From: Misha Brukman Date: Wed, 25 Feb 2004 20:52:20 +0000 (+0000) Subject: SparcV8 has different types of instructions, but F1 is only used for CALL. X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=3dff82298818d2760c0b53b45214bff5dea9fb4a;p=oota-llvm.git SparcV8 has different types of instructions, but F1 is only used for CALL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11832 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Sparc/SparcV8Instrs_F2.td b/lib/Target/Sparc/SparcV8Instrs_F2.td new file mode 100644 index 00000000000..69b0a4e81c5 --- /dev/null +++ b/lib/Target/Sparc/SparcV8Instrs_F2.td @@ -0,0 +1,44 @@ +//===- SparcV8Instrs_F2.td - Format 2 instructions: SparcV8 Target --------===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Format #2 instruction classes in the SparcV8 +// +//===----------------------------------------------------------------------===// + +class F2 : InstV8 { // Format 2 instructions + bits<3> op2; + bits<22> imm22; + let op = 0; // op = 0 + let Inst{24-22} = op2; + let Inst{21-0} = imm22; +} + +// Specific F2 classes: SparcV8 manual, page 44 +// +class F2_1 op2Val, string name> : F2 { + bits<5> rd; + bits<22> imm; + + let op2 = op2Val; + let Name = name; + + let Inst{29-25} = rd; +} + +class F2_2 cond, bits<3> op2Val, string name> : F2 { + bits<4> cond; + bit annul = 0; // currently unused + + let cond = condVal; + let op2 = op2Val; + let Name = name; + + let Inst{29} = annul; + let Inst{28-25} = cond; +} diff --git a/lib/Target/Sparc/SparcV8Instrs_F3.td b/lib/Target/Sparc/SparcV8Instrs_F3.td new file mode 100644 index 00000000000..a19cd34480e --- /dev/null +++ b/lib/Target/Sparc/SparcV8Instrs_F3.td @@ -0,0 +1,61 @@ +//===- SparcV8Instrs_F3.td - Format 3 Instructions: SparcV8 Target --------===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Format #3 instruction classes in the SparcV8 +// +//===----------------------------------------------------------------------===// + +class F3 : InstV8 { + bits<5> rd; + bits<6> op3; + bits<5> rs1; + let op{1} = 1; // Op = 2 or 3 + let Inst{29-25} = rd; + let Inst{24-19} = op3; + let Inst{18-14} = rs1; +} + +// Specific F3 classes: SparcV8 manual, page 44 +// +class F3_1 opVal, bits<6> op3val, string name> : F3 { + bits<8> asi; + bits<5> rs2; + + let op = opVal; + let op3 = op3val; + let Name = name; + + let Inst{13} = 0; // i field = 0 + let Inst{12-5} = asi; // address space identifier + let Inst{4-0} = rs2; +} + +class F3_2 opVal, bits<6> op3val, string name> : F3 { + bits<13> simm13; + + let op = opVal; + let op3 = op3val; + let Name = name; + + let Inst{13} = 1; // i field = 1 + let Inst{12-0} = simm13; +} + +class F3_3 opVal, bits<6> op3val, bits<9> opfVal, string name> + : F3_rs1rs2 { + bits<5> rs2; + + let op = opVal; + let op3 = op3val; + let Name = name; + + let Inst{13-5} = opfVal; + let Inst{4-0} = rs2; +} + diff --git a/lib/Target/SparcV8/SparcV8Instrs_F2.td b/lib/Target/SparcV8/SparcV8Instrs_F2.td new file mode 100644 index 00000000000..69b0a4e81c5 --- /dev/null +++ b/lib/Target/SparcV8/SparcV8Instrs_F2.td @@ -0,0 +1,44 @@ +//===- SparcV8Instrs_F2.td - Format 2 instructions: SparcV8 Target --------===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Format #2 instruction classes in the SparcV8 +// +//===----------------------------------------------------------------------===// + +class F2 : InstV8 { // Format 2 instructions + bits<3> op2; + bits<22> imm22; + let op = 0; // op = 0 + let Inst{24-22} = op2; + let Inst{21-0} = imm22; +} + +// Specific F2 classes: SparcV8 manual, page 44 +// +class F2_1 op2Val, string name> : F2 { + bits<5> rd; + bits<22> imm; + + let op2 = op2Val; + let Name = name; + + let Inst{29-25} = rd; +} + +class F2_2 cond, bits<3> op2Val, string name> : F2 { + bits<4> cond; + bit annul = 0; // currently unused + + let cond = condVal; + let op2 = op2Val; + let Name = name; + + let Inst{29} = annul; + let Inst{28-25} = cond; +} diff --git a/lib/Target/SparcV8/SparcV8Instrs_F3.td b/lib/Target/SparcV8/SparcV8Instrs_F3.td new file mode 100644 index 00000000000..a19cd34480e --- /dev/null +++ b/lib/Target/SparcV8/SparcV8Instrs_F3.td @@ -0,0 +1,61 @@ +//===- SparcV8Instrs_F3.td - Format 3 Instructions: SparcV8 Target --------===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Format #3 instruction classes in the SparcV8 +// +//===----------------------------------------------------------------------===// + +class F3 : InstV8 { + bits<5> rd; + bits<6> op3; + bits<5> rs1; + let op{1} = 1; // Op = 2 or 3 + let Inst{29-25} = rd; + let Inst{24-19} = op3; + let Inst{18-14} = rs1; +} + +// Specific F3 classes: SparcV8 manual, page 44 +// +class F3_1 opVal, bits<6> op3val, string name> : F3 { + bits<8> asi; + bits<5> rs2; + + let op = opVal; + let op3 = op3val; + let Name = name; + + let Inst{13} = 0; // i field = 0 + let Inst{12-5} = asi; // address space identifier + let Inst{4-0} = rs2; +} + +class F3_2 opVal, bits<6> op3val, string name> : F3 { + bits<13> simm13; + + let op = opVal; + let op3 = op3val; + let Name = name; + + let Inst{13} = 1; // i field = 1 + let Inst{12-0} = simm13; +} + +class F3_3 opVal, bits<6> op3val, bits<9> opfVal, string name> + : F3_rs1rs2 { + bits<5> rs2; + + let op = opVal; + let op3 = op3val; + let Name = name; + + let Inst{13-5} = opfVal; + let Inst{4-0} = rs2; +} +