From: Nate Begeman Date: Wed, 27 Jul 2005 23:11:27 +0000 (+0000) Subject: Fix some comments X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=3dee17581c38ce598376e83666c54a6b5d96ef05;p=oota-llvm.git Fix some comments git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22530 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index ee794911d60..a21cf5b83ee 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -1656,9 +1656,6 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { return Result; case ISD::AND: - // FIXME: should add check in getImmediateForOpcode to return a value - // indicating the immediate is a run of set bits so we can emit a bitfield - // clear with RLWINM instead. switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) { default: assert(0 && "unhandled result code"); case 0: // No immediate @@ -1690,6 +1687,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { Tmp3 = Tmp2 >> 16; // MB Tmp2 &= 0xFFFF; // ME + // FIXME: Catch SHL-AND in addition to SRL-AND in this block. if (N.getOperand(0).getOpcode() == ISD::SRL) if (ConstantSDNode *SA = dyn_cast(N.getOperand(0).getOperand(1))) { diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 7977a005001..3493fdc02a1 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -263,7 +263,7 @@ void PPC32RegisterInfo::emitPrologue(MachineFunction &MF) const { // Update frame info to pretend that this is part of the stack... MFI->setStackSize(NumBytes); - // If , adjust stack pointer: r1 -= numbytes. + // Adjust stack pointer: r1 -= numbytes. if (NumBytes <= 32768) { MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1); MBB.insert(MBBI, MI);