From: Evan Cheng <evan.cheng@apple.com>
Date: Wed, 30 May 2012 00:42:02 +0000 (+0000)
Subject: If-converter models predicated defs as read + write. The read should be marked as... 
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=3d4166dff0624b8843338acc156987e8bc890e9b;p=oota-llvm.git

If-converter models predicated defs as read + write. The read should be marked as 'undef' since it may not already be live. This appeases -verify-machineinstrs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157662 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/IfConversion.cpp b/lib/CodeGen/IfConversion.cpp
index 75ae5b9c2c2..00ea3c599f6 100644
--- a/lib/CodeGen/IfConversion.cpp
+++ b/lib/CodeGen/IfConversion.cpp
@@ -993,7 +993,8 @@ static void UpdatePredRedefs(MachineInstr *MI, SmallSet<unsigned,4> &Redefs,
       if (AddImpUse)
         // Treat predicated update as read + write.
         MI->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
-                                                true/*IsImp*/,false/*IsKill*/));
+                                              true/*IsImp*/,false/*IsKill*/,
+                                              false/*IsDead*/,true/*IsUndef*/));
     } else {
       Redefs.insert(Reg);
       for (const uint16_t *SR = TRI->getSubRegisters(Reg); *SR; ++SR)