From: Evan Cheng <evan.cheng@apple.com>
Date: Wed, 19 Jul 2006 05:58:18 +0000 (+0000)
Subject: Make sub- and super- register classes const.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=3b0c0148ed9ec752b240dbea767ad4a9f0a682ca;p=oota-llvm.git

Make sub- and super- register classes const.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29200 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h
index 0cac31bb365..1ca560eab14 100644
--- a/include/llvm/Target/MRegisterInfo.h
+++ b/include/llvm/Target/MRegisterInfo.h
@@ -47,7 +47,7 @@ public:
   typedef const unsigned* const_iterator;
 
   typedef const MVT::ValueType* vt_iterator;
-  typedef const TargetRegisterClass** sc_iterator;
+  typedef const TargetRegisterClass* const * sc_iterator;
 private:
   bool  isSubClass;
   const vt_iterator VTs;
@@ -57,8 +57,8 @@ private:
   const iterator RegsBegin, RegsEnd;
 public:
   TargetRegisterClass(const MVT::ValueType *vts,
-                      const TargetRegisterClass **subcs,
-                      const TargetRegisterClass **supcs,
+                      const TargetRegisterClass * const *subcs,
+                      const TargetRegisterClass * const *supcs,
                       unsigned RS, unsigned Al, iterator RB, iterator RE)
     : VTs(vts), SubClasses(subcs), SuperClasses(supcs),
     RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index 8ed9eefef1f..e572544075d 100644
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -149,8 +149,9 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
     
     // Emit the register list now.
     OS << "  // " << Name 
-      << " Register Class Value Types...\n  const MVT::ValueType " << Name
-      << "[] = {\n    ";
+       << " Register Class Value Types...\n"
+       << "  static const MVT::ValueType " << Name
+       << "[] = {\n    ";
     for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
       OS << RC.VTs[i] << ", ";
     OS << "MVT::Other\n  };\n\n";
@@ -182,7 +183,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
 
       OS << "  // " << Name 
          << " Register Class sub-classes...\n"
-         << "  static const TargetRegisterClass* "
+         << "  static const TargetRegisterClass* const "
          << Name << "Subclasses [] = {\n    ";
 
       bool Empty = true;
@@ -217,7 +218,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
 
       OS << "  // " << Name 
          << " Register Class super-classes...\n"
-         << "  static const TargetRegisterClass* "
+         << "  static const TargetRegisterClass* const "
          << Name << "Superclasses [] = {\n    ";
 
       bool Empty = true;