From: Bill Wendling <isanbard@gmail.com>
Date: Wed, 11 Aug 2010 00:23:00 +0000 (+0000)
Subject: Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds.
X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=38ae997e63e3e1bb2c8679e01ea74cf8fd0be893;p=oota-llvm.git

Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110762 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 5881a121a9d..7e166d52737 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1358,6 +1358,8 @@ bool ARMBaseInstrInfo::
 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpValue) const {
   switch (MI->getOpcode()) {
   default: break;
+  case ARM::CMPri:
+  case ARM::CMPzri:
   case ARM::t2CMPri:
   case ARM::t2CMPzri:
     SrcReg = MI->getOperand(0).getReg();
@@ -1398,6 +1400,9 @@ ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const {
   // Set the "zero" bit in CPSR.
   switch (MI->getOpcode()) {
   default: break;
+  case ARM::ADDri:
+  case ARM::SUBri:
+  case ARM::t2ADDri:
   case ARM::t2SUBri: {
     MI->RemoveOperand(5);
     MachineInstrBuilder MB(MI);