From: Artyom Skrobov Date: Mon, 20 Jan 2014 10:18:42 +0000 (+0000) Subject: [ARM] Do not generate Tag_DIV_use=AllowDIVExt when hardware div is non-optional:... X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=3767c7446edea95277509477a9bb3048ef2e0b95;p=oota-llvm.git [ARM] Do not generate Tag_DIV_use=AllowDIVExt when hardware div is non-optional: it should have the default value of AllowDIVIfExists git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199638 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/Support/ARMBuildAttributes.h b/include/llvm/Support/ARMBuildAttributes.h index ef52ffba085..69732fc041e 100644 --- a/include/llvm/Support/ARMBuildAttributes.h +++ b/include/llvm/Support/ARMBuildAttributes.h @@ -168,9 +168,11 @@ enum { AllowMP = 1, // Allow use of MP extensions // Tag_DIV_use, (=44), uleb128 + // Note: AllowDIVExt must be emitted if and only if the permission to use + // hardware divide cannot be conveyed using AllowDIVIfExists or DisallowDIV AllowDIVIfExists = 0, // Allow hardware divide if available in arch, or no // info exists. - DisallowDIV = 1, // Hardware divide explicitly disallowed + DisallowDIV = 1, // Hardware divide explicitly disallowed. AllowDIVExt = 2, // Allow hardware divide as optional architecture // extension above the base arch specified by // Tag_CPU_arch and Tag_CPU_arch_profile. diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 4701cb44884..f688407d694 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -719,12 +719,14 @@ void ARMAsmPrinter::emitAttributes() { if (Subtarget->hasMPExtension()) ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP); - if (Subtarget->hasDivide()) { - // Check if hardware divide is only available in thumb2 or ARM as well. - ATS.emitAttribute(ARMBuildAttrs::DIV_use, - Subtarget->hasDivideInARMMode() ? ARMBuildAttrs::AllowDIVExt : - ARMBuildAttrs::AllowDIVIfExists); - } + // Hardware divide in ARM mode is part of base arch, starting from ARMv8. + // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M). + // It is not possible to produce DisallowDIV: if hwdiv is present in the base + // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits. + // AllowDIVExt is only emitted if hwdiv isn't available in the base arch; + // otherwise, the default value (AllowDIVIfExists) applies. + if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops()) + ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt); if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization()) ATS.emitAttribute(ARMBuildAttrs::Virtualization_use, diff --git a/test/CodeGen/ARM/build-attributes.ll b/test/CodeGen/ARM/build-attributes.ll index d49a70d932e..013138b3c20 100644 --- a/test/CodeGen/ARM/build-attributes.ll +++ b/test/CodeGen/ARM/build-attributes.ll @@ -23,6 +23,7 @@ ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9-mp | FileCheck %s --check-prefix=CORTEX-A9-MP ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 | FileCheck %s --check-prefix=CORTEX-A15 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0 +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=CORTEX-M3 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-M4-HARD ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5 @@ -85,7 +86,7 @@ ; V7M-NOT: .eabi_attribute 28 ; V7M-NOT: .eabi_attribute 36 ; V7M-NOT: .eabi_attribute 42 -; V7M: .eabi_attribute 44, 0 +; V7M-NOT: .eabi_attribute 44 ; V7M-NOT: .eabi_attribute 68 ; V7: .syntax unified @@ -349,6 +350,23 @@ ; CORTEX-M0-NOT: .eabi_attribute 42 ; CORTEX-M0-NOT: .eabi_attribute 68 +; CORTEX-M3: .cpu cortex-m3 +; CORTEX-M3: .eabi_attribute 6, 10 +; CORTEX-M3: .eabi_attribute 7, 77 +; CORTEX-M3: .eabi_attribute 8, 0 +; CORTEX-M3: .eabi_attribute 9, 2 +; CORTEX-M3: .eabi_attribute 20, 1 +; CORTEX-M3: .eabi_attribute 21, 1 +; CORTEX-M3: .eabi_attribute 23, 3 +; CORTEX-M3: .eabi_attribute 24, 1 +; CORTEX-M3: .eabi_attribute 25, 1 +; CORTEX-M3-NOT: .eabi_attribute 27 +; CORTEX-M3-NOT: .eabi_attribute 28 +; CORTEX-M3-NOT: .eabi_attribute 36 +; CORTEX-M3-NOT: .eabi_attribute 42 +; CORTEX-M3-NOT: .eabi_attribute 44 +; CORTEX-M3-NOT: .eabi_attribute 68 + ; CORTEX-M4-SOFT: .cpu cortex-m4 ; CORTEX-M4-SOFT: .eabi_attribute 6, 13 ; CORTEX-M4-SOFT: .eabi_attribute 7, 77 @@ -364,7 +382,7 @@ ; CORTEX-M4-SOFT-NOT: .eabi_attribute 28 ; CORTEX-M4-SOFT: .eabi_attribute 36, 1 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 42 -; CORTEX-M4-SOFT: .eabi_attribute 44, 0 +; CORTEX-M4-SOFT-NOT: .eabi_attribute 44 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 68 ; CORTEX-M4-HARD: .cpu cortex-m4 @@ -382,7 +400,7 @@ ; CORTEX-M4-HARD: .eabi_attribute 28, 1 ; CORTEX-M4-HARD: .eabi_attribute 36, 1 ; CORTEX-M4-HARD-NOT: .eabi_attribute 42 -; CORTEX-M4-HARD: .eabi_attribute 44, 0 +; CORTEX-M4-HARD-NOT: .eabi_attribute 44 ; CORTEX-M4-HRAD-NOT: .eabi_attribute 68 ; CORTEX-R5: .cpu cortex-r5 @@ -416,7 +434,7 @@ ; CORTEX-A53-NOT: .eabi_attribute 28 ; CORTEX-A53: .eabi_attribute 36, 1 ; CORTEX-A53: .eabi_attribute 42, 1 -; CORTEX-A53: .eabi_attribute 44, 2 +; CORTEX-A53-NOT: .eabi_attribute 44 ; CORTEX-A53: .eabi_attribute 68, 3 ; CORTEX-A57: .cpu cortex-a57 @@ -432,7 +450,7 @@ ; CORTEX-A57-NOT: .eabi_attribute 28 ; CORTEX-A57: .eabi_attribute 36, 1 ; CORTEX-A57: .eabi_attribute 42, 1 -; CORTEX-A57: .eabi_attribute 44, 2 +; CORTEX-A57-NOT: .eabi_attribute 44 ; CORTEX-A57: .eabi_attribute 68, 3 define i32 @f(i64 %z) {