From: Jack Carter Date: Thu, 16 May 2013 19:40:19 +0000 (+0000) Subject: Mips assembler: Add branch macro definitions X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=3209baefd4ab8242563118c37d8357bd9de6b421;p=oota-llvm.git Mips assembler: Add branch macro definitions This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows: bnez $rs,$imm => bne $rs,$zero,$imm beqz $rs,$imm => beq $rs,$zero,$imm The corresponding test cases are added. Patch by Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index fc533fb03f6..3ac7883cc37 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -167,12 +167,12 @@ let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in { /// Jump and Branch Instructions def JR64 : IndirectBranch, MTLO_FM<8>; -def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>; -def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>; -def BGEZ64 : CBranchZero<"bgez", setge, CPU64Regs>, BGEZ_FM<1, 1>; -def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64Regs>, BGEZ_FM<7, 0>; -def BLEZ64 : CBranchZero<"blez", setle, CPU64Regs>, BGEZ_FM<6, 0>; -def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>; +def BEQ64 : CBranch<"beq", seteq, CPU64RegsOpnd>, BEQ_FM<4>; +def BNE64 : CBranch<"bne", setne, CPU64RegsOpnd>, BEQ_FM<5>; +def BGEZ64 : CBranchZero<"bgez", setge, CPU64RegsOpnd>, BGEZ_FM<1, 1>; +def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64RegsOpnd>, BGEZ_FM<7, 0>; +def BLEZ64 : CBranchZero<"blez", setle, CPU64RegsOpnd>, BGEZ_FM<6, 0>; +def BLTZ64 : CBranchZero<"bltz", setlt, CPU64RegsOpnd>, BGEZ_FM<1, 0>; } let DecoderNamespace = "Mips64" in def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM; @@ -361,8 +361,14 @@ def : InstAlias<"dadd $rs, $rt, $imm", def : InstAlias<"or $rs, $rt, $imm", (ORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm), 1>, Requires<[HasMips64]>; -/// Move between CPU and coprocessor registers +def : InstAlias<"bnez $rs,$offset", + (BNE64 CPU64RegsOpnd:$rs, ZERO_64, brtarget:$offset), 1>, + Requires<[HasMips64]>; +def : InstAlias<"beqz $rs,$offset", + (BEQ64 CPU64RegsOpnd:$rs, ZERO_64, brtarget:$offset), 1>, + Requires<[HasMips64]>; +/// Move between CPU and coprocessor registers let DecoderNamespace = "Mips64" in { def DMFC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt), (ins CPU64RegsOpnd:$rd, uimm16:$sel), diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 5ada1df2671..7515a6330a8 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -521,7 +521,7 @@ multiclass StoreLeftRightM { } // Conditional Branch -class CBranch : +class CBranch : InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), !strconcat(opstr, "\t$rs, $rt, $offset"), [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, @@ -532,7 +532,7 @@ class CBranch : let Defs = [AT]; } -class CBranchZero : +class CBranchZero : InstSE<(outs), (ins RC:$rs, brtarget:$offset), !strconcat(opstr, "\t$rs, $offset"), [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { @@ -940,12 +940,12 @@ def J : JumpFJ, FJ<2>, Requires<[RelocStatic, HasStdEnc]>, IsBranch; def JR : IndirectBranch, MTLO_FM<8>; def B : UncondBranch<"b">, B_FM; -def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; -def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; -def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; -def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; -def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; -def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; +def BEQ : CBranch<"beq", seteq, CPURegsOpnd>, BEQ_FM<4>; +def BNE : CBranch<"bne", setne, CPURegsOpnd>, BEQ_FM<5>; +def BGEZ : CBranchZero<"bgez", setge, CPURegsOpnd>, BGEZ_FM<1, 1>; +def BGTZ : CBranchZero<"bgtz", setgt, CPURegsOpnd>, BGEZ_FM<7, 0>; +def BLEZ : CBranchZero<"blez", setle, CPURegsOpnd>, BGEZ_FM<6, 0>; +def BLTZ : CBranchZero<"bltz", setlt, CPURegsOpnd>, BGEZ_FM<1, 0>; def BAL_BR: BAL_FT, BAL_FM; @@ -1097,6 +1097,12 @@ def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; def : InstAlias<"addiu $rs, $imm", (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rs, simm16:$imm), 0>; +def : InstAlias<"bnez $rs,$offset", + (BNE CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>, + Requires<[NotMips64]>; +def : InstAlias<"beqz $rs,$offset", + (BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>, + Requires<[NotMips64]>; //===----------------------------------------------------------------------===// // Assembler Pseudo Instructions //===----------------------------------------------------------------------===// diff --git a/test/MC/Mips/mips-jump-instructions.s b/test/MC/Mips/mips-jump-instructions.s index 597f6872d60..bfc052c9ce4 100644 --- a/test/MC/Mips/mips-jump-instructions.s +++ b/test/MC/Mips/mips-jump-instructions.s @@ -26,7 +26,11 @@ # CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK32: bne $9, $6, 1332 # encoding: [0x4d,0x01,0x26,0x15] # CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK32: bal 1332 # encoding: [0x4d,0x01,0x11,0x04] +# CHECK32: bal 1332 # encoding: [0x4d,0x01,0x11,0x04] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: bne $11, $zero, 1332 # encoding: [0x4d,0x01,0x60,0x15] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: beq $11, $zero, 1332 # encoding: [0x4d,0x01,0x60,0x11] # CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK64: b 1332 # encoding: [0x4d,0x01,0x00,0x10] @@ -49,6 +53,10 @@ # CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK64: bal 1332 # encoding: [0x4d,0x01,0x11,0x04] # CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: bne $11, $zero, 1332 # encoding: [0x4d,0x01,0x60,0x15] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: beq $11, $zero, 1332 # encoding: [0x4d,0x01,0x60,0x11] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] .set noreorder @@ -72,6 +80,10 @@ nop bal 1332 nop + bnez $11,1332 + nop + beqz $11,1332 + nop end_of_code: #------------------------------------------------------------------------------