From: Bill Wendling Date: Sun, 20 Jul 2008 02:32:23 +0000 (+0000) Subject: Fix for first part of PR2562. Generate the "pinsrw" instruction for inserts X-Git-Url: http://plrg.eecs.uci.edu/git/?a=commitdiff_plain;h=3180e20cda2150a3fc694b3713cae4c5f2fda49f;p=oota-llvm.git Fix for first part of PR2562. Generate the "pinsrw" instruction for inserts into v4i16 vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53807 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 8bfa574fb79..85788ef90c7 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -604,6 +604,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); + + setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); } if (Subtarget->hasSSE1()) { diff --git a/test/CodeGen/X86/mmx-pinsrw.ll b/test/CodeGen/X86/mmx-pinsrw.ll new file mode 100644 index 00000000000..f1d04fa46ca --- /dev/null +++ b/test/CodeGen/X86/mmx-pinsrw.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep pinsrw | count 1 +; PR2562 + +external global i16 ; :0 [#uses=1] +external global <4 x i16> ; <<4 x i16>*>:1 [#uses=2] + +declare void @abort() + +define void @""() { + load i16* @0 ; :1 [#uses=1] + load <4 x i16>* @1 ; <<4 x i16>>:2 [#uses=1] + insertelement <4 x i16> %2, i16 %1, i32 0 ; <<4 x i16>>:3 [#uses=1] + store <4 x i16> %3, <4 x i16>* @1 + ret void +}